2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/thread_state.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/thread_context.hh"
40 #include "arch/kernel_stats.hh"
42 class EndQuiesceEvent;
48 * Derived ThreadContext class for use with the InOrderCPU. It
49 * provides the interface for any external objects to access a
50 * single thread's state and some general CPU state. Any time
51 * external objects try to update state through this interface,
52 * the CPU will create an event to squash all in-flight
53 * instructions in order to ensure state is maintained correctly.
54 * It must be defined specifically for the InOrderCPU because
55 * not all architectural state is located within the O3ThreadState
56 * (such as the commit PC, and registers), and specific actions
57 * must be taken when using this interface (such as squashing all
58 * in-flight instructions when doing a write to this interface).
60 class InOrderThreadContext : public ThreadContext
63 InOrderThreadContext() { }
65 /** Pointer to the CPU. */
68 /** Pointer to the thread state that this TC corrseponds to. */
69 InOrderThreadState *thread;
71 /** Returns a pointer to the ITB. */
72 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
73 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
75 /** Returns a pointer to the DTB. */
76 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
77 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
79 Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
81 System *getSystemPtr() { return cpu->system; }
83 /** Returns a pointer to this CPU. */
84 BaseCPU *getCpuPtr() { return cpu; }
86 /** Returns a pointer to this CPU. */
87 std::string getCpuName() { return cpu->name(); }
89 /** Reads this CPU's ID. */
90 int cpuId() { return cpu->cpuId(); }
92 int contextId() { return thread->contextId(); }
94 void setContextId(int id) { thread->setContextId(id); }
96 /** Returns this thread's ID number. */
97 int threadId() { return thread->threadId(); }
98 void setThreadId(int id) { return thread->setThreadId(id); }
100 uint64_t readMicroPC()
103 void setMicroPC(uint64_t val) { };
105 uint64_t readNextMicroPC()
108 void setNextMicroPC(uint64_t val) { };
110 /** Returns a pointer to physical memory. */
111 PhysicalMemory *getPhysMemPtr()
112 { assert(0); return 0; /*return cpu->physmem;*/ }
114 /** Returns a pointer to this thread's kernel statistics. */
115 TheISA::Kernel::Statistics *getKernelStats()
116 { return thread->kernelStats; }
118 PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
120 FSTranslatingPortProxy* getVirtProxy();
122 void initMemProxies(ThreadContext *tc)
123 { thread->initMemProxies(tc); }
125 /** Dumps the function profiling information.
128 void dumpFuncProfile();
130 /** Reads the last tick that this thread was activated on. */
131 Tick readLastActivate();
132 /** Reads the last tick that this thread was suspended on. */
133 Tick readLastSuspend();
135 /** Clears the function profiling information. */
138 /** Samples the function profiling information. */
139 void profileSample();
141 /** Returns pointer to the quiesce event. */
142 EndQuiesceEvent *getQuiesceEvent()
144 return this->thread->quiesceEvent;
147 SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
149 /** Returns a pointer to this thread's process. */
150 Process *getProcessPtr() { return thread->getProcessPtr(); }
152 /** Returns this thread's status. */
153 Status status() const { return thread->status(); }
155 /** Sets this thread's status. */
156 void setStatus(Status new_status)
157 { thread->setStatus(new_status); }
159 /** Set the status to Active. Optional delay indicates number of
160 * cycles to wait before beginning execution. */
161 void activate(int delay = 1);
163 /** Set the status to Suspended. */
164 void suspend(int delay = 0);
166 /** Set the status to Halted. */
167 void halt(int delay = 0);
169 /** Takes over execution of a thread from another CPU. */
170 void takeOverFrom(ThreadContext *old_context);
172 /** Registers statistics associated with this TC. */
173 void regStats(const std::string &name);
175 /** Serializes state. */
176 void serialize(std::ostream &os);
178 /** Unserializes state. */
179 void unserialize(Checkpoint *cp, const std::string §ion);
181 /** Returns this thread's ID number. */
182 int getThreadNum() { return thread->threadId(); }
184 /** Copies the architectural registers from another TC into this TC. */
185 void copyArchRegs(ThreadContext *src_tc);
187 /** Resets all architectural registers to 0. */
188 void clearArchRegs();
190 /** Reads an integer register. */
191 uint64_t readIntReg(int reg_idx);
193 FloatReg readFloatReg(int reg_idx);
195 FloatRegBits readFloatRegBits(int reg_idx);
197 uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
199 /** Sets an integer register to a value. */
200 void setIntReg(int reg_idx, uint64_t val);
202 void setFloatReg(int reg_idx, FloatReg val);
204 void setFloatRegBits(int reg_idx, FloatRegBits val);
206 void setRegOtherThread(int misc_reg,
210 /** Reads this thread's PC. */
211 TheISA::PCState pcState()
212 { return cpu->pcState(thread->threadId()); }
214 /** Sets this thread's PC. */
215 void pcState(const TheISA::PCState &val)
216 { cpu->pcState(val, thread->threadId()); }
219 { return cpu->instAddr(thread->threadId()); }
222 { return cpu->nextInstAddr(thread->threadId()); }
225 { return cpu->microPC(thread->threadId()); }
227 /** Reads a miscellaneous register. */
228 MiscReg readMiscRegNoEffect(int misc_reg)
229 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
231 /** Reads a misc. register, including any side-effects the
232 * read might have as defined by the architecture. */
233 MiscReg readMiscReg(int misc_reg)
234 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
236 /** Sets a misc. register. */
237 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
239 /** Sets a misc. register, including any side-effects the
240 * write might have as defined by the architecture. */
241 void setMiscReg(int misc_reg, const MiscReg &val);
243 int flattenIntIndex(int reg)
244 { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
246 int flattenFloatIndex(int reg)
247 { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
249 void activateContext(int delay)
250 { cpu->activateContext(thread->threadId(), delay); }
252 void deallocateContext()
253 { cpu->deallocateContext(thread->threadId()); }
255 /** Returns the number of consecutive store conditional failures. */
256 // @todo: Figure out where these store cond failures should go.
257 unsigned readStCondFailures()
258 { return thread->storeCondFailures; }
260 /** Sets the number of consecutive store conditional failures. */
261 void setStCondFailures(unsigned sc_failures)
262 { thread->storeCondFailures = sc_failures; }
264 // Only really makes sense for old CPU model. Lots of code
265 // outside the CPU still checks this function, so it will
266 // always return false to keep everything working.
267 /** Checks if the thread is misspeculating. Because it is
268 * very difficult to determine if the thread is
269 * misspeculating, this is set as false. */
270 bool misspeculating() { return false; }
272 /** Executes a syscall in SE mode. */
273 void syscall(int64_t callnum)
274 { return cpu->syscall(callnum, thread->threadId()); }
276 /** Reads the funcExeInst counter. */
277 Counter readFuncExeInst() { return thread->funcExeInst; }
279 void changeRegFileContext(unsigned param,
281 { panic("Not supported!"); }