2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/exetrace.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/inorder/thread_state.hh"
39 #include "cpu/inorder/cpu.hh"
41 class TranslatingPort;
44 * Derived ThreadContext class for use with the InOrderCPU. It
45 * provides the interface for any external objects to access a
46 * single thread's state and some general CPU state. Any time
47 * external objects try to update state through this interface,
48 * the CPU will create an event to squash all in-flight
49 * instructions in order to ensure state is maintained correctly.
50 * It must be defined specifically for the InOrderCPU because
51 * not all architectural state is located within the O3ThreadState
52 * (such as the commit PC, and registers), and specific actions
53 * must be taken when using this interface (such as squashing all
54 * in-flight instructions when doing a write to this interface).
56 class InOrderThreadContext : public ThreadContext
59 InOrderThreadContext() { }
61 /** Pointer to the CPU. */
64 /** Pointer to the thread state that this TC corrseponds to. */
65 InOrderThreadState *thread;
67 /** Returns a pointer to the ITB. */
68 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
69 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
71 /** Returns a pointer to the DTB. */
72 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
73 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
75 System *getSystemPtr() { return cpu->system; }
77 /** Returns a pointer to this CPU. */
78 virtual BaseCPU *getCpuPtr() { return cpu; }
80 /** Returns a pointer to this CPU. */
81 virtual std::string getCpuName() { return cpu->name(); }
83 /** Reads this CPU's ID. */
84 virtual int cpuId() { return cpu->cpuId(); }
86 virtual int contextId() { return thread->contextId(); }
88 virtual void setContextId(int id) { thread->setContextId(id); }
90 /** Returns this thread's ID number. */
91 virtual int threadId() { return thread->threadId(); }
92 virtual void setThreadId(int id) { return thread->setThreadId(id); }
94 virtual uint64_t readMicroPC()
97 virtual void setMicroPC(uint64_t val) { };
99 virtual uint64_t readNextMicroPC()
102 virtual void setNextMicroPC(uint64_t val) { };
105 /** Returns a pointer to physical memory. */
106 virtual PhysicalMemory *getPhysMemPtr()
107 { assert(0); return 0; /*return cpu->physmem;*/ }
109 /** Returns a pointer to this thread's kernel statistics. */
110 virtual TheISA::Kernel::Statistics *getKernelStats()
111 { return thread->kernelStats; }
113 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
115 virtual VirtualPort *getVirtPort();
117 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
119 /** Dumps the function profiling information.
122 virtual void dumpFuncProfile();
124 /** Reads the last tick that this thread was activated on. */
125 virtual Tick readLastActivate();
126 /** Reads the last tick that this thread was suspended on. */
127 virtual Tick readLastSuspend();
129 /** Clears the function profiling information. */
130 virtual void profileClear();
132 /** Samples the function profiling information. */
133 virtual void profileSample();
135 /** Returns pointer to the quiesce event. */
136 virtual EndQuiesceEvent *getQuiesceEvent()
138 return this->thread->quiesceEvent;
141 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
143 /** Returns a pointer to this thread's process. */
144 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
147 /** Returns this thread's status. */
148 virtual Status status() const { return thread->status(); }
150 /** Sets this thread's status. */
151 virtual void setStatus(Status new_status)
152 { thread->setStatus(new_status); }
154 /** Set the status to Active. Optional delay indicates number of
155 * cycles to wait before beginning execution. */
156 virtual void activate(int delay = 1);
158 /** Set the status to Suspended. */
159 virtual void suspend(int delay = 0);
161 /** Set the status to Halted. */
162 virtual void halt(int delay = 0);
164 /** Takes over execution of a thread from another CPU. */
165 virtual void takeOverFrom(ThreadContext *old_context);
167 /** Registers statistics associated with this TC. */
168 virtual void regStats(const std::string &name);
170 /** Serializes state. */
171 virtual void serialize(std::ostream &os);
173 /** Unserializes state. */
174 virtual void unserialize(Checkpoint *cp, const std::string §ion);
176 /** Returns this thread's ID number. */
177 virtual int getThreadNum() { return thread->readTid(); }
179 /** Returns the instruction this thread is currently committing.
180 * Only used when an instruction faults.
182 virtual TheISA::MachInst getInst();
184 /** Copies the architectural registers from another TC into this TC. */
185 virtual void copyArchRegs(ThreadContext *src_tc);
187 /** Resets all architectural registers to 0. */
188 virtual void clearArchRegs();
190 /** Reads an integer register. */
191 virtual uint64_t readIntReg(int reg_idx);
193 virtual FloatReg readFloatReg(int reg_idx);
195 virtual FloatRegBits readFloatRegBits(int reg_idx);
197 virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
199 /** Sets an integer register to a value. */
200 virtual void setIntReg(int reg_idx, uint64_t val);
202 virtual void setFloatReg(int reg_idx, FloatReg val);
204 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
206 virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
209 /** Reads this thread's PC. */
210 virtual uint64_t readPC()
211 { return cpu->readPC(thread->readTid()); }
213 /** Sets this thread's PC. */
214 virtual void setPC(uint64_t val);
216 /** Reads this thread's next PC. */
217 virtual uint64_t readNextPC()
218 { return cpu->readNextPC(thread->readTid()); }
220 /** Sets this thread's next PC. */
221 virtual void setNextPC(uint64_t val);
223 virtual uint64_t readNextNPC()
224 { return cpu->readNextNPC(thread->readTid()); }
226 virtual void setNextNPC(uint64_t val);
228 /** Reads a miscellaneous register. */
229 virtual MiscReg readMiscRegNoEffect(int misc_reg)
230 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
232 /** Reads a misc. register, including any side-effects the
233 * read might have as defined by the architecture. */
234 virtual MiscReg readMiscReg(int misc_reg)
235 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
237 /** Sets a misc. register. */
238 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
240 /** Sets a misc. register, including any side-effects the
241 * write might have as defined by the architecture. */
242 virtual void setMiscReg(int misc_reg, const MiscReg &val);
244 virtual int flattenIntIndex(int reg)
245 { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
247 virtual int flattenFloatIndex(int reg)
248 { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
250 virtual void activateContext(int delay)
251 { cpu->activateContext(thread->readTid(), delay); }
253 virtual void deallocateContext()
254 { cpu->deallocateContext(thread->readTid()); }
256 /** Returns the number of consecutive store conditional failures. */
257 // @todo: Figure out where these store cond failures should go.
258 virtual unsigned readStCondFailures()
259 { return thread->storeCondFailures; }
261 /** Sets the number of consecutive store conditional failures. */
262 virtual void setStCondFailures(unsigned sc_failures)
263 { thread->storeCondFailures = sc_failures; }
265 // Only really makes sense for old CPU model. Lots of code
266 // outside the CPU still checks this function, so it will
267 // always return false to keep everything working.
268 /** Checks if the thread is misspeculating. Because it is
269 * very difficult to determine if the thread is
270 * misspeculating, this is set as false. */
271 virtual bool misspeculating() { return false; }
274 /** Executes a syscall in SE mode. */
275 virtual void syscall(int64_t callnum)
276 { return cpu->syscall(callnum, thread->readTid()); }
279 /** Reads the funcExeInst counter. */
280 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
282 virtual void changeRegFileContext(unsigned param,
284 { panic("Not supported!"); }