2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/exetrace.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/inorder/thread_state.hh"
39 #include "cpu/inorder/cpu.hh"
41 class TranslatingPort;
44 * Derived ThreadContext class for use with the InOrderCPU. It
45 * provides the interface for any external objects to access a
46 * single thread's state and some general CPU state. Any time
47 * external objects try to update state through this interface,
48 * the CPU will create an event to squash all in-flight
49 * instructions in order to ensure state is maintained correctly.
50 * It must be defined specifically for the InOrderCPU because
51 * not all architectural state is located within the O3ThreadState
52 * (such as the commit PC, and registers), and specific actions
53 * must be taken when using this interface (such as squashing all
54 * in-flight instructions when doing a write to this interface).
56 class InOrderThreadContext : public ThreadContext
59 InOrderThreadContext() { }
61 /** Pointer to the CPU. */
64 /** Pointer to the thread state that this TC corrseponds to. */
65 InOrderThreadState *thread;
68 /** Returns a pointer to the ITB. */
69 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
70 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
72 /** Returns a pointer to the DTB. */
73 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
74 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
76 System *getSystemPtr() { return cpu->system; }
78 /** Returns a pointer to this CPU. */
79 virtual BaseCPU *getCpuPtr() { return cpu; }
81 /** Returns a pointer to this CPU. */
82 virtual std::string getCpuName() { return cpu->name(); }
84 /** Reads this CPU's ID. */
85 virtual int cpuId() { return cpu->cpuId(); }
87 virtual int contextId() { return thread->contextId(); }
89 virtual void setContextId(int id) { thread->setContextId(id); }
91 /** Returns this thread's ID number. */
92 virtual int threadId() { return thread->threadId(); }
93 virtual void setThreadId(int id) { return thread->setThreadId(id); }
95 virtual uint64_t readMicroPC()
98 virtual void setMicroPC(uint64_t val) { };
100 virtual uint64_t readNextMicroPC()
103 virtual void setNextMicroPC(uint64_t val) { };
106 /** Returns a pointer to physical memory. */
107 virtual PhysicalMemory *getPhysMemPtr()
108 { assert(0); return 0; /*return cpu->physmem;*/ }
110 /** Returns a pointer to this thread's kernel statistics. */
111 virtual TheISA::Kernel::Statistics *getKernelStats()
112 { return thread->kernelStats; }
114 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
116 virtual VirtualPort *getVirtPort();
118 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
120 /** Dumps the function profiling information.
123 virtual void dumpFuncProfile();
125 /** Reads the last tick that this thread was activated on. */
126 virtual Tick readLastActivate();
127 /** Reads the last tick that this thread was suspended on. */
128 virtual Tick readLastSuspend();
130 /** Clears the function profiling information. */
131 virtual void profileClear();
133 /** Samples the function profiling information. */
134 virtual void profileSample();
136 /** Returns pointer to the quiesce event. */
137 virtual EndQuiesceEvent *getQuiesceEvent()
139 return this->thread->quiesceEvent;
142 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
144 /** Returns a pointer to this thread's process. */
145 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
148 /** Returns this thread's status. */
149 virtual Status status() const { return thread->status(); }
151 /** Sets this thread's status. */
152 virtual void setStatus(Status new_status)
153 { thread->setStatus(new_status); }
155 /** Set the status to Active. Optional delay indicates number of
156 * cycles to wait before beginning execution. */
157 virtual void activate(int delay = 1);
159 /** Set the status to Suspended. */
160 virtual void suspend(int delay = 0);
162 /** Set the status to Halted. */
163 virtual void halt(int delay = 0);
165 /** Takes over execution of a thread from another CPU. */
166 virtual void takeOverFrom(ThreadContext *old_context);
168 /** Registers statistics associated with this TC. */
169 virtual void regStats(const std::string &name);
171 /** Serializes state. */
172 virtual void serialize(std::ostream &os);
174 /** Unserializes state. */
175 virtual void unserialize(Checkpoint *cp, const std::string §ion);
177 /** Returns this thread's ID number. */
178 virtual int getThreadNum() { return thread->readTid(); }
180 /** Returns the instruction this thread is currently committing.
181 * Only used when an instruction faults.
183 virtual TheISA::MachInst getInst();
185 /** Copies the architectural registers from another TC into this TC. */
186 virtual void copyArchRegs(ThreadContext *src_tc);
188 /** Resets all architectural registers to 0. */
189 virtual void clearArchRegs();
191 /** Reads an integer register. */
192 virtual uint64_t readIntReg(int reg_idx);
194 virtual FloatReg readFloatReg(int reg_idx);
196 virtual FloatRegBits readFloatRegBits(int reg_idx);
198 virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
200 /** Sets an integer register to a value. */
201 virtual void setIntReg(int reg_idx, uint64_t val);
203 virtual void setFloatReg(int reg_idx, FloatReg val);
205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
207 virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
210 /** Reads this thread's PC. */
211 virtual uint64_t readPC()
212 { return cpu->readPC(thread->readTid()); }
214 /** Sets this thread's PC. */
215 virtual void setPC(uint64_t val);
217 /** Reads this thread's next PC. */
218 virtual uint64_t readNextPC()
219 { return cpu->readNextPC(thread->readTid()); }
221 /** Sets this thread's next PC. */
222 virtual void setNextPC(uint64_t val);
224 virtual uint64_t readNextNPC()
225 { return cpu->readNextNPC(thread->readTid()); }
227 virtual void setNextNPC(uint64_t val);
229 /** Reads a miscellaneous register. */
230 virtual MiscReg readMiscRegNoEffect(int misc_reg)
231 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
233 /** Reads a misc. register, including any side-effects the
234 * read might have as defined by the architecture. */
235 virtual MiscReg readMiscReg(int misc_reg)
236 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
238 /** Sets a misc. register. */
239 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
241 /** Sets a misc. register, including any side-effects the
242 * write might have as defined by the architecture. */
243 virtual void setMiscReg(int misc_reg, const MiscReg &val);
245 virtual int flattenIntIndex(int reg)
246 { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
248 virtual int flattenFloatIndex(int reg)
249 { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
251 virtual void activateContext(int delay)
252 { cpu->activateContext(thread->readTid(), delay); }
254 virtual void deallocateContext()
255 { cpu->deallocateContext(thread->readTid()); }
257 /** Returns the number of consecutive store conditional failures. */
258 // @todo: Figure out where these store cond failures should go.
259 virtual unsigned readStCondFailures()
260 { return thread->storeCondFailures; }
262 /** Sets the number of consecutive store conditional failures. */
263 virtual void setStCondFailures(unsigned sc_failures)
264 { thread->storeCondFailures = sc_failures; }
266 // Only really makes sense for old CPU model. Lots of code
267 // outside the CPU still checks this function, so it will
268 // always return false to keep everything working.
269 /** Checks if the thread is misspeculating. Because it is
270 * very difficult to determine if the thread is
271 * misspeculating, this is set as false. */
272 virtual bool misspeculating() { return false; }
275 /** Executes a syscall in SE mode. */
276 virtual void syscall(int64_t callnum)
277 { return cpu->syscall(callnum, thread->readTid()); }
280 /** Reads the funcExeInst counter. */
281 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
283 virtual void changeRegFileContext(unsigned param,
285 { panic("Not supported!"); }