2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/thread_state.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/thread_context.hh"
40 #include "arch/kernel_stats.hh"
42 class EndQuiesceEvent;
49 * Derived ThreadContext class for use with the InOrderCPU. It
50 * provides the interface for any external objects to access a
51 * single thread's state and some general CPU state. Any time
52 * external objects try to update state through this interface,
53 * the CPU will create an event to squash all in-flight
54 * instructions in order to ensure state is maintained correctly.
55 * It must be defined specifically for the InOrderCPU because
56 * not all architectural state is located within the O3ThreadState
57 * (such as the commit PC, and registers), and specific actions
58 * must be taken when using this interface (such as squashing all
59 * in-flight instructions when doing a write to this interface).
61 class InOrderThreadContext : public ThreadContext
64 InOrderThreadContext() { }
66 /** Pointer to the CPU. */
69 /** Pointer to the thread state that this TC corrseponds to. */
70 InOrderThreadState *thread;
72 /** Returns a pointer to the ITB. */
73 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
74 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
76 /** Returns a pointer to the DTB. */
77 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
78 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
80 /** Currently InOrder model does not support CheckerCPU, this is
81 * merely here for supporting compilation of gem5 with the Checker
84 CheckerCPU *getCheckerCpuPtr() { return NULL; }
86 TheISA::Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
88 System *getSystemPtr() { return cpu->system; }
90 /** Returns a pointer to this CPU. */
91 BaseCPU *getCpuPtr() { return cpu; }
93 /** Returns a pointer to this CPU. */
94 std::string getCpuName() { return cpu->name(); }
96 /** Reads this CPU's ID. */
97 int cpuId() { return cpu->cpuId(); }
99 int contextId() { return thread->contextId(); }
101 void setContextId(int id) { thread->setContextId(id); }
103 /** Returns this thread's ID number. */
104 int threadId() { return thread->threadId(); }
105 void setThreadId(int id) { return thread->setThreadId(id); }
107 uint64_t readMicroPC()
110 void setMicroPC(uint64_t val) { };
112 uint64_t readNextMicroPC()
115 void setNextMicroPC(uint64_t val) { };
117 /** Returns a pointer to this thread's kernel statistics. */
118 TheISA::Kernel::Statistics *getKernelStats()
119 { return thread->kernelStats; }
121 PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
123 FSTranslatingPortProxy &getVirtProxy();
125 void initMemProxies(ThreadContext *tc)
126 { thread->initMemProxies(tc); }
128 /** Dumps the function profiling information.
131 void dumpFuncProfile();
133 /** Reads the last tick that this thread was activated on. */
134 Tick readLastActivate();
135 /** Reads the last tick that this thread was suspended on. */
136 Tick readLastSuspend();
138 /** Clears the function profiling information. */
141 /** Samples the function profiling information. */
142 void profileSample();
144 /** Returns pointer to the quiesce event. */
145 EndQuiesceEvent *getQuiesceEvent()
147 return this->thread->quiesceEvent;
150 SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
152 /** Returns a pointer to this thread's process. */
153 Process *getProcessPtr() { return thread->getProcessPtr(); }
155 /** Returns this thread's status. */
156 Status status() const { return thread->status(); }
158 /** Sets this thread's status. */
159 void setStatus(Status new_status)
160 { thread->setStatus(new_status); }
162 /** Set the status to Active. Optional delay indicates number of
163 * cycles to wait before beginning execution. */
164 void activate(int delay = 1);
166 /** Set the status to Suspended. */
167 void suspend(int delay = 0);
169 /** Set the status to Halted. */
170 void halt(int delay = 0);
172 /** Takes over execution of a thread from another CPU. */
173 void takeOverFrom(ThreadContext *old_context);
175 /** Registers statistics associated with this TC. */
176 void regStats(const std::string &name);
178 /** Serializes state. */
179 void serialize(std::ostream &os);
181 /** Unserializes state. */
182 void unserialize(Checkpoint *cp, const std::string §ion);
184 /** Returns this thread's ID number. */
185 int getThreadNum() { return thread->threadId(); }
187 /** Copies the architectural registers from another TC into this TC. */
188 void copyArchRegs(ThreadContext *src_tc);
190 /** Resets all architectural registers to 0. */
191 void clearArchRegs();
193 /** Reads an integer register. */
194 uint64_t readIntReg(int reg_idx);
196 FloatReg readFloatReg(int reg_idx);
198 FloatRegBits readFloatRegBits(int reg_idx);
200 uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
202 /** Sets an integer register to a value. */
203 void setIntReg(int reg_idx, uint64_t val);
205 void setFloatReg(int reg_idx, FloatReg val);
207 void setFloatRegBits(int reg_idx, FloatRegBits val);
209 void setRegOtherThread(int misc_reg,
213 /** Reads this thread's PC. */
214 TheISA::PCState pcState()
215 { return cpu->pcState(thread->threadId()); }
217 /** Sets this thread's PC. */
218 void pcState(const TheISA::PCState &val)
219 { cpu->pcState(val, thread->threadId()); }
221 /** Needs to be implemented for future CheckerCPU support.
222 * See O3CPU for examples on how to integrate Checker.
224 void pcStateNoRecord(const TheISA::PCState &val)
228 { return cpu->instAddr(thread->threadId()); }
231 { return cpu->nextInstAddr(thread->threadId()); }
234 { return cpu->microPC(thread->threadId()); }
236 /** Reads a miscellaneous register. */
237 MiscReg readMiscRegNoEffect(int misc_reg)
238 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
240 /** Reads a misc. register, including any side-effects the
241 * read might have as defined by the architecture. */
242 MiscReg readMiscReg(int misc_reg)
243 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
245 /** Sets a misc. register. */
246 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
248 /** Sets a misc. register, including any side-effects the
249 * write might have as defined by the architecture. */
250 void setMiscReg(int misc_reg, const MiscReg &val);
252 int flattenIntIndex(int reg)
253 { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
255 int flattenFloatIndex(int reg)
256 { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
258 void activateContext(int delay)
259 { cpu->activateContext(thread->threadId(), delay); }
261 void deallocateContext()
262 { cpu->deallocateContext(thread->threadId()); }
264 /** Returns the number of consecutive store conditional failures. */
265 // @todo: Figure out where these store cond failures should go.
266 unsigned readStCondFailures()
267 { return thread->storeCondFailures; }
269 /** Sets the number of consecutive store conditional failures. */
270 void setStCondFailures(unsigned sc_failures)
271 { thread->storeCondFailures = sc_failures; }
273 // Only really makes sense for old CPU model. Lots of code
274 // outside the CPU still checks this function, so it will
275 // always return false to keep everything working.
276 /** Checks if the thread is misspeculating. Because it is
277 * very difficult to determine if the thread is
278 * misspeculating, this is set as false. */
279 bool misspeculating() { return false; }
281 /** Executes a syscall in SE mode. */
282 void syscall(int64_t callnum)
283 { return cpu->syscall(callnum, thread->threadId()); }
285 /** Reads the funcExeInst counter. */
286 Counter readFuncExeInst() { return thread->funcExeInst; }
288 void changeRegFileContext(unsigned param,
290 { panic("Not supported!"); }