src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  34
  35 #include "cpu/exetrace.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/inorder/thread_state.hh"
  38 #include "cpu/inorder/cpu.hh"
  39
  40 class TranslatingPort;
  41
  42 /**
  43  * Derived ThreadContext class for use with the InOrderCPU.  It
  44  * provides the interface for any external objects to access a
  45  * single thread's state and some general CPU state.  Any time
  46  * external objects try to update state through this interface,
  47  * the CPU will create an event to squash all in-flight
  48  * instructions in order to ensure state is maintained correctly.
  49  * It must be defined specifically for the InOrderCPU because
  50  * not all architectural state is located within the O3ThreadState
  51  * (such as the commit PC, and registers), and specific actions
  52  * must be taken when using this interface (such as squashing all
  53  * in-flight instructions when doing a write to this interface).
  54  */
  55 class InOrderThreadContext : public ThreadContext
  56 {
  57   public:
  58     InOrderThreadContext() { }
  59
  60     /** Pointer to the CPU. */
  61     InOrderCPU *cpu;
  62
  63     /** Pointer to the thread state that this TC corrseponds to. */
  64     InOrderThreadState *thread;
  65
  66
  67     /** Returns a pointer to the ITB. */
  68     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  69     TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
  70
  71     /** Returns a pointer to the DTB. */
  72     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  73     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
  74
  75     System *getSystemPtr() { return cpu->system; }
  76
  77     /** Returns a pointer to this CPU. */
  78     virtual BaseCPU *getCpuPtr() { return cpu; }
  79
  80     /** Returns a pointer to this CPU. */
  81     virtual std::string getCpuName() { return cpu->name(); }
  82
  83     /** Reads this CPU's ID. */
  84     virtual int cpuId() { return cpu->cpuId(); }
  85
  86     virtual int contextId() { return thread->contextId(); }
  87
  88     virtual void setContextId(int id) { thread->setContextId(id); }
  89
  90     /** Returns this thread's ID number. */
  91     virtual int threadId() { return thread->threadId(); }
  92     virtual void setThreadId(int id) { return thread->setThreadId(id); }
  93
  94     virtual uint64_t readMicroPC()
  95     { return 0; }
  96
  97     virtual void setMicroPC(uint64_t val) { };
  98
  99     virtual uint64_t readNextMicroPC()
 100     { return 0; }
 101
 102     virtual void setNextMicroPC(uint64_t val) { };
 103
 104     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 105
 106     /** Returns a pointer to this thread's process. */
 107     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 108
 109     /** Returns this thread's status. */
 110     virtual Status status() const { return thread->status(); }
 111
 112     /** Sets this thread's status. */
 113     virtual void setStatus(Status new_status)
 114     { thread->setStatus(new_status); }
 115
 116     /** Set the status to Active.  Optional delay indicates number of
 117      * cycles to wait before beginning execution. */
 118     virtual void activate(int delay = 1);
 119
 120     /** Set the status to Suspended. */
 121     virtual void suspend(int delay = 0);
 122
 123     /** Set the status to Halted. */
 124     virtual void halt(int delay = 0);
 125
 126     /** Takes over execution of a thread from another CPU. */
 127     virtual void takeOverFrom(ThreadContext *old_context);
 128
 129     /** Registers statistics associated with this TC. */
 130     virtual void regStats(const std::string &name);
 131
 132     /** Serializes state. */
 133     virtual void serialize(std::ostream &os);
 134
 135     /** Unserializes state. */
 136     virtual void unserialize(Checkpoint *cp, const std::string &section);
 137
 138     /** Returns this thread's ID number. */
 139     virtual int getThreadNum() { return thread->readTid(); }
 140
 141     /** Returns the instruction this thread is currently committing.
 142      *  Only used when an instruction faults.
 143      */
 144     virtual TheISA::MachInst getInst();
 145
 146     /** Copies the architectural registers from another TC into this TC. */
 147     virtual void copyArchRegs(ThreadContext *src_tc);
 148
 149     /** Resets all architectural registers to 0. */
 150     virtual void clearArchRegs();
 151
 152     /** Reads an integer register. */
 153     virtual uint64_t readIntReg(int reg_idx);
 154
 155     virtual FloatReg readFloatReg(int reg_idx, int width);
 156
 157     virtual FloatReg readFloatReg(int reg_idx);
 158
 159     virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
 160
 161     virtual FloatRegBits readFloatRegBits(int reg_idx);
 162
 163     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid);
 164
 165     /** Sets an integer register to a value. */
 166     virtual void setIntReg(int reg_idx, uint64_t val);
 167
 168     virtual void setFloatReg(int reg_idx, FloatReg val, int width);
 169
 170     virtual void setFloatReg(int reg_idx, FloatReg val);
 171
 172     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
 173
 174     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 175
 176     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid);
 177
 178     /** Reads this thread's PC. */
 179     virtual uint64_t readPC()
 180     { return cpu->readPC(thread->readTid()); }
 181
 182     /** Sets this thread's PC. */
 183     virtual void setPC(uint64_t val);
 184
 185     /** Reads this thread's next PC. */
 186     virtual uint64_t readNextPC()
 187     { return cpu->readNextPC(thread->readTid()); }
 188
 189     /** Sets this thread's next PC. */
 190     virtual void setNextPC(uint64_t val);
 191
 192     virtual uint64_t readNextNPC()
 193     { return cpu->readNextNPC(thread->readTid()); }
 194
 195     virtual void setNextNPC(uint64_t val);
 196
 197     /** Reads a miscellaneous register. */
 198     virtual MiscReg readMiscRegNoEffect(int misc_reg)
 199     { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 200
 201     /** Reads a misc. register, including any side-effects the
 202      * read might have as defined by the architecture. */
 203     virtual MiscReg readMiscReg(int misc_reg)
 204     { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 205
 206     /** Sets a misc. register. */
 207     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 208
 209     /** Sets a misc. register, including any side-effects the
 210      * write might have as defined by the architecture. */
 211     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 212
 213     virtual void activateContext(int delay)
 214     { cpu->activateContext(thread->readTid(), delay); }
 215
 216     virtual void deallocateContext()
 217     { cpu->deallocateContext(thread->readTid()); }
 218
 219     /** Returns the number of consecutive store conditional failures. */
 220     // @todo: Figure out where these store cond failures should go.
 221     virtual unsigned readStCondFailures()
 222     { return thread->storeCondFailures; }
 223
 224     /** Sets the number of consecutive store conditional failures. */
 225     virtual void setStCondFailures(unsigned sc_failures)
 226     { thread->storeCondFailures = sc_failures; }
 227
 228     // Only really makes sense for old CPU model.  Lots of code
 229     // outside the CPU still checks this function, so it will
 230     // always return false to keep everything working.
 231     /** Checks if the thread is misspeculating.  Because it is
 232      * very difficult to determine if the thread is
 233      * misspeculating, this is set as false. */
 234     virtual bool misspeculating() { return false; }
 235
 236     /** Executes a syscall in SE mode. */
 237     virtual void syscall(int64_t callnum)
 238     { return cpu->syscall(callnum, thread->readTid()); }
 239
 240     /** Reads the funcExeInst counter. */
 241     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 242
 243     virtual void changeRegFileContext(unsigned param,
 244                                       unsigned val)
 245     { panic("Not supported!"); }
 246 };
 247
 248 #endif