src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  45 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  46
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/cpu.hh"
  49 #include "cpu/inorder/thread_state.hh"
  50 #include "cpu/exetrace.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "arch/kernel_stats.hh"
  53
  54 class EndQuiesceEvent;
  55 class CheckerCPU;
  56 namespace Kernel {
  57     class Statistics;
  58 };
  59
  60 /**
  61  * Derived ThreadContext class for use with the InOrderCPU.  It
  62  * provides the interface for any external objects to access a
  63  * single thread's state and some general CPU state.  Any time
  64  * external objects try to update state through this interface,
  65  * the CPU will create an event to squash all in-flight
  66  * instructions in order to ensure state is maintained correctly.
  67  * It must be defined specifically for the InOrderCPU because
  68  * not all architectural state is located within the O3ThreadState
  69  * (such as the commit PC, and registers), and specific actions
  70  * must be taken when using this interface (such as squashing all
  71  * in-flight instructions when doing a write to this interface).
  72  */
  73 class InOrderThreadContext : public ThreadContext
  74 {
  75   public:
  76     InOrderThreadContext() { }
  77
  78     /** Pointer to the CPU. */
  79     InOrderCPU *cpu;
  80
  81     /** Pointer to the thread state that this TC corrseponds to. */
  82     InOrderThreadState *thread;
  83
  84     /** Returns a pointer to the ITB. */
  85     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  86     TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
  87
  88     /** Returns a pointer to the DTB. */
  89     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  90     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
  91
  92     /** Currently InOrder model does not support CheckerCPU, this is
  93      *  merely here for supporting compilation of gem5 with the Checker
  94      *  as a runtime option
  95      */
  96     CheckerCPU *getCheckerCpuPtr() { return NULL; }
  97
  98     TheISA::Decoder *
  99     getDecoderPtr()
 100     {
 101         return cpu->getDecoderPtr(thread->contextId());
 102     }
 103
 104     System *getSystemPtr() { return cpu->system; }
 105
 106     /** Returns a pointer to this CPU. */
 107     BaseCPU *getCpuPtr() { return cpu; }
 108
 109     /** Returns a pointer to this CPU. */
 110     std::string getCpuName() { return cpu->name(); }
 111
 112     /** Reads this CPU's ID. */
 113     int cpuId() { return cpu->cpuId(); }
 114
 115     int contextId() { return thread->contextId(); }
 116
 117     void setContextId(int id) { thread->setContextId(id); }
 118
 119     /** Returns this thread's ID number. */
 120     int threadId() { return thread->threadId(); }
 121     void setThreadId(int id) { return thread->setThreadId(id); }
 122
 123     uint64_t readMicroPC()
 124     { return 0; }
 125
 126     void setMicroPC(uint64_t val) { };
 127
 128     uint64_t readNextMicroPC()
 129     { return 0; }
 130
 131     void setNextMicroPC(uint64_t val) { };
 132
 133     /** Returns a pointer to this thread's kernel statistics. */
 134     TheISA::Kernel::Statistics *getKernelStats()
 135     { return thread->kernelStats; }
 136
 137     PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
 138
 139     FSTranslatingPortProxy &getVirtProxy();
 140
 141     void initMemProxies(ThreadContext *tc)
 142     { thread->initMemProxies(tc); }
 143
 144     /** Dumps the function profiling information.
 145      * @todo: Implement.
 146      */
 147     void dumpFuncProfile();
 148
 149     /** Reads the last tick that this thread was activated on. */
 150     Tick readLastActivate();
 151     /** Reads the last tick that this thread was suspended on. */
 152     Tick readLastSuspend();
 153
 154     /** Clears the function profiling information. */
 155     void profileClear();
 156
 157     /** Samples the function profiling information. */
 158     void profileSample();
 159
 160     /** Returns pointer to the quiesce event. */
 161     EndQuiesceEvent *getQuiesceEvent()
 162     {
 163         return this->thread->quiesceEvent;
 164     }
 165
 166     SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
 167
 168     /** Returns a pointer to this thread's process. */
 169     Process *getProcessPtr() { return thread->getProcessPtr(); }
 170
 171     /** Returns this thread's status. */
 172     Status status() const { return thread->status(); }
 173
 174     /** Sets this thread's status. */
 175     void setStatus(Status new_status)
 176     { thread->setStatus(new_status); }
 177
 178     /** Set the status to Active.  Optional delay indicates number of
 179      * cycles to wait before beginning execution. */
 180     void activate(Cycles delay = Cycles(1));
 181
 182     /** Set the status to Suspended. */
 183     void suspend(Cycles delay = Cycles(0));
 184
 185     /** Set the status to Halted. */
 186     void halt(Cycles delay = Cycles(0));
 187
 188     /** Takes over execution of a thread from another CPU. */
 189     void takeOverFrom(ThreadContext *old_context);
 190
 191     /** Registers statistics associated with this TC. */
 192     void regStats(const std::string &name);
 193
 194     /** Returns this thread's ID number. */
 195     int getThreadNum() { return thread->threadId(); }
 196
 197     /** Copies the architectural registers from another TC into this TC. */
 198     void copyArchRegs(ThreadContext *src_tc);
 199
 200     /** Resets all architectural registers to 0. */
 201     void clearArchRegs();
 202
 203     /** Reads an integer register. */
 204     uint64_t readIntReg(int reg_idx);
 205
 206     FloatReg readFloatReg(int reg_idx);
 207
 208     FloatRegBits readFloatRegBits(int reg_idx);
 209
 210     uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
 211
 212     /** Sets an integer register to a value. */
 213     void setIntReg(int reg_idx, uint64_t val);
 214
 215     void setFloatReg(int reg_idx, FloatReg val);
 216
 217     void setFloatRegBits(int reg_idx, FloatRegBits val);
 218
 219     void setRegOtherThread(int misc_reg,
 220                                    const MiscReg &val,
 221                                    ThreadID tid);
 222
 223     /** Reads this thread's PC. */
 224     TheISA::PCState pcState()
 225     { return cpu->pcState(thread->threadId()); }
 226
 227     /** Sets this thread's PC. */
 228     void pcState(const TheISA::PCState &val)
 229     { cpu->pcState(val, thread->threadId()); }
 230
 231     /** Needs to be implemented for future CheckerCPU support.
 232      *  See O3CPU for examples on how to integrate Checker.
 233      */
 234     void pcStateNoRecord(const TheISA::PCState &val)
 235     {}
 236
 237     Addr instAddr()
 238     { return cpu->instAddr(thread->threadId()); }
 239
 240     Addr nextInstAddr()
 241     { return cpu->nextInstAddr(thread->threadId()); }
 242
 243     MicroPC microPC()
 244     { return cpu->microPC(thread->threadId()); }
 245
 246     /** Reads a miscellaneous register. */
 247     MiscReg readMiscRegNoEffect(int misc_reg)
 248     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 249
 250     /** Reads a misc. register, including any side-effects the
 251      * read might have as defined by the architecture. */
 252     MiscReg readMiscReg(int misc_reg)
 253     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 254
 255     /** Sets a misc. register. */
 256     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 257
 258     /** Sets a misc. register, including any side-effects the
 259      * write might have as defined by the architecture. */
 260     void setMiscReg(int misc_reg, const MiscReg &val);
 261
 262     int flattenIntIndex(int reg)
 263     { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
 264
 265     int flattenFloatIndex(int reg)
 266     { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
 267
 268     void activateContext(Cycles delay)
 269     { cpu->activateContext(thread->threadId(), delay); }
 270
 271     void deallocateContext()
 272     { cpu->deallocateContext(thread->threadId()); }
 273
 274     /** Returns the number of consecutive store conditional failures. */
 275     // @todo: Figure out where these store cond failures should go.
 276     unsigned readStCondFailures()
 277     { return thread->storeCondFailures; }
 278
 279     /** Sets the number of consecutive store conditional failures. */
 280     void setStCondFailures(unsigned sc_failures)
 281     { thread->storeCondFailures = sc_failures; }
 282
 283     // Only really makes sense for old CPU model.  Lots of code
 284     // outside the CPU still checks this function, so it will
 285     // always return false to keep everything working.
 286     /** Checks if the thread is misspeculating.  Because it is
 287      * very difficult to determine if the thread is
 288      * misspeculating, this is set as false. */
 289     bool misspeculating() { return false; }
 290
 291     /** Executes a syscall in SE mode. */
 292     void syscall(int64_t callnum)
 293     { return cpu->syscall(callnum, thread->threadId()); }
 294
 295     /** Reads the funcExeInst counter. */
 296     Counter readFuncExeInst() { return thread->funcExeInst; }
 297
 298     void changeRegFileContext(unsigned param,
 299                                       unsigned val)
 300     { panic("Not supported!"); }
 301
 302     uint64_t readIntRegFlat(int idx);
 303     void setIntRegFlat(int idx, uint64_t val);
 304
 305     FloatReg readFloatRegFlat(int idx);
 306     void setFloatRegFlat(int idx, FloatReg val);
 307
 308     FloatRegBits readFloatRegBitsFlat(int idx);
 309     void setFloatRegBitsFlat(int idx, FloatRegBits val);
 310 };
 311
 312 #endif