src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  34
  35 #include "config/the_isa.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/thread_state.hh"
  38 #include "cpu/exetrace.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "arch/kernel_stats.hh"
  41
  42 class EndQuiesceEvent;
  43 namespace Kernel {
  44     class Statistics;
  45 };
  46
  47 class TranslatingPort;
  48
  49 /**
  50  * Derived ThreadContext class for use with the InOrderCPU.  It
  51  * provides the interface for any external objects to access a
  52  * single thread's state and some general CPU state.  Any time
  53  * external objects try to update state through this interface,
  54  * the CPU will create an event to squash all in-flight
  55  * instructions in order to ensure state is maintained correctly.
  56  * It must be defined specifically for the InOrderCPU because
  57  * not all architectural state is located within the O3ThreadState
  58  * (such as the commit PC, and registers), and specific actions
  59  * must be taken when using this interface (such as squashing all
  60  * in-flight instructions when doing a write to this interface).
  61  */
  62 class InOrderThreadContext : public ThreadContext
  63 {
  64   public:
  65     InOrderThreadContext() { }
  66
  67     /** Pointer to the CPU. */
  68     InOrderCPU *cpu;
  69
  70     /** Pointer to the thread state that this TC corrseponds to. */
  71     InOrderThreadState *thread;
  72
  73     /** Returns a pointer to the ITB. */
  74     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  75     TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
  76
  77     /** Returns a pointer to the DTB. */
  78     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  79     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
  80
  81     Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
  82
  83     System *getSystemPtr() { return cpu->system; }
  84
  85     /** Returns a pointer to this CPU. */
  86     BaseCPU *getCpuPtr() { return cpu; }
  87
  88     /** Returns a pointer to this CPU. */
  89     std::string getCpuName() { return cpu->name(); }
  90
  91     /** Reads this CPU's ID. */
  92     int cpuId() { return cpu->cpuId(); }
  93
  94     int contextId() { return thread->contextId(); }
  95
  96     void setContextId(int id) { thread->setContextId(id); }
  97
  98     /** Returns this thread's ID number. */
  99     int threadId() { return thread->threadId(); }
 100     void setThreadId(int id) { return thread->setThreadId(id); }
 101
 102     uint64_t readMicroPC()
 103     { return 0; }
 104
 105     void setMicroPC(uint64_t val) { };
 106
 107     uint64_t readNextMicroPC()
 108     { return 0; }
 109
 110     void setNextMicroPC(uint64_t val) { };
 111
 112 #if FULL_SYSTEM
 113     /** Returns a pointer to physical memory. */
 114     PhysicalMemory *getPhysMemPtr()
 115     { assert(0); return 0; /*return cpu->physmem;*/ }
 116
 117     /** Returns a pointer to this thread's kernel statistics. */
 118     TheISA::Kernel::Statistics *getKernelStats()
 119     { return thread->kernelStats; }
 120
 121     void connectMemPorts(ThreadContext *tc)
 122     { thread->connectMemPorts(tc); }
 123
 124     /** Dumps the function profiling information.
 125      * @todo: Implement.
 126      */
 127     void dumpFuncProfile();
 128
 129     /** Reads the last tick that this thread was activated on. */
 130     Tick readLastActivate();
 131     /** Reads the last tick that this thread was suspended on. */
 132     Tick readLastSuspend();
 133
 134     /** Clears the function profiling information. */
 135     void profileClear();
 136
 137     /** Samples the function profiling information. */
 138     void profileSample();
 139
 140     /** Returns pointer to the quiesce event. */
 141     EndQuiesceEvent *getQuiesceEvent()
 142     {
 143         return this->thread->quiesceEvent;
 144     }
 145 #else
 146     TranslatingPort *getMemPort() { return thread->getMemPort(); }
 147
 148     /** Returns a pointer to this thread's process. */
 149     Process *getProcessPtr() { return thread->getProcessPtr(); }
 150 #endif
 151
 152     VirtualPort *getVirtPort();
 153     FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
 154
 155     /** Returns this thread's status. */
 156     Status status() const { return thread->status(); }
 157
 158     /** Sets this thread's status. */
 159     void setStatus(Status new_status)
 160     { thread->setStatus(new_status); }
 161
 162     /** Set the status to Active.  Optional delay indicates number of
 163      * cycles to wait before beginning execution. */
 164     void activate(int delay = 1);
 165
 166     /** Set the status to Suspended. */
 167     void suspend(int delay = 0);
 168
 169     /** Set the status to Halted. */
 170     void halt(int delay = 0);
 171
 172     /** Takes over execution of a thread from another CPU. */
 173     void takeOverFrom(ThreadContext *old_context);
 174
 175     /** Registers statistics associated with this TC. */
 176     void regStats(const std::string &name);
 177
 178     /** Serializes state. */
 179     void serialize(std::ostream &os);
 180
 181     /** Unserializes state. */
 182     void unserialize(Checkpoint *cp, const std::string &section);
 183
 184     /** Returns this thread's ID number. */
 185     int getThreadNum() { return thread->threadId(); }
 186
 187     /** Copies the architectural registers from another TC into this TC. */
 188     void copyArchRegs(ThreadContext *src_tc);
 189
 190     /** Resets all architectural registers to 0. */
 191     void clearArchRegs();
 192
 193     /** Reads an integer register. */
 194     uint64_t readIntReg(int reg_idx);
 195
 196     FloatReg readFloatReg(int reg_idx);
 197
 198     FloatRegBits readFloatRegBits(int reg_idx);
 199
 200     uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
 201
 202     /** Sets an integer register to a value. */
 203     void setIntReg(int reg_idx, uint64_t val);
 204
 205     void setFloatReg(int reg_idx, FloatReg val);
 206
 207     void setFloatRegBits(int reg_idx, FloatRegBits val);
 208
 209     void setRegOtherThread(int misc_reg,
 210                                    const MiscReg &val,
 211                                    ThreadID tid);
 212
 213     /** Reads this thread's PC. */
 214     TheISA::PCState pcState()
 215     { return cpu->pcState(thread->threadId()); }
 216
 217     /** Sets this thread's PC. */
 218     void pcState(const TheISA::PCState &val)
 219     { cpu->pcState(val, thread->threadId()); }
 220
 221     Addr instAddr()
 222     { return cpu->instAddr(thread->threadId()); }
 223
 224     Addr nextInstAddr()
 225     { return cpu->nextInstAddr(thread->threadId()); }
 226
 227     MicroPC microPC()
 228     { return cpu->microPC(thread->threadId()); }
 229
 230     /** Reads a miscellaneous register. */
 231     MiscReg readMiscRegNoEffect(int misc_reg)
 232     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 233
 234     /** Reads a misc. register, including any side-effects the
 235      * read might have as defined by the architecture. */
 236     MiscReg readMiscReg(int misc_reg)
 237     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 238
 239     /** Sets a misc. register. */
 240     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 241
 242     /** Sets a misc. register, including any side-effects the
 243      * write might have as defined by the architecture. */
 244     void setMiscReg(int misc_reg, const MiscReg &val);
 245
 246     int flattenIntIndex(int reg)
 247     { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
 248
 249     int flattenFloatIndex(int reg)
 250     { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
 251
 252     void activateContext(int delay)
 253     { cpu->activateContext(thread->threadId(), delay); }
 254
 255     void deallocateContext()
 256     { cpu->deallocateContext(thread->threadId()); }
 257
 258     /** Returns the number of consecutive store conditional failures. */
 259     // @todo: Figure out where these store cond failures should go.
 260     unsigned readStCondFailures()
 261     { return thread->storeCondFailures; }
 262
 263     /** Sets the number of consecutive store conditional failures. */
 264     void setStCondFailures(unsigned sc_failures)
 265     { thread->storeCondFailures = sc_failures; }
 266
 267     // Only really makes sense for old CPU model.  Lots of code
 268     // outside the CPU still checks this function, so it will
 269     // always return false to keep everything working.
 270     /** Checks if the thread is misspeculating.  Because it is
 271      * very difficult to determine if the thread is
 272      * misspeculating, this is set as false. */
 273     bool misspeculating() { return false; }
 274
 275 #if !FULL_SYSTEM
 276     /** Executes a syscall in SE mode. */
 277     void syscall(int64_t callnum)
 278     { return cpu->syscall(callnum, thread->threadId()); }
 279 #endif
 280
 281     /** Reads the funcExeInst counter. */
 282     Counter readFuncExeInst() { return thread->funcExeInst; }
 283
 284     void changeRegFileContext(unsigned param,
 285                                       unsigned val)
 286     { panic("Not supported!"); }
 287 };
 288
 289 #endif