2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/thread_state.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/thread_context.hh"
40 #include "arch/kernel_stats.hh"
42 class EndQuiesceEvent;
49 * Derived ThreadContext class for use with the InOrderCPU. It
50 * provides the interface for any external objects to access a
51 * single thread's state and some general CPU state. Any time
52 * external objects try to update state through this interface,
53 * the CPU will create an event to squash all in-flight
54 * instructions in order to ensure state is maintained correctly.
55 * It must be defined specifically for the InOrderCPU because
56 * not all architectural state is located within the O3ThreadState
57 * (such as the commit PC, and registers), and specific actions
58 * must be taken when using this interface (such as squashing all
59 * in-flight instructions when doing a write to this interface).
61 class InOrderThreadContext : public ThreadContext
64 InOrderThreadContext() { }
66 /** Pointer to the CPU. */
69 /** Pointer to the thread state that this TC corrseponds to. */
70 InOrderThreadState *thread;
72 /** Returns a pointer to the ITB. */
73 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
74 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
76 /** Returns a pointer to the DTB. */
77 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
78 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
80 /** Currently InOrder model does not support CheckerCPU, this is
81 * merely here for supporting compilation of gem5 with the Checker
84 CheckerCPU *getCheckerCpuPtr() { return NULL; }
89 return cpu->getDecoderPtr(thread->contextId());
92 System *getSystemPtr() { return cpu->system; }
94 /** Returns a pointer to this CPU. */
95 BaseCPU *getCpuPtr() { return cpu; }
97 /** Returns a pointer to this CPU. */
98 std::string getCpuName() { return cpu->name(); }
100 /** Reads this CPU's ID. */
101 int cpuId() { return cpu->cpuId(); }
103 int contextId() { return thread->contextId(); }
105 void setContextId(int id) { thread->setContextId(id); }
107 /** Returns this thread's ID number. */
108 int threadId() { return thread->threadId(); }
109 void setThreadId(int id) { return thread->setThreadId(id); }
111 uint64_t readMicroPC()
114 void setMicroPC(uint64_t val) { };
116 uint64_t readNextMicroPC()
119 void setNextMicroPC(uint64_t val) { };
121 /** Returns a pointer to this thread's kernel statistics. */
122 TheISA::Kernel::Statistics *getKernelStats()
123 { return thread->kernelStats; }
125 PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
127 FSTranslatingPortProxy &getVirtProxy();
129 void initMemProxies(ThreadContext *tc)
130 { thread->initMemProxies(tc); }
132 /** Dumps the function profiling information.
135 void dumpFuncProfile();
137 /** Reads the last tick that this thread was activated on. */
138 Tick readLastActivate();
139 /** Reads the last tick that this thread was suspended on. */
140 Tick readLastSuspend();
142 /** Clears the function profiling information. */
145 /** Samples the function profiling information. */
146 void profileSample();
148 /** Returns pointer to the quiesce event. */
149 EndQuiesceEvent *getQuiesceEvent()
151 return this->thread->quiesceEvent;
154 SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
156 /** Returns a pointer to this thread's process. */
157 Process *getProcessPtr() { return thread->getProcessPtr(); }
159 /** Returns this thread's status. */
160 Status status() const { return thread->status(); }
162 /** Sets this thread's status. */
163 void setStatus(Status new_status)
164 { thread->setStatus(new_status); }
166 /** Set the status to Active. Optional delay indicates number of
167 * cycles to wait before beginning execution. */
168 void activate(Cycles delay = Cycles(1));
170 /** Set the status to Suspended. */
171 void suspend(Cycles delay = Cycles(0));
173 /** Set the status to Halted. */
174 void halt(Cycles delay = Cycles(0));
176 /** Takes over execution of a thread from another CPU. */
177 void takeOverFrom(ThreadContext *old_context);
179 /** Registers statistics associated with this TC. */
180 void regStats(const std::string &name);
182 /** Serializes state. */
183 void serialize(std::ostream &os);
185 /** Unserializes state. */
186 void unserialize(Checkpoint *cp, const std::string §ion);
188 /** Returns this thread's ID number. */
189 int getThreadNum() { return thread->threadId(); }
191 /** Copies the architectural registers from another TC into this TC. */
192 void copyArchRegs(ThreadContext *src_tc);
194 /** Resets all architectural registers to 0. */
195 void clearArchRegs();
197 /** Reads an integer register. */
198 uint64_t readIntReg(int reg_idx);
200 FloatReg readFloatReg(int reg_idx);
202 FloatRegBits readFloatRegBits(int reg_idx);
204 uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
206 /** Sets an integer register to a value. */
207 void setIntReg(int reg_idx, uint64_t val);
209 void setFloatReg(int reg_idx, FloatReg val);
211 void setFloatRegBits(int reg_idx, FloatRegBits val);
213 void setRegOtherThread(int misc_reg,
217 /** Reads this thread's PC. */
218 TheISA::PCState pcState()
219 { return cpu->pcState(thread->threadId()); }
221 /** Sets this thread's PC. */
222 void pcState(const TheISA::PCState &val)
223 { cpu->pcState(val, thread->threadId()); }
225 /** Needs to be implemented for future CheckerCPU support.
226 * See O3CPU for examples on how to integrate Checker.
228 void pcStateNoRecord(const TheISA::PCState &val)
232 { return cpu->instAddr(thread->threadId()); }
235 { return cpu->nextInstAddr(thread->threadId()); }
238 { return cpu->microPC(thread->threadId()); }
240 /** Reads a miscellaneous register. */
241 MiscReg readMiscRegNoEffect(int misc_reg)
242 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
244 /** Reads a misc. register, including any side-effects the
245 * read might have as defined by the architecture. */
246 MiscReg readMiscReg(int misc_reg)
247 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
249 /** Sets a misc. register. */
250 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
252 /** Sets a misc. register, including any side-effects the
253 * write might have as defined by the architecture. */
254 void setMiscReg(int misc_reg, const MiscReg &val);
256 int flattenIntIndex(int reg)
257 { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
259 int flattenFloatIndex(int reg)
260 { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
262 void activateContext(Cycles delay)
263 { cpu->activateContext(thread->threadId(), delay); }
265 void deallocateContext()
266 { cpu->deallocateContext(thread->threadId()); }
268 /** Returns the number of consecutive store conditional failures. */
269 // @todo: Figure out where these store cond failures should go.
270 unsigned readStCondFailures()
271 { return thread->storeCondFailures; }
273 /** Sets the number of consecutive store conditional failures. */
274 void setStCondFailures(unsigned sc_failures)
275 { thread->storeCondFailures = sc_failures; }
277 // Only really makes sense for old CPU model. Lots of code
278 // outside the CPU still checks this function, so it will
279 // always return false to keep everything working.
280 /** Checks if the thread is misspeculating. Because it is
281 * very difficult to determine if the thread is
282 * misspeculating, this is set as false. */
283 bool misspeculating() { return false; }
285 /** Executes a syscall in SE mode. */
286 void syscall(int64_t callnum)
287 { return cpu->syscall(callnum, thread->threadId()); }
289 /** Reads the funcExeInst counter. */
290 Counter readFuncExeInst() { return thread->funcExeInst; }
292 void changeRegFileContext(unsigned param,
294 { panic("Not supported!"); }