src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  34
  35 #include "cpu/exetrace.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/inorder/thread_state.hh"
  38 #include "cpu/inorder/cpu.hh"
  39
  40 class TranslatingPort;
  41
  42 /**
  43  * Derived ThreadContext class for use with the InOrderCPU.  It
  44  * provides the interface for any external objects to access a
  45  * single thread's state and some general CPU state.  Any time
  46  * external objects try to update state through this interface,
  47  * the CPU will create an event to squash all in-flight
  48  * instructions in order to ensure state is maintained correctly.
  49  * It must be defined specifically for the InOrderCPU because
  50  * not all architectural state is located within the O3ThreadState
  51  * (such as the commit PC, and registers), and specific actions
  52  * must be taken when using this interface (such as squashing all
  53  * in-flight instructions when doing a write to this interface).
  54  */
  55 class InOrderThreadContext : public ThreadContext
  56 {
  57   public:
  58     InOrderThreadContext() { }
  59
  60    /** Pointer to the CPU. */
  61     InOrderCPU *cpu;
  62
  63     /** Pointer to the thread state that this TC corrseponds to. */
  64     InOrderThreadState *thread;
  65
  66
  67     /** Returns a pointer to the ITB. */
  68     TheISA::TLB *getITBPtr() { return cpu->itb; }
  69
  70     /** Returns a pointer to the DTB. */
  71     TheISA::TLB *getDTBPtr() { return cpu->dtb; }
  72
  73     System *getSystemPtr() { return cpu->system; }
  74
  75     /** Returns a pointer to this CPU. */
  76     virtual BaseCPU *getCpuPtr() { return cpu; }
  77
  78     /** Returns a pointer to this CPU. */
  79     virtual std::string getCpuName() { return cpu->name(); }
  80
  81     /** Reads this CPU's ID. */
  82     virtual int cpuId() { return cpu->cpuId(); }
  83
  84     virtual int contextId() { return thread->contextId(); }
  85
  86     virtual void setContextId(int id) { thread->setContextId(id); }
  87
  88     /** Returns this thread's ID number. */
  89     virtual int threadId() { return thread->threadId(); }
  90     virtual void setThreadId(int id) { return thread->setThreadId(id); }
  91
  92     virtual uint64_t readMicroPC()
  93     { return 0; }
  94
  95     virtual void setMicroPC(uint64_t val) { };
  96
  97     virtual uint64_t readNextMicroPC()
  98     { return 0; }
  99
 100     virtual void setNextMicroPC(uint64_t val) { };
 101
 102     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 103
 104     /** Returns a pointer to this thread's process. */
 105     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 106
 107     /** Returns this thread's status. */
 108     virtual Status status() const { return thread->status(); }
 109
 110     /** Sets this thread's status. */
 111     virtual void setStatus(Status new_status)
 112     { thread->setStatus(new_status); }
 113
 114     /** Set the status to Active.  Optional delay indicates number of
 115      * cycles to wait before beginning execution. */
 116     virtual void activate(int delay = 1);
 117
 118     /** Set the status to Suspended. */
 119     virtual void suspend(int delay = 0);
 120
 121     /** Set the status to Unallocated. */
 122     virtual void deallocate(int delay = 1);
 123
 124     /** Set the status to Halted. */
 125     virtual void halt(int delay = 0);
 126
 127     /** Takes over execution of a thread from another CPU. */
 128     virtual void takeOverFrom(ThreadContext *old_context);
 129
 130     /** Registers statistics associated with this TC. */
 131     virtual void regStats(const std::string &name);
 132
 133     /** Serializes state. */
 134     virtual void serialize(std::ostream &os);
 135
 136     /** Unserializes state. */
 137     virtual void unserialize(Checkpoint *cp, const std::string &section);
 138
 139     /** Returns this thread's ID number. */
 140     virtual int getThreadNum() { return thread->readTid(); }
 141
 142     /** Returns the instruction this thread is currently committing.
 143      *  Only used when an instruction faults.
 144      */
 145     virtual TheISA::MachInst getInst();
 146
 147     /** Copies the architectural registers from another TC into this TC. */
 148     virtual void copyArchRegs(ThreadContext *src_tc);
 149
 150     /** Resets all architectural registers to 0. */
 151     virtual void clearArchRegs();
 152
 153     /** Reads an integer register. */
 154     virtual uint64_t readIntReg(int reg_idx);
 155
 156     virtual FloatReg readFloatReg(int reg_idx, int width);
 157
 158     virtual FloatReg readFloatReg(int reg_idx);
 159
 160     virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
 161
 162     virtual FloatRegBits readFloatRegBits(int reg_idx);
 163
 164     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid);
 165
 166     /** Sets an integer register to a value. */
 167     virtual void setIntReg(int reg_idx, uint64_t val);
 168
 169     virtual void setFloatReg(int reg_idx, FloatReg val, int width);
 170
 171     virtual void setFloatReg(int reg_idx, FloatReg val);
 172
 173     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
 174
 175     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 176
 177     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid);
 178
 179     /** Reads this thread's PC. */
 180     virtual uint64_t readPC()
 181     { return cpu->readPC(thread->readTid()); }
 182
 183     /** Sets this thread's PC. */
 184     virtual void setPC(uint64_t val);
 185
 186     /** Reads this thread's next PC. */
 187     virtual uint64_t readNextPC()
 188     { return cpu->readNextPC(thread->readTid()); }
 189
 190     /** Sets this thread's next PC. */
 191     virtual void setNextPC(uint64_t val);
 192
 193     virtual uint64_t readNextNPC()
 194     { return cpu->readNextNPC(thread->readTid()); }
 195
 196     virtual void setNextNPC(uint64_t val);
 197
 198     /** Reads a miscellaneous register. */
 199     virtual MiscReg readMiscRegNoEffect(int misc_reg)
 200     { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 201
 202     /** Reads a misc. register, including any side-effects the
 203      * read might have as defined by the architecture. */
 204     virtual MiscReg readMiscReg(int misc_reg)
 205     { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 206
 207     /** Sets a misc. register. */
 208     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 209
 210     /** Sets a misc. register, including any side-effects the
 211      * write might have as defined by the architecture. */
 212     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 213
 214     virtual void activateContext(int delay)
 215     { cpu->activateContext(thread->readTid(), delay); }
 216
 217     virtual void deallocateContext()
 218     { cpu->deallocateContext(thread->readTid()); }
 219
 220     /** Returns the number of consecutive store conditional failures. */
 221     // @todo: Figure out where these store cond failures should go.
 222     virtual unsigned readStCondFailures()
 223     { return thread->storeCondFailures; }
 224
 225     /** Sets the number of consecutive store conditional failures. */
 226     virtual void setStCondFailures(unsigned sc_failures)
 227     { thread->storeCondFailures = sc_failures; }
 228
 229     // Only really makes sense for old CPU model.  Lots of code
 230     // outside the CPU still checks this function, so it will
 231     // always return false to keep everything working.
 232     /** Checks if the thread is misspeculating.  Because it is
 233      * very difficult to determine if the thread is
 234      * misspeculating, this is set as false. */
 235     virtual bool misspeculating() { return false; }
 236
 237     /** Executes a syscall in SE mode. */
 238     virtual void syscall(int64_t callnum)
 239     { return cpu->syscall(callnum, thread->readTid()); }
 240
 241     /** Reads the funcExeInst counter. */
 242     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 243
 244     virtual void changeRegFileContext(unsigned param,
 245                                       unsigned val)
 246     { panic("Not supported!"); }
 247
 248     /** This function exits the thread context in the CPU and returns
 249      * 1 if the CPU has no more active threads (meaning it's OK to exit);
 250      * Used in syscall-emulation mode when a thread executes the 'exit'
 251      * syscall.
 252      */
 253     virtual int exit()
 254     {
 255         this->deallocate();
 256
 257         // If there are still threads executing in the system (for now
 258         // this single cpu)
 259         if (this->cpu->numActiveThreads() - 1 > 0)
 260             return 0; // don't exit simulation
 261         else
 262             return 1; // exit simulation
 263     }
 264
 265     virtual void setThreadRescheduleCondition(uint64_t cond)
 266     {
 267         this->deallocate();
 268
 269         this->setStatus(ThreadContext::Suspended);
 270
 271         activateContext(cond);
 272     }
 273 };
 274
 275 #endif