src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  34
  35 #include "cpu/exetrace.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/inorder/thread_state.hh"
  38 #include "cpu/inorder/cpu.hh"
  39
  40 class TranslatingPort;
  41
  42 /**
  43  * Derived ThreadContext class for use with the InOrderCPU.  It
  44  * provides the interface for any external objects to access a
  45  * single thread's state and some general CPU state.  Any time
  46  * external objects try to update state through this interface,
  47  * the CPU will create an event to squash all in-flight
  48  * instructions in order to ensure state is maintained correctly.
  49  * It must be defined specifically for the InOrderCPU because
  50  * not all architectural state is located within the O3ThreadState
  51  * (such as the commit PC, and registers), and specific actions
  52  * must be taken when using this interface (such as squashing all
  53  * in-flight instructions when doing a write to this interface).
  54  */
  55 class InOrderThreadContext : public ThreadContext
  56 {
  57   public:
  58     InOrderThreadContext() { }
  59
  60    /** Pointer to the CPU. */
  61     InOrderCPU *cpu;
  62
  63     /** Pointer to the thread state that this TC corrseponds to. */
  64     InOrderThreadState *thread;
  65
  66
  67     /** Returns a pointer to the ITB. */
  68     TheISA::TLB *getITBPtr() { return cpu->itb; }
  69
  70     /** Returns a pointer to the DTB. */
  71     TheISA::TLB *getDTBPtr() { return cpu->dtb; }
  72
  73     System *getSystemPtr() { return cpu->system; }
  74
  75     /** Returns a pointer to this CPU. */
  76     virtual BaseCPU *getCpuPtr() { return cpu; }
  77
  78     /** Returns a pointer to this CPU. */
  79     virtual std::string getCpuName() { return cpu->name(); }
  80
  81     /** Reads this CPU's ID. */
  82     virtual int cpuId() { return cpu->cpuId(); }
  83
  84     virtual int contextId() { return thread->contextId(); }
  85
  86     virtual void setContextId(int id) { thread->setContextId(id); }
  87
  88     /** Returns this thread's ID number. */
  89     virtual int threadId() { return thread->threadId(); }
  90     virtual void setThreadId(int id) { return thread->setThreadId(id); }
  91
  92     virtual uint64_t readMicroPC()
  93     { return 0; }
  94
  95     virtual void setMicroPC(uint64_t val) { };
  96
  97     virtual uint64_t readNextMicroPC()
  98     { return 0; }
  99
 100     virtual void setNextMicroPC(uint64_t val) { };
 101
 102     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 103
 104     /** Returns a pointer to this thread's process. */
 105     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 106
 107     /** Returns this thread's status. */
 108     virtual Status status() const { return thread->status(); }
 109
 110     /** Sets this thread's status. */
 111     virtual void setStatus(Status new_status)
 112     { thread->setStatus(new_status); }
 113
 114     /** Set the status to Active.  Optional delay indicates number of
 115      * cycles to wait before beginning execution. */
 116     virtual void activate(int delay = 1);
 117
 118     /** Set the status to Suspended. */
 119     virtual void suspend(int delay = 0);
 120
 121     /** Set the status to Halted. */
 122     virtual void halt(int delay = 0);
 123
 124     /** Takes over execution of a thread from another CPU. */
 125     virtual void takeOverFrom(ThreadContext *old_context);
 126
 127     /** Registers statistics associated with this TC. */
 128     virtual void regStats(const std::string &name);
 129
 130     /** Serializes state. */
 131     virtual void serialize(std::ostream &os);
 132
 133     /** Unserializes state. */
 134     virtual void unserialize(Checkpoint *cp, const std::string &section);
 135
 136     /** Returns this thread's ID number. */
 137     virtual int getThreadNum() { return thread->readTid(); }
 138
 139     /** Returns the instruction this thread is currently committing.
 140      *  Only used when an instruction faults.
 141      */
 142     virtual TheISA::MachInst getInst();
 143
 144     /** Copies the architectural registers from another TC into this TC. */
 145     virtual void copyArchRegs(ThreadContext *src_tc);
 146
 147     /** Resets all architectural registers to 0. */
 148     virtual void clearArchRegs();
 149
 150     /** Reads an integer register. */
 151     virtual uint64_t readIntReg(int reg_idx);
 152
 153     virtual FloatReg readFloatReg(int reg_idx, int width);
 154
 155     virtual FloatReg readFloatReg(int reg_idx);
 156
 157     virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
 158
 159     virtual FloatRegBits readFloatRegBits(int reg_idx);
 160
 161     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid);
 162
 163     /** Sets an integer register to a value. */
 164     virtual void setIntReg(int reg_idx, uint64_t val);
 165
 166     virtual void setFloatReg(int reg_idx, FloatReg val, int width);
 167
 168     virtual void setFloatReg(int reg_idx, FloatReg val);
 169
 170     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
 171
 172     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 173
 174     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid);
 175
 176     /** Reads this thread's PC. */
 177     virtual uint64_t readPC()
 178     { return cpu->readPC(thread->readTid()); }
 179
 180     /** Sets this thread's PC. */
 181     virtual void setPC(uint64_t val);
 182
 183     /** Reads this thread's next PC. */
 184     virtual uint64_t readNextPC()
 185     { return cpu->readNextPC(thread->readTid()); }
 186
 187     /** Sets this thread's next PC. */
 188     virtual void setNextPC(uint64_t val);
 189
 190     virtual uint64_t readNextNPC()
 191     { return cpu->readNextNPC(thread->readTid()); }
 192
 193     virtual void setNextNPC(uint64_t val);
 194
 195     /** Reads a miscellaneous register. */
 196     virtual MiscReg readMiscRegNoEffect(int misc_reg)
 197     { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 198
 199     /** Reads a misc. register, including any side-effects the
 200      * read might have as defined by the architecture. */
 201     virtual MiscReg readMiscReg(int misc_reg)
 202     { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 203
 204     /** Sets a misc. register. */
 205     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 206
 207     /** Sets a misc. register, including any side-effects the
 208      * write might have as defined by the architecture. */
 209     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 210
 211     virtual void activateContext(int delay)
 212     { cpu->activateContext(thread->readTid(), delay); }
 213
 214     virtual void deallocateContext()
 215     { cpu->deallocateContext(thread->readTid()); }
 216
 217     /** Returns the number of consecutive store conditional failures. */
 218     // @todo: Figure out where these store cond failures should go.
 219     virtual unsigned readStCondFailures()
 220     { return thread->storeCondFailures; }
 221
 222     /** Sets the number of consecutive store conditional failures. */
 223     virtual void setStCondFailures(unsigned sc_failures)
 224     { thread->storeCondFailures = sc_failures; }
 225
 226     // Only really makes sense for old CPU model.  Lots of code
 227     // outside the CPU still checks this function, so it will
 228     // always return false to keep everything working.
 229     /** Checks if the thread is misspeculating.  Because it is
 230      * very difficult to determine if the thread is
 231      * misspeculating, this is set as false. */
 232     virtual bool misspeculating() { return false; }
 233
 234     /** Executes a syscall in SE mode. */
 235     virtual void syscall(int64_t callnum)
 236     { return cpu->syscall(callnum, thread->readTid()); }
 237
 238     /** Reads the funcExeInst counter. */
 239     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 240
 241     virtual void changeRegFileContext(unsigned param,
 242                                       unsigned val)
 243     { panic("Not supported!"); }
 244 };
 245
 246 #endif