src/cpu/inorder/thread_context.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
  33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
  34
  35 #include "config/the_isa.hh"
  36 #include "cpu/exetrace.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "cpu/inorder/thread_state.hh"
  39 #include "cpu/inorder/cpu.hh"
  40
  41 class TranslatingPort;
  42
  43 /**
  44  * Derived ThreadContext class for use with the InOrderCPU.  It
  45  * provides the interface for any external objects to access a
  46  * single thread's state and some general CPU state.  Any time
  47  * external objects try to update state through this interface,
  48  * the CPU will create an event to squash all in-flight
  49  * instructions in order to ensure state is maintained correctly.
  50  * It must be defined specifically for the InOrderCPU because
  51  * not all architectural state is located within the O3ThreadState
  52  * (such as the commit PC, and registers), and specific actions
  53  * must be taken when using this interface (such as squashing all
  54  * in-flight instructions when doing a write to this interface).
  55  */
  56 class InOrderThreadContext : public ThreadContext
  57 {
  58   public:
  59     InOrderThreadContext() { }
  60
  61     /** Pointer to the CPU. */
  62     InOrderCPU *cpu;
  63
  64     /** Pointer to the thread state that this TC corrseponds to. */
  65     InOrderThreadState *thread;
  66
  67
  68     /** Returns a pointer to the ITB. */
  69     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  70     TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
  71
  72     /** Returns a pointer to the DTB. */
  73     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
  74     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
  75
  76     System *getSystemPtr() { return cpu->system; }
  77
  78     /** Returns a pointer to this CPU. */
  79     virtual BaseCPU *getCpuPtr() { return cpu; }
  80
  81     /** Returns a pointer to this CPU. */
  82     virtual std::string getCpuName() { return cpu->name(); }
  83
  84     /** Reads this CPU's ID. */
  85     virtual int cpuId() { return cpu->cpuId(); }
  86
  87     virtual int contextId() { return thread->contextId(); }
  88
  89     virtual void setContextId(int id) { thread->setContextId(id); }
  90
  91     /** Returns this thread's ID number. */
  92     virtual int threadId() { return thread->threadId(); }
  93     virtual void setThreadId(int id) { return thread->setThreadId(id); }
  94
  95     virtual uint64_t readMicroPC()
  96     { return 0; }
  97
  98     virtual void setMicroPC(uint64_t val) { };
  99
 100     virtual uint64_t readNextMicroPC()
 101     { return 0; }
 102
 103     virtual void setNextMicroPC(uint64_t val) { };
 104
 105 #if FULL_SYSTEM
 106     /** Returns a pointer to physical memory. */
 107     virtual PhysicalMemory *getPhysMemPtr()
 108     { assert(0); return 0; /*return cpu->physmem;*/ }
 109
 110     /** Returns a pointer to this thread's kernel statistics. */
 111     virtual TheISA::Kernel::Statistics *getKernelStats()
 112     { return thread->kernelStats; }
 113
 114     virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
 115
 116     virtual VirtualPort *getVirtPort();
 117
 118     virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
 119
 120     /** Dumps the function profiling information.
 121      * @todo: Implement.
 122      */
 123     virtual void dumpFuncProfile();
 124
 125     /** Reads the last tick that this thread was activated on. */
 126     virtual Tick readLastActivate();
 127     /** Reads the last tick that this thread was suspended on. */
 128     virtual Tick readLastSuspend();
 129
 130     /** Clears the function profiling information. */
 131     virtual void profileClear();
 132
 133     /** Samples the function profiling information. */
 134     virtual void profileSample();
 135
 136     /** Returns pointer to the quiesce event. */
 137     virtual EndQuiesceEvent *getQuiesceEvent()
 138     {
 139         return this->thread->quiesceEvent;
 140     }
 141 #else
 142     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 143
 144     /** Returns a pointer to this thread's process. */
 145     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 146 #endif
 147
 148     /** Returns this thread's status. */
 149     virtual Status status() const { return thread->status(); }
 150
 151     /** Sets this thread's status. */
 152     virtual void setStatus(Status new_status)
 153     { thread->setStatus(new_status); }
 154
 155     /** Set the status to Active.  Optional delay indicates number of
 156      * cycles to wait before beginning execution. */
 157     virtual void activate(int delay = 1);
 158
 159     /** Set the status to Suspended. */
 160     virtual void suspend(int delay = 0);
 161
 162     /** Set the status to Halted. */
 163     virtual void halt(int delay = 0);
 164
 165     /** Takes over execution of a thread from another CPU. */
 166     virtual void takeOverFrom(ThreadContext *old_context);
 167
 168     /** Registers statistics associated with this TC. */
 169     virtual void regStats(const std::string &name);
 170
 171     /** Serializes state. */
 172     virtual void serialize(std::ostream &os);
 173
 174     /** Unserializes state. */
 175     virtual void unserialize(Checkpoint *cp, const std::string &section);
 176
 177     /** Returns this thread's ID number. */
 178     virtual int getThreadNum() { return thread->readTid(); }
 179
 180     /** Returns the instruction this thread is currently committing.
 181      *  Only used when an instruction faults.
 182      */
 183     virtual TheISA::MachInst getInst();
 184
 185     /** Copies the architectural registers from another TC into this TC. */
 186     virtual void copyArchRegs(ThreadContext *src_tc);
 187
 188     /** Resets all architectural registers to 0. */
 189     virtual void clearArchRegs();
 190
 191     /** Reads an integer register. */
 192     virtual uint64_t readIntReg(int reg_idx);
 193
 194     virtual FloatReg readFloatReg(int reg_idx);
 195
 196     virtual FloatRegBits readFloatRegBits(int reg_idx);
 197
 198     virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
 199
 200     /** Sets an integer register to a value. */
 201     virtual void setIntReg(int reg_idx, uint64_t val);
 202
 203     virtual void setFloatReg(int reg_idx, FloatReg val);
 204
 205     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 206
 207     virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
 208                                    ThreadID tid);
 209
 210     /** Reads this thread's PC. */
 211     virtual uint64_t readPC()
 212     { return cpu->readPC(thread->readTid()); }
 213
 214     /** Sets this thread's PC. */
 215     virtual void setPC(uint64_t val);
 216
 217     /** Reads this thread's next PC. */
 218     virtual uint64_t readNextPC()
 219     { return cpu->readNextPC(thread->readTid()); }
 220
 221     /** Sets this thread's next PC. */
 222     virtual void setNextPC(uint64_t val);
 223
 224     virtual uint64_t readNextNPC()
 225     { return cpu->readNextNPC(thread->readTid()); }
 226
 227     virtual void setNextNPC(uint64_t val);
 228
 229     /** Reads a miscellaneous register. */
 230     virtual MiscReg readMiscRegNoEffect(int misc_reg)
 231     { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 232
 233     /** Reads a misc. register, including any side-effects the
 234      * read might have as defined by the architecture. */
 235     virtual MiscReg readMiscReg(int misc_reg)
 236     { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 237
 238     /** Sets a misc. register. */
 239     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 240
 241     /** Sets a misc. register, including any side-effects the
 242      * write might have as defined by the architecture. */
 243     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 244
 245     virtual int flattenIntIndex(int reg)
 246     { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
 247
 248     virtual int flattenFloatIndex(int reg)
 249     { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
 250
 251     virtual void activateContext(int delay)
 252     { cpu->activateContext(thread->readTid(), delay); }
 253
 254     virtual void deallocateContext()
 255     { cpu->deallocateContext(thread->readTid()); }
 256
 257     /** Returns the number of consecutive store conditional failures. */
 258     // @todo: Figure out where these store cond failures should go.
 259     virtual unsigned readStCondFailures()
 260     { return thread->storeCondFailures; }
 261
 262     /** Sets the number of consecutive store conditional failures. */
 263     virtual void setStCondFailures(unsigned sc_failures)
 264     { thread->storeCondFailures = sc_failures; }
 265
 266     // Only really makes sense for old CPU model.  Lots of code
 267     // outside the CPU still checks this function, so it will
 268     // always return false to keep everything working.
 269     /** Checks if the thread is misspeculating.  Because it is
 270      * very difficult to determine if the thread is
 271      * misspeculating, this is set as false. */
 272     virtual bool misspeculating() { return false; }
 273
 274 #if !FULL_SYSTEM
 275     /** Executes a syscall in SE mode. */
 276     virtual void syscall(int64_t callnum)
 277     { return cpu->syscall(callnum, thread->readTid()); }
 278 #endif
 279
 280     /** Reads the funcExeInst counter. */
 281     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 282
 283     virtual void changeRegFileContext(unsigned param,
 284                                       unsigned val)
 285     { panic("Not supported!"); }
 286 };
 287
 288 #endif