2 * Copyright (c) 2012 ARM Limited
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14 * Copyright (c) 2007 MIPS Technologies, Inc.
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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40 * Authors: Korey Sewell
44 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
45 #define __CPU_INORDER_THREAD_CONTEXT_HH__
47 #include "config/the_isa.hh"
48 #include "cpu/inorder/cpu.hh"
49 #include "cpu/inorder/thread_state.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/thread_context.hh"
52 #include "arch/kernel_stats.hh"
54 class EndQuiesceEvent;
61 * Derived ThreadContext class for use with the InOrderCPU. It
62 * provides the interface for any external objects to access a
63 * single thread's state and some general CPU state. Any time
64 * external objects try to update state through this interface,
65 * the CPU will create an event to squash all in-flight
66 * instructions in order to ensure state is maintained correctly.
67 * It must be defined specifically for the InOrderCPU because
68 * not all architectural state is located within the O3ThreadState
69 * (such as the commit PC, and registers), and specific actions
70 * must be taken when using this interface (such as squashing all
71 * in-flight instructions when doing a write to this interface).
73 class InOrderThreadContext : public ThreadContext
76 InOrderThreadContext() { }
78 /** Pointer to the CPU. */
81 /** Pointer to the thread state that this TC corrseponds to. */
82 InOrderThreadState *thread;
84 /** Returns a pointer to the ITB. */
85 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
86 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
88 /** Returns a pointer to the DTB. */
89 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
90 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
92 /** Currently InOrder model does not support CheckerCPU, this is
93 * merely here for supporting compilation of gem5 with the Checker
96 CheckerCPU *getCheckerCpuPtr() { return NULL; }
101 return cpu->getDecoderPtr(thread->contextId());
104 System *getSystemPtr() { return cpu->system; }
106 /** Returns a pointer to this CPU. */
107 BaseCPU *getCpuPtr() { return cpu; }
109 /** Returns a pointer to this CPU. */
110 std::string getCpuName() { return cpu->name(); }
112 /** Reads this CPU's ID. */
113 int cpuId() { return cpu->cpuId(); }
115 int contextId() { return thread->contextId(); }
117 void setContextId(int id) { thread->setContextId(id); }
119 /** Returns this thread's ID number. */
120 int threadId() { return thread->threadId(); }
121 void setThreadId(int id) { return thread->setThreadId(id); }
123 uint64_t readMicroPC()
126 void setMicroPC(uint64_t val) { };
128 uint64_t readNextMicroPC()
131 void setNextMicroPC(uint64_t val) { };
133 /** Returns a pointer to this thread's kernel statistics. */
134 TheISA::Kernel::Statistics *getKernelStats()
135 { return thread->kernelStats; }
137 PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
139 FSTranslatingPortProxy &getVirtProxy();
141 void initMemProxies(ThreadContext *tc)
142 { thread->initMemProxies(tc); }
144 /** Dumps the function profiling information.
147 void dumpFuncProfile();
149 /** Reads the last tick that this thread was activated on. */
150 Tick readLastActivate();
151 /** Reads the last tick that this thread was suspended on. */
152 Tick readLastSuspend();
154 /** Clears the function profiling information. */
157 /** Samples the function profiling information. */
158 void profileSample();
160 /** Returns pointer to the quiesce event. */
161 EndQuiesceEvent *getQuiesceEvent()
163 return this->thread->quiesceEvent;
166 SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
168 /** Returns a pointer to this thread's process. */
169 Process *getProcessPtr() { return thread->getProcessPtr(); }
171 /** Returns this thread's status. */
172 Status status() const { return thread->status(); }
174 /** Sets this thread's status. */
175 void setStatus(Status new_status)
176 { thread->setStatus(new_status); }
178 /** Set the status to Active. Optional delay indicates number of
179 * cycles to wait before beginning execution. */
180 void activate(Cycles delay = Cycles(1));
182 /** Set the status to Suspended. */
183 void suspend(Cycles delay = Cycles(0));
185 /** Set the status to Halted. */
186 void halt(Cycles delay = Cycles(0));
188 /** Takes over execution of a thread from another CPU. */
189 void takeOverFrom(ThreadContext *old_context);
191 /** Registers statistics associated with this TC. */
192 void regStats(const std::string &name);
194 /** Serializes state. */
195 void serialize(std::ostream &os);
197 /** Unserializes state. */
198 void unserialize(Checkpoint *cp, const std::string §ion);
200 /** Returns this thread's ID number. */
201 int getThreadNum() { return thread->threadId(); }
203 /** Copies the architectural registers from another TC into this TC. */
204 void copyArchRegs(ThreadContext *src_tc);
206 /** Resets all architectural registers to 0. */
207 void clearArchRegs();
209 /** Reads an integer register. */
210 uint64_t readIntReg(int reg_idx);
212 FloatReg readFloatReg(int reg_idx);
214 FloatRegBits readFloatRegBits(int reg_idx);
216 uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
218 /** Sets an integer register to a value. */
219 void setIntReg(int reg_idx, uint64_t val);
221 void setFloatReg(int reg_idx, FloatReg val);
223 void setFloatRegBits(int reg_idx, FloatRegBits val);
225 void setRegOtherThread(int misc_reg,
229 /** Reads this thread's PC. */
230 TheISA::PCState pcState()
231 { return cpu->pcState(thread->threadId()); }
233 /** Sets this thread's PC. */
234 void pcState(const TheISA::PCState &val)
235 { cpu->pcState(val, thread->threadId()); }
237 /** Needs to be implemented for future CheckerCPU support.
238 * See O3CPU for examples on how to integrate Checker.
240 void pcStateNoRecord(const TheISA::PCState &val)
244 { return cpu->instAddr(thread->threadId()); }
247 { return cpu->nextInstAddr(thread->threadId()); }
250 { return cpu->microPC(thread->threadId()); }
252 /** Reads a miscellaneous register. */
253 MiscReg readMiscRegNoEffect(int misc_reg)
254 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
256 /** Reads a misc. register, including any side-effects the
257 * read might have as defined by the architecture. */
258 MiscReg readMiscReg(int misc_reg)
259 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
261 /** Sets a misc. register. */
262 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
264 /** Sets a misc. register, including any side-effects the
265 * write might have as defined by the architecture. */
266 void setMiscReg(int misc_reg, const MiscReg &val);
268 int flattenIntIndex(int reg)
269 { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
271 int flattenFloatIndex(int reg)
272 { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
274 void activateContext(Cycles delay)
275 { cpu->activateContext(thread->threadId(), delay); }
277 void deallocateContext()
278 { cpu->deallocateContext(thread->threadId()); }
280 /** Returns the number of consecutive store conditional failures. */
281 // @todo: Figure out where these store cond failures should go.
282 unsigned readStCondFailures()
283 { return thread->storeCondFailures; }
285 /** Sets the number of consecutive store conditional failures. */
286 void setStCondFailures(unsigned sc_failures)
287 { thread->storeCondFailures = sc_failures; }
289 // Only really makes sense for old CPU model. Lots of code
290 // outside the CPU still checks this function, so it will
291 // always return false to keep everything working.
292 /** Checks if the thread is misspeculating. Because it is
293 * very difficult to determine if the thread is
294 * misspeculating, this is set as false. */
295 bool misspeculating() { return false; }
297 /** Executes a syscall in SE mode. */
298 void syscall(int64_t callnum)
299 { return cpu->syscall(callnum, thread->threadId()); }
301 /** Reads the funcExeInst counter. */
302 Counter readFuncExeInst() { return thread->funcExeInst; }
304 void changeRegFileContext(unsigned param,
306 { panic("Not supported!"); }
308 uint64_t readIntRegFlat(int idx);
309 void setIntRegFlat(int idx, uint64_t val);
311 FloatReg readFloatRegFlat(int idx);
312 void setFloatRegFlat(int idx, FloatReg val);
314 FloatRegBits readFloatRegBitsFlat(int idx);
315 void setFloatRegBitsFlat(int idx, FloatRegBits val);