src/cpu/inst_res.hh

   1 /*
   2  * Copyright (c) 2016-2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __CPU_INST_RES_HH__
  39 #define __CPU_INST_RES_HH__
  40
  41 #include <type_traits>
  42
  43 #include "arch/generic/types.hh"
  44 #include "arch/generic/vec_reg.hh"
  45
  46 class InstResult {
  47     using VecRegContainer = TheISA::VecRegContainer;
  48     using VecElem = TheISA::VecElem;
  49     using VecPredRegContainer = TheISA::VecPredRegContainer;
  50   public:
  51     union MultiResult {
  52         uint64_t integer;
  53         double dbl;
  54         VecRegContainer vector;
  55         VecElem vecElem;
  56         VecPredRegContainer pred;
  57         MultiResult() {}
  58     };
  59
  60     enum class ResultType {
  61         Scalar,
  62         VecElem,
  63         VecReg,
  64         VecPredReg,
  65         NumResultTypes,
  66         Invalid
  67     };
  68
  69   private:
  70     MultiResult result;
  71     ResultType type;
  72
  73   public:
  74     /** Default constructor creates an invalid result. */
  75     InstResult() : type(ResultType::Invalid) { }
  76     InstResult(const InstResult &) = default;
  77     /** Scalar result from scalar. */
  78     template<typename T>
  79     explicit InstResult(T i, const ResultType& t) : type(t) {
  80         static_assert(std::is_integral<T>::value ^
  81                         std::is_floating_point<T>::value,
  82                 "Parameter type is neither integral nor fp, or it is both");
  83         if (std::is_integral<T>::value) {
  84             result.integer = i;
  85         } else if (std::is_floating_point<T>::value) {
  86             result.dbl = i;
  87         }
  88     }
  89     /** Vector result. */
  90     explicit InstResult(const VecRegContainer& v, const ResultType& t)
  91         : type(t) { result.vector = v; }
  92     /** Predicate result. */
  93     explicit InstResult(const VecPredRegContainer& v, const ResultType& t)
  94         : type(t) { result.pred = v; }
  95
  96     InstResult& operator=(const InstResult& that) {
  97         type = that.type;
  98         switch (type) {
  99         /* Given that misc regs are not written to, there may be invalids in
 100          * the result stack. */
 101         case ResultType::Invalid:
 102             break;
 103         case ResultType::Scalar:
 104             result.integer = that.result.integer;
 105             break;
 106         case ResultType::VecElem:
 107             result.vecElem = that.result.vecElem;
 108             break;
 109         case ResultType::VecReg:
 110             result.vector = that.result.vector;
 111             break;
 112         case ResultType::VecPredReg:
 113             result.pred = that.result.pred;
 114             break;
 115
 116         default:
 117             panic("Assigning result from unknown result type");
 118             break;
 119         }
 120         return *this;
 121     }
 122     /**
 123      * Result comparison
 124      * Two invalid results always differ.
 125      */
 126     bool operator==(const InstResult& that) const {
 127         if (this->type != that.type)
 128             return false;
 129         switch (type) {
 130         case ResultType::Scalar:
 131             return result.integer == that.result.integer;
 132         case ResultType::VecElem:
 133             return result.vecElem == that.result.vecElem;
 134         case ResultType::VecReg:
 135             return result.vector == that.result.vector;
 136         case ResultType::VecPredReg:
 137             return result.pred == that.result.pred;
 138         case ResultType::Invalid:
 139             return false;
 140         default:
 141             panic("Unknown type of result: %d\n", (int)type);
 142         }
 143     }
 144
 145     bool operator!=(const InstResult& that) const {
 146         return !operator==(that);
 147     }
 148
 149     /** Checks */
 150     /** @{ */
 151     /** Is this a scalar result?. */
 152     bool isScalar() const { return type == ResultType::Scalar; }
 153     /** Is this a vector result?. */
 154     bool isVector() const { return type == ResultType::VecReg; }
 155     /** Is this a vector element result?. */
 156     bool isVecElem() const { return type == ResultType::VecElem; }
 157     /** Is this a predicate result?. */
 158     bool isPred() const { return type == ResultType::VecPredReg; }
 159     /** Is this a valid result?. */
 160     bool isValid() const { return type != ResultType::Invalid; }
 161     /** @} */
 162
 163     /** Explicit cast-like operations. */
 164     /** @{ */
 165     const uint64_t&
 166     asInteger() const
 167     {
 168         assert(isScalar());
 169         return result.integer;
 170     }
 171
 172     /** Cast to integer without checking type.
 173      * This is required to have the o3 cpu checker happy, as it
 174      * compares results as integers without being fully aware of
 175      * their nature. */
 176     const uint64_t&
 177     asIntegerNoAssert() const
 178     {
 179         return result.integer;
 180     }
 181     const VecRegContainer&
 182     asVector() const
 183     {
 184         panic_if(!isVector(), "Converting scalar (or invalid) to vector!!");
 185         return result.vector;
 186     }
 187     const VecElem&
 188     asVectorElem() const
 189     {
 190         panic_if(!isVecElem(), "Converting scalar (or invalid) to vector!!");
 191         return result.vecElem;
 192     }
 193
 194     const VecPredRegContainer&
 195     asPred() const
 196     {
 197         panic_if(!isPred(), "Converting scalar (or invalid) to predicate!!");
 198         return result.pred;
 199     }
 200
 201     /** @} */
 202 };
 203
 204 #endif // __CPU_INST_RES_HH__