params: Deprecate old-style constructors; update most SimObject constructors.
[gem5.git] / src / cpu / inteltrace.cc
1 /*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34 #include <iomanip>
35
36 #include "cpu/exetrace.hh"
37 #include "cpu/inteltrace.hh"
38 #include "cpu/static_inst.hh"
39
40 using namespace std;
41 using namespace TheISA;
42
43 namespace Trace {
44
45 void
46 Trace::IntelTraceRecord::dump()
47 {
48 ostream &outs = Trace::output();
49 ccprintf(outs, "%7d ) ", when);
50 outs << "0x" << hex << PC << ":\t";
51 if (staticInst->isLoad()) {
52 ccprintf(outs, "<RD %#x>", addr);
53 } else if (staticInst->isStore()) {
54 ccprintf(outs, "<WR %#x>", addr);
55 }
56 outs << endl;
57 }
58
59 /* namespace Trace */ }
60
61 ////////////////////////////////////////////////////////////////////////
62 //
63 // ExeTracer Simulation Object
64 //
65 Trace::IntelTrace *
66 IntelTraceParams::create()
67 {
68 return new Trace::IntelTrace(this);
69 };