2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
35 #include "base/trace.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/intr_control.hh"
39 #include "sim/sim_object.hh"
43 IntrControl::IntrControl(const Params
*p
)
44 : SimObject(p
), sys(p
->sys
)
48 IntrControl::post(int cpu_id
, int int_num
, int index
)
50 DPRINTF(IntrControl
, "post %d:%d (cpu %d)\n", int_num
, index
, cpu_id
);
51 std::vector
<ThreadContext
*> &tcvec
= sys
->threadContexts
;
52 BaseCPU
*cpu
= tcvec
[cpu_id
]->getCpuPtr();
53 cpu
->postInterrupt(int_num
, index
);
57 IntrControl::clear(int cpu_id
, int int_num
, int index
)
59 DPRINTF(IntrControl
, "clear %d:%d (cpu %d)\n", int_num
, index
, cpu_id
);
60 std::vector
<ThreadContext
*> &tcvec
= sys
->threadContexts
;
61 BaseCPU
*cpu
= tcvec
[cpu_id
]->getCpuPtr();
62 cpu
->clearInterrupt(int_num
, index
);
66 IntrControlParams::create()
68 return new IntrControl(this);