src/cpu/kvm/arm_cpu.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andreas Sandberg
  38  */
  39
  40 #include <linux/kvm.h>
  41
  42 #include <algorithm>
  43 #include <cerrno>
  44 #include <memory>
  45
  46 #include "arch/registers.hh"
  47 #include "cpu/kvm/arm_cpu.hh"
  48 #include "cpu/kvm/base.hh"
  49 #include "debug/Kvm.hh"
  50 #include "debug/KvmContext.hh"
  51 #include "debug/KvmInt.hh"
  52 #include "sim/pseudo_inst.hh"
  53
  54 using namespace ArmISA;
  55
  56 #define EXTRACT_FIELD(val, mask, shift)         \
  57     (((val) & (mask)) >> (shift))
  58
  59 #define REG_IS_ARM(id)                          \
  60     (((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
  61
  62 #define REG_IS_32BIT(id)                                \
  63     (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
  64
  65 #define REG_IS_64BIT(id)                                \
  66     (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
  67
  68 #define REG_IS_CP(id, cp)                       \
  69     (((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
  70
  71 #define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
  72
  73 #define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
  74 #define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
  75 // HACK: These aren't really defined in any of the headers, so we'll
  76 // assume some reasonable values for now.
  77 #define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
  78 #define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
  79
  80 #define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
  81
  82
  83 // There is no constant in the kernel headers defining the mask to use
  84 // to get the core register index. We'll just do what they do
  85 // internally.
  86 #define REG_CORE_IDX(id)                                                \
  87     (~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE))
  88
  89 #define REG_CP(id)                                                      \
  90     EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
  91
  92 #define REG_CRN(id)                                                     \
  93     EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
  94
  95 #define REG_OPC1(id)                                                    \
  96     EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
  97
  98 #define REG_CRM(id)                                                     \
  99     EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
 100
 101 #define REG_OPC2(id)                                                    \
 102     EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
 103
 104 #define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
 105         (KVM_REG_ARM | KVM_REG_SIZE_U32) |      \
 106         ((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
 107         ((crn) << KVM_REG_ARM_32_CRN_SHIFT) |   \
 108         ((opc1) << KVM_REG_ARM_OPC1_SHIFT) |    \
 109         ((crm) << KVM_REG_ARM_CRM_SHIFT) |      \
 110         ((opc2) << KVM_REG_ARM_32_OPC2_SHIFT))
 111
 112 #define REG_CP64(cpnum, opc1, crm) (            \
 113         (KVM_REG_ARM | KVM_REG_SIZE_U64) |      \
 114         ((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
 115         ((opc1) << KVM_REG_ARM_OPC1_SHIFT) |    \
 116         ((crm) << KVM_REG_ARM_CRM_SHIFT))
 117
 118 #define REG_CORE32(kname) (                     \
 119         (KVM_REG_ARM | KVM_REG_SIZE_U32) |      \
 120         (KVM_REG_ARM_CORE) |                    \
 121         (KVM_REG_ARM_CORE_REG(kname)))
 122
 123 #define REG_VFP32(regno) (                      \
 124         (KVM_REG_ARM | KVM_REG_SIZE_U32) |      \
 125         KVM_REG_ARM_VFP | (regno))
 126
 127 #define REG_VFP64(regno) (                      \
 128         (KVM_REG_ARM | KVM_REG_SIZE_U64) |      \
 129         KVM_REG_ARM_VFP | (regno))
 130
 131 #define REG_DEMUX32(dmxid, val) (               \
 132         (KVM_REG_ARM | KVM_REG_SIZE_U32) |      \
 133         (dmxid) | (val))
 134
 135 // Some of the co-processor registers are invariants and must have the
 136 // same value on both the host and the guest. We need to keep a list
 137 // of these to prevent gem5 from fiddling with them on the guest.
 138 static uint64_t invariant_reg_vector[] = {
 139     REG_CP32(15, 0, 0, 0, 0), // MIDR
 140     REG_CP32(15, 0, 0, 0, 1), // CTR
 141     REG_CP32(15, 0, 0, 0, 2), // TCMTR
 142     REG_CP32(15, 0, 0, 0, 3), // TLBTR
 143     REG_CP32(15, 0, 0, 0, 6), // REVIDR
 144
 145     REG_CP32(15, 0, 0, 1, 0), // ID_PFR0
 146     REG_CP32(15, 0, 0, 1, 1), // ID_PFR1
 147     REG_CP32(15, 0, 0, 1, 2), // ID_DFR0
 148     REG_CP32(15, 0, 0, 1, 3), // ID_AFR0
 149     REG_CP32(15, 0, 0, 1, 4), // ID_MMFR0
 150     REG_CP32(15, 0, 0, 1, 5), // ID_MMFR1
 151     REG_CP32(15, 0, 0, 1, 6), // ID_MMFR2
 152     REG_CP32(15, 0, 0, 1, 7), // ID_MMFR3
 153
 154     REG_CP32(15, 0, 0, 2, 0), // ID_ISAR0
 155     REG_CP32(15, 0, 0, 2, 1), // ID_ISAR1
 156     REG_CP32(15, 0, 0, 2, 2), // ID_ISAR2
 157     REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
 158     REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
 159     REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
 160
 161     REG_CP32(15, 0, 1, 0, 0), // CSSIDR
 162     REG_CP32(15, 0, 1, 0, 1), // CLIDR
 163     REG_CP32(15, 0, 1, 0, 7), // AIDR
 164
 165     REG_VFP32(KVM_REG_ARM_VFP_MVFR0),
 166     REG_VFP32(KVM_REG_ARM_VFP_MVFR1),
 167     REG_VFP32(KVM_REG_ARM_VFP_FPSID),
 168
 169     REG_DEMUX32(KVM_REG_ARM_DEMUX_ID_CCSIDR, 0),
 170 };
 171
 172 const static uint64_t KVM_REG64_TTBR0(REG_CP64(15, 0, 2));
 173 const static uint64_t KVM_REG64_TTBR1(REG_CP64(15, 1, 2));
 174
 175 #define INTERRUPT_ID(type, vcpu, irq) (                    \
 176         ((type) << KVM_ARM_IRQ_TYPE_SHIFT) |               \
 177         ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) |               \
 178         ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
 179
 180 #define INTERRUPT_VCPU_IRQ(vcpu)                                \
 181     INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
 182
 183 #define INTERRUPT_VCPU_FIQ(vcpu)                                \
 184     INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
 185
 186
 187 #define COUNT_OF(l) (sizeof(l) / sizeof(*l))
 188
 189 const std::set<uint64_t> ArmKvmCPU::invariant_regs(
 190     invariant_reg_vector,
 191     invariant_reg_vector + COUNT_OF(invariant_reg_vector));
 192
 193
 194 ArmKvmCPU::KvmIntRegInfo ArmKvmCPU::kvmIntRegs[] = {
 195     { REG_CORE32(usr_regs.ARM_r0), INTREG_R0, "R0" },
 196     { REG_CORE32(usr_regs.ARM_r1), INTREG_R1, "R1" },
 197     { REG_CORE32(usr_regs.ARM_r2), INTREG_R2, "R2" },
 198     { REG_CORE32(usr_regs.ARM_r3), INTREG_R3, "R3" },
 199     { REG_CORE32(usr_regs.ARM_r4), INTREG_R4, "R4" },
 200     { REG_CORE32(usr_regs.ARM_r5), INTREG_R5, "R5" },
 201     { REG_CORE32(usr_regs.ARM_r6), INTREG_R6, "R6" },
 202     { REG_CORE32(usr_regs.ARM_r7), INTREG_R7, "R7" },
 203     { REG_CORE32(usr_regs.ARM_r8), INTREG_R8, "R8" },
 204     { REG_CORE32(usr_regs.ARM_r9), INTREG_R9, "R9" },
 205     { REG_CORE32(usr_regs.ARM_r10), INTREG_R10, "R10" },
 206     { REG_CORE32(usr_regs.ARM_fp), INTREG_R11, "R11" },
 207     { REG_CORE32(usr_regs.ARM_ip), INTREG_R12, "R12" },
 208     { REG_CORE32(usr_regs.ARM_sp), INTREG_R13, "R13(USR)" },
 209     { REG_CORE32(usr_regs.ARM_lr), INTREG_R14, "R14(USR)" },
 210
 211     { REG_CORE32(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)" },
 212     { REG_CORE32(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)" },
 213
 214     { REG_CORE32(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)" },
 215     { REG_CORE32(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)" },
 216
 217     { REG_CORE32(und_regs[0]), INTREG_SP_UND, "R13(UND)" },
 218     { REG_CORE32(und_regs[1]), INTREG_LR_UND, "R14(UND)" },
 219
 220     { REG_CORE32(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)" },
 221     { REG_CORE32(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)" },
 222
 223
 224     { REG_CORE32(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)" },
 225     { REG_CORE32(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)" },
 226     { REG_CORE32(fiq_regs[2]), INTREG_R10_FIQ, "R10(FIQ)" },
 227     { REG_CORE32(fiq_regs[3]), INTREG_R11_FIQ, "R11(FIQ)" },
 228     { REG_CORE32(fiq_regs[4]), INTREG_R12_FIQ, "R12(FIQ)" },
 229     { REG_CORE32(fiq_regs[5]), INTREG_R13_FIQ, "R13(FIQ)" },
 230     { REG_CORE32(fiq_regs[6]), INTREG_R14_FIQ, "R14(FIQ)" },
 231     { 0, NUM_INTREGS, NULL }
 232 };
 233
 234 ArmKvmCPU::KvmCoreMiscRegInfo ArmKvmCPU::kvmCoreMiscRegs[] = {
 235     { REG_CORE32(usr_regs.ARM_cpsr), MISCREG_CPSR, "CPSR" },
 236     { REG_CORE32(svc_regs[2]), MISCREG_SPSR_SVC, "SPSR(SVC)" },
 237     { REG_CORE32(abt_regs[2]), MISCREG_SPSR_ABT, "SPSR(ABT)" },
 238     { REG_CORE32(und_regs[2]), MISCREG_SPSR_UND, "SPSR(UND)" },
 239     { REG_CORE32(irq_regs[2]), MISCREG_SPSR_IRQ, "SPSR(IRQ)" },
 240     { REG_CORE32(fiq_regs[2]), MISCREG_SPSR_FIQ, "SPSR(FIQ)" },
 241     { 0, NUM_MISCREGS }
 242 };
 243
 244 ArmKvmCPU::ArmKvmCPU(ArmKvmCPUParams *params)
 245     : BaseKvmCPU(params),
 246       irqAsserted(false), fiqAsserted(false)
 247 {
 248 }
 249
 250 ArmKvmCPU::~ArmKvmCPU()
 251 {
 252 }
 253
 254 void
 255 ArmKvmCPU::startup()
 256 {
 257     BaseKvmCPU::startup();
 258
 259     /* TODO: This needs to be moved when we start to support VMs with
 260      * multiple threads since kvmArmVCpuInit requires that all CPUs in
 261      * the VM have been created.
 262      */
 263     /* TODO: The CPU type needs to be configurable once KVM on ARM
 264      * starts to support more CPUs.
 265      */
 266     kvmArmVCpuInit(KVM_ARM_TARGET_CORTEX_A15);
 267 }
 268
 269 Tick
 270 ArmKvmCPU::kvmRun(Tick ticks)
 271 {
 272     bool simFIQ(interrupts->checkRaw(INT_FIQ));
 273     bool simIRQ(interrupts->checkRaw(INT_IRQ));
 274
 275     if (fiqAsserted != simFIQ) {
 276         fiqAsserted = simFIQ;
 277         DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
 278         vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
 279     }
 280     if (irqAsserted != simIRQ) {
 281         irqAsserted = simIRQ;
 282         DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
 283         vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
 284     }
 285
 286     return BaseKvmCPU::kvmRun(ticks);
 287 }
 288
 289 void
 290 ArmKvmCPU::dump()
 291 {
 292     dumpKvmStateCore();
 293     dumpKvmStateMisc();
 294 }
 295
 296 void
 297 ArmKvmCPU::updateKvmState()
 298 {
 299     DPRINTF(KvmContext, "Updating KVM state...\n");
 300
 301     updateKvmStateCore();
 302     updateKvmStateMisc();
 303 }
 304
 305 void
 306 ArmKvmCPU::updateThreadContext()
 307 {
 308     DPRINTF(KvmContext, "Updating gem5 state...\n");
 309
 310     updateTCStateCore();
 311     updateTCStateMisc();
 312 }
 313
 314 Tick
 315 ArmKvmCPU::onKvmExitHypercall()
 316 {
 317     ThreadContext *tc(getContext(0));
 318     const uint32_t reg_ip(tc->readIntRegFlat(INTREG_R12));
 319     const uint8_t func((reg_ip >> 8) & 0xFF);
 320     const uint8_t subfunc(reg_ip & 0xFF);
 321
 322     DPRINTF(Kvm, "KVM Hypercall: 0x%x/0x%x\n", func, subfunc);
 323     const uint64_t ret(PseudoInst::pseudoInst(getContext(0), func, subfunc));
 324
 325     // Just set the return value using the KVM API instead of messing
 326     // with the context. We could have used the context, but that
 327     // would have required us to request a full context sync.
 328     setOneReg(REG_CORE32(usr_regs.ARM_r0), ret & 0xFFFFFFFF);
 329     setOneReg(REG_CORE32(usr_regs.ARM_r1), (ret >> 32) & 0xFFFFFFFF);
 330
 331     return 0;
 332 }
 333
 334 const ArmKvmCPU::RegIndexVector &
 335 ArmKvmCPU::getRegList() const
 336 {
 337     if (_regIndexList.size() == 0) {
 338         std::unique_ptr<struct kvm_reg_list> regs;
 339         uint64_t i(1);
 340
 341         do {
 342             i <<= 1;
 343             regs.reset((struct kvm_reg_list *)
 344                        operator new(sizeof(struct kvm_reg_list) +
 345                                     i * sizeof(uint64_t)));
 346             regs->n = i;
 347         } while (!getRegList(*regs));
 348         _regIndexList.assign(regs->reg,
 349                              regs->reg + regs->n);
 350     }
 351
 352     return _regIndexList;
 353 }
 354
 355 void
 356 ArmKvmCPU::kvmArmVCpuInit(uint32_t target)
 357 {
 358     struct kvm_vcpu_init init;
 359
 360     memset(&init, 0, sizeof(init));
 361
 362     init.target = target;
 363
 364     kvmArmVCpuInit(init);
 365 }
 366
 367 void
 368 ArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init)
 369 {
 370     if (ioctl(KVM_ARM_VCPU_INIT, (void *)&init) == -1)
 371         panic("KVM: Failed to initialize vCPU\n");
 372 }
 373
 374 MiscRegIndex
 375 ArmKvmCPU::decodeCoProcReg(uint64_t id) const
 376 {
 377     const unsigned cp(REG_CP(id));
 378     const bool is_reg32(REG_IS_32BIT(id));
 379     const bool is_reg64(REG_IS_64BIT(id));
 380
 381     // CP numbers larger than 15 are reserved for KVM extensions
 382     if (cp > 15)
 383         return NUM_MISCREGS;
 384
 385     const unsigned crm(REG_CRM(id));
 386     const unsigned crn(REG_CRN(id));
 387     const unsigned opc1(REG_OPC1(id));
 388     const unsigned opc2(REG_OPC2(id));
 389
 390     if (is_reg32) {
 391         switch (cp) {
 392           case 14:
 393             return decodeCP14Reg(crn, opc1, crm, opc2);
 394
 395           case 15:
 396             return decodeCP15Reg(crn, opc1, crm, opc2);
 397
 398           default:
 399             return NUM_MISCREGS;
 400         }
 401     } else if(is_reg64) {
 402         return NUM_MISCREGS;
 403     } else {
 404         warn("Unhandled register length, register (0x%x) ignored.\n");
 405         return NUM_MISCREGS;
 406     }
 407 }
 408
 409 ArmISA::MiscRegIndex
 410 ArmKvmCPU::decodeVFPCtrlReg(uint64_t id) const
 411 {
 412     if (!REG_IS_ARM(id) || !REG_IS_VFP(id) || !REG_IS_VFP_CTRL(id))
 413         return NUM_MISCREGS;
 414
 415     const unsigned vfp_reg(REG_VFP_REG(id));
 416     switch (vfp_reg) {
 417       case KVM_REG_ARM_VFP_FPSID: return MISCREG_FPSID;
 418       case KVM_REG_ARM_VFP_FPSCR: return MISCREG_FPSCR;
 419       case KVM_REG_ARM_VFP_MVFR0: return MISCREG_MVFR0;
 420       case KVM_REG_ARM_VFP_MVFR1: return MISCREG_MVFR1;
 421       case KVM_REG_ARM_VFP_FPEXC: return MISCREG_FPEXC;
 422
 423       case KVM_REG_ARM_VFP_FPINST:
 424       case KVM_REG_ARM_VFP_FPINST2:
 425         warn_once("KVM: FPINST not implemented.\n");
 426         return NUM_MISCREGS;
 427
 428       default:
 429         return NUM_MISCREGS;
 430     }
 431 }
 432
 433 bool
 434 ArmKvmCPU::isInvariantReg(uint64_t id)
 435 {
 436     /* Mask away the value field from multiplexed registers, we assume
 437      * that entire groups of multiplexed registers can be treated as
 438      * invariant. */
 439     if (REG_IS_ARM(id) && REG_IS_DEMUX(id))
 440         id &= ~KVM_REG_ARM_DEMUX_VAL_MASK;
 441
 442     return invariant_regs.find(id) != invariant_regs.end();
 443 }
 444
 445 bool
 446 ArmKvmCPU::getRegList(struct kvm_reg_list &regs) const
 447 {
 448     if (ioctl(KVM_GET_REG_LIST, (void *)&regs) == -1) {
 449         if (errno == E2BIG) {
 450             return false;
 451         } else {
 452             panic("KVM: Failed to get vCPU register list (errno: %i)\n",
 453                   errno);
 454         }
 455     } else {
 456         return true;
 457     }
 458 }
 459
 460 void
 461 ArmKvmCPU::dumpKvmStateCore()
 462 {
 463     /* Print core registers */
 464     uint32_t pc(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
 465     inform("PC: 0x%x\n", pc);
 466
 467     for (const KvmIntRegInfo *ri(kvmIntRegs);
 468          ri->idx != NUM_INTREGS; ++ri) {
 469
 470         uint32_t value(getOneRegU32(ri->id));
 471         inform("%s: 0x%x\n", ri->name, value);
 472     }
 473
 474     for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
 475          ri->idx != NUM_MISCREGS; ++ri) {
 476
 477         uint32_t value(getOneRegU32(ri->id));
 478         inform("%s: 0x%x\n", miscRegName[ri->idx], value);
 479     }
 480 }
 481
 482 void
 483 ArmKvmCPU::dumpKvmStateMisc()
 484 {
 485     /* Print co-processor registers */
 486     const RegIndexVector &reg_ids(getRegList());;
 487     for (RegIndexVector::const_iterator it(reg_ids.begin());
 488          it != reg_ids.end(); ++it) {
 489         uint64_t id(*it);
 490
 491         if (REG_IS_ARM(id) && REG_CP(id) <= 15) {
 492             dumpKvmStateCoProc(id);
 493         } else if (REG_IS_ARM(id) && REG_IS_VFP(id)) {
 494             dumpKvmStateVFP(id);
 495         } else if (REG_IS_ARM(id) && REG_IS_DEMUX(id)) {
 496             switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 497               case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 498                 inform("CCSIDR [0x%x]: %s\n",
 499                        EXTRACT_FIELD(id,
 500                                      KVM_REG_ARM_DEMUX_VAL_MASK,
 501                                      KVM_REG_ARM_DEMUX_VAL_SHIFT),
 502                        getAndFormatOneReg(id));
 503                 break;
 504               default:
 505                 inform("DEMUX [0x%x, 0x%x]: %s\n",
 506                        EXTRACT_FIELD(id,
 507                                      KVM_REG_ARM_DEMUX_ID_MASK,
 508                                      KVM_REG_ARM_DEMUX_ID_SHIFT),
 509                        EXTRACT_FIELD(id,
 510                                      KVM_REG_ARM_DEMUX_VAL_MASK,
 511                                      KVM_REG_ARM_DEMUX_VAL_SHIFT),
 512                        getAndFormatOneReg(id));
 513                 break;
 514             }
 515         } else if (!REG_IS_CORE(id)) {
 516             inform("0x%x: %s\n", id, getAndFormatOneReg(id));
 517         }
 518     }
 519 }
 520
 521 void
 522 ArmKvmCPU::dumpKvmStateCoProc(uint64_t id)
 523 {
 524     assert(REG_IS_ARM(id));
 525     assert(REG_CP(id) <= 15);
 526
 527     if (REG_IS_32BIT(id)) {
 528         // 32-bit co-proc registers
 529         MiscRegIndex idx(decodeCoProcReg(id));
 530         uint32_t value(getOneRegU32(id));
 531
 532         if (idx != NUM_MISCREGS &&
 533             !(idx >= MISCREG_CP15_UNIMP_START && idx < MISCREG_CP15_END)) {
 534             const char *name(miscRegName[idx]);
 535             const unsigned m5_ne(tc->readMiscRegNoEffect(idx));
 536             const unsigned m5_e(tc->readMiscReg(idx));
 537             inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: "
 538                    "[%s]: 0x%x/0x%x\n",
 539                    REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
 540                    REG_OPC2(id), isInvariantReg(id),
 541                    name, value, m5_e);
 542             if (m5_e != m5_ne) {
 543                 inform("readMiscReg: %x, readMiscRegNoEffect: %x\n",
 544                        m5_e, m5_ne);
 545             }
 546         } else {
 547             const char *name(idx != NUM_MISCREGS ? miscRegName[idx] : "-");
 548             inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: [%s]: "
 549                    "0x%x\n",
 550                    REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
 551                    REG_OPC2(id), isInvariantReg(id), name, value);
 552         }
 553     } else {
 554         inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i "
 555                "len: 0x%x]: %s\n",
 556                REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
 557                REG_OPC2(id), isInvariantReg(id),
 558                EXTRACT_FIELD(id, KVM_REG_SIZE_MASK, KVM_REG_SIZE_SHIFT),
 559                getAndFormatOneReg(id));
 560     }
 561 }
 562
 563 void
 564 ArmKvmCPU::dumpKvmStateVFP(uint64_t id)
 565 {
 566     assert(REG_IS_ARM(id));
 567     assert(REG_IS_VFP(id));
 568
 569     if (REG_IS_VFP_REG(id)) {
 570         const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
 571         inform("VFP reg %i: %s", idx, getAndFormatOneReg(id));
 572     } else if (REG_IS_VFP_CTRL(id)) {
 573         MiscRegIndex idx(decodeVFPCtrlReg(id));
 574         if (idx != NUM_MISCREGS) {
 575             inform("VFP [%s]: %s", miscRegName[idx], getAndFormatOneReg(id));
 576         } else {
 577             inform("VFP [0x%x]: %s", id, getAndFormatOneReg(id));
 578         }
 579     } else {
 580         inform("VFP [0x%x]: %s", id, getAndFormatOneReg(id));
 581     }
 582 }
 583
 584 void
 585 ArmKvmCPU::updateKvmStateCore()
 586 {
 587     for (const KvmIntRegInfo *ri(kvmIntRegs);
 588          ri->idx != NUM_INTREGS; ++ri) {
 589
 590         uint64_t value(tc->readIntRegFlat(ri->idx));
 591         DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
 592         setOneReg(ri->id, value);
 593     }
 594
 595     DPRINTF(KvmContext, "kvm(PC) := 0x%x\n", tc->instAddr());
 596     setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->instAddr());
 597
 598     for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
 599          ri->idx != NUM_MISCREGS; ++ri) {
 600
 601         uint64_t value(tc->readMiscReg(ri->idx));
 602         DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
 603         setOneReg(ri->id, value);
 604     }
 605
 606     if (DTRACE(KvmContext))
 607         dumpKvmStateCore();
 608 }
 609
 610 void
 611 ArmKvmCPU::updateKvmStateMisc()
 612 {
 613     static bool warned(false); // We can't use warn_once since we want
 614                                // to show /all/ registers
 615
 616     const RegIndexVector &regs(getRegList());
 617
 618     for (RegIndexVector::const_iterator it(regs.begin());
 619          it != regs.end();
 620          ++it) {
 621
 622         if (!REG_IS_ARM(*it)) {
 623             if (!warned)
 624                 warn("Skipping non-ARM register: 0x%x\n", *it);
 625         } else if (isInvariantReg(*it)) {
 626             DPRINTF(Kvm, "Skipping invariant register: 0x%x\n", *it);
 627         } else if (REG_IS_CORE(*it)) {
 628             // Core registers are handled in updateKvmStateCore
 629             continue;
 630         } else if (REG_CP(*it) <= 15) {
 631             updateKvmStateCoProc(*it, !warned);
 632         } else if (REG_IS_VFP(*it)) {
 633             updateKvmStateVFP(*it, !warned);
 634         } else {
 635             if (!warned) {
 636                 warn("Skipping register with unknown CP (%i) id: 0x%x\n",
 637                      REG_CP(*it), *it);
 638             }
 639         }
 640
 641     }
 642
 643     warned = true;
 644     if (DTRACE(KvmContext))
 645         dumpKvmStateMisc();
 646 }
 647
 648 void
 649 ArmKvmCPU::updateKvmStateCoProc(uint64_t id, bool show_warnings)
 650 {
 651     MiscRegIndex reg(decodeCoProcReg(id));
 652
 653     assert(REG_IS_ARM(id));
 654     assert(REG_CP(id) <= 15);
 655
 656     if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
 657         // HACK HACK HACK: Workaround for 64-bit TTBRx
 658         reg = (id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1);
 659         if (show_warnings)
 660             hack("KVM: 64-bit TTBBRx workaround\n");
 661     }
 662
 663     if (reg == NUM_MISCREGS) {
 664         if (show_warnings) {
 665             warn("KVM: Ignoring unknown KVM co-processor register (0x%.8x):\n",
 666                  id);
 667             warn("\t0x%x: [CP: %i 64: %i CRn: c%i opc1: %.2i CRm: c%i"
 668                  " opc2: %i]\n",
 669                  id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
 670                  REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
 671         }
 672     } else if (reg >= MISCREG_CP15_UNIMP_START && reg < MISCREG_CP15_END) {
 673         if (show_warnings)
 674             warn("KVM: Co-processor reg. %s not implemented by gem5.\n",
 675                  miscRegName[reg]);
 676     } else {
 677         setOneReg(id, tc->readMiscRegNoEffect(reg));
 678     }
 679 }
 680
 681
 682 void
 683 ArmKvmCPU::updateKvmStateVFP(uint64_t id, bool show_warnings)
 684 {
 685     assert(REG_IS_ARM(id));
 686     assert(REG_IS_VFP(id));
 687
 688     if (REG_IS_VFP_REG(id)) {
 689         if (!REG_IS_64BIT(id)) {
 690             if (show_warnings)
 691                 warn("Unexpected VFP register length (reg: 0x%x).\n", id);
 692             return;
 693         }
 694         const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
 695         const unsigned idx_base(idx << 1);
 696         const unsigned idx_hi(idx_base + 1);
 697         const unsigned idx_lo(idx_base + 0);
 698         uint64_t value(
 699             ((uint64_t)tc->readFloatRegBitsFlat(idx_hi) << 32) |
 700             tc->readFloatRegBitsFlat(idx_lo));
 701
 702         setOneReg(id, value);
 703     } else if (REG_IS_VFP_CTRL(id)) {
 704         MiscRegIndex idx(decodeVFPCtrlReg(id));
 705         if (idx == NUM_MISCREGS) {
 706             if (show_warnings)
 707                 warn("Unhandled VFP control register: 0x%x\n", id);
 708             return;
 709         }
 710         if (!REG_IS_32BIT(id)) {
 711             if (show_warnings)
 712                 warn("Ignoring VFP control register (%s) with "
 713                      "unexpected size.\n",
 714                      miscRegName[idx]);
 715             return;
 716         }
 717         setOneReg(id, (uint32_t)tc->readMiscReg(idx));
 718     } else {
 719         if (show_warnings)
 720             warn("Unhandled VFP register: 0x%x\n", id);
 721     }
 722 }
 723
 724 void
 725 ArmKvmCPU::updateTCStateCore()
 726 {
 727     for (const KvmIntRegInfo *ri(kvmIntRegs);
 728          ri->idx != NUM_INTREGS; ++ri) {
 729
 730         tc->setIntRegFlat(ri->idx, getOneRegU32(ri->id));
 731     }
 732
 733     for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
 734          ri->idx != NUM_MISCREGS; ++ri) {
 735
 736         tc->setMiscRegNoEffect(ri->idx, getOneRegU32(ri->id));
 737     }
 738
 739     /* We want the simulator to execute all side-effects of the CPSR
 740      * update since this updates PC state and register maps.
 741      */
 742     tc->setMiscReg(MISCREG_CPSR, tc->readMiscRegNoEffect(MISCREG_CPSR));
 743
 744     // We update the PC state after we have updated the CPSR the
 745     // contents of the CPSR affects how the npc is updated.
 746     PCState pc(tc->pcState());
 747     pc.set(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
 748     tc->pcState(pc);
 749
 750     if (DTRACE(KvmContext))
 751         dumpKvmStateCore();
 752 }
 753
 754 void
 755 ArmKvmCPU::updateTCStateMisc()
 756 {
 757     static bool warned(false); // We can't use warn_once since we want
 758                                // to show /all/ registers
 759
 760     const RegIndexVector &reg_ids(getRegList());;
 761     for (RegIndexVector::const_iterator it(reg_ids.begin());
 762          it != reg_ids.end(); ++it) {
 763
 764         if (!REG_IS_ARM(*it)) {
 765             if (!warned)
 766                 warn("Skipping non-ARM register: 0x%x\n", *it);
 767         } else if (REG_IS_CORE(*it)) {
 768             // Core registers are handled in updateKvmStateCore
 769         } else if (REG_CP(*it) <= 15) {
 770             updateTCStateCoProc(*it, !warned);
 771         } else if (REG_IS_VFP(*it)) {
 772             updateTCStateVFP(*it, !warned);
 773         } else {
 774             if (!warned) {
 775                 warn("Skipping register with unknown CP (%i) id: 0x%x\n",
 776                      REG_CP(*it), *it);
 777             }
 778         }
 779     }
 780
 781     warned = true;
 782
 783     if (DTRACE(KvmContext))
 784         dumpKvmStateMisc();
 785 }
 786
 787 void
 788 ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
 789 {
 790     MiscRegIndex reg(decodeCoProcReg(id));
 791
 792     assert(REG_IS_ARM(id));
 793     assert(REG_CP(id) <= 15);
 794
 795     if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
 796         // HACK HACK HACK: We don't currently support 64-bit TTBR0/TTBR1
 797         hack_once("KVM: 64-bit TTBRx workaround\n");
 798         tc->setMiscRegNoEffect(
 799             id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1,
 800             (uint32_t)(getOneRegU64(id) & 0xFFFFFFFF));
 801     } else if (reg == MISCREG_TTBCR) {
 802         uint32_t value(getOneRegU64(id));
 803         if (value & 0x80000000)
 804             panic("KVM: Guest tried to enable LPAE.\n");
 805         tc->setMiscRegNoEffect(reg, value);
 806     } else if (reg == NUM_MISCREGS) {
 807         if (show_warnings) {
 808             warn("KVM: Ignoring unknown KVM co-processor register:\n", id);
 809             warn("\t0x%x: [CP: %i 64: %i CRn: c%i opc1: %.2i CRm: c%i"
 810                  " opc2: %i]\n",
 811                  id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
 812                  REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
 813         }
 814     } else if (reg >= MISCREG_CP15_UNIMP_START && reg < MISCREG_CP15_END) {
 815         if (show_warnings)
 816             warn_once("KVM: Co-processor reg. %s not implemented by gem5.\n",
 817                       miscRegName[reg]);
 818     } else {
 819         tc->setMiscRegNoEffect(reg, getOneRegU32(id));
 820     }
 821 }
 822
 823 void
 824 ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings)
 825 {
 826     assert(REG_IS_ARM(id));
 827     assert(REG_IS_VFP(id));
 828
 829     if (REG_IS_VFP_REG(id)) {
 830         if (!REG_IS_64BIT(id)) {
 831             if (show_warnings)
 832                 warn("Unexpected VFP register length (reg: 0x%x).\n", id);
 833             return;
 834         }
 835         const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
 836         const unsigned idx_base(idx << 1);
 837         const unsigned idx_hi(idx_base + 1);
 838         const unsigned idx_lo(idx_base + 0);
 839         uint64_t value(getOneRegU64(id));
 840
 841         tc->setFloatRegBitsFlat(idx_hi, (value >> 32) & 0xFFFFFFFF);
 842         tc->setFloatRegBitsFlat(idx_lo, value & 0xFFFFFFFF);
 843     } else if (REG_IS_VFP_CTRL(id)) {
 844         MiscRegIndex idx(decodeVFPCtrlReg(id));
 845         if (idx == NUM_MISCREGS) {
 846             if (show_warnings)
 847                 warn("Unhandled VFP control register: 0x%x\n", id);
 848             return;
 849         }
 850         if (!REG_IS_32BIT(id)) {
 851             if (show_warnings)
 852                 warn("Ignoring VFP control register (%s) with "
 853                      "unexpected size.\n",
 854                      miscRegName[idx]);
 855             return;
 856         }
 857         tc->setMiscReg(idx, getOneRegU64(id));
 858     } else {
 859         if (show_warnings)
 860             warn("Unhandled VFP register: 0x%x\n", id);
 861     }
 862 }
 863
 864 ArmKvmCPU *
 865 ArmKvmCPUParams::create()
 866 {
 867     return new ArmKvmCPU(this);
 868 }