src/cpu/legiontrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include "arch/isa_specific.hh"
  35 #if THE_ISA != SPARC_ISA
  36     #error Legion tracing only works with SPARC simulations!
  37 #endif
  38
  39 #include "config/full_system.hh"
  40 #if !FULL_SYSTEM
  41     #error Legion tracing only works in full system!
  42 #endif
  43
  44 #include <iomanip>
  45 #include <sys/ipc.h>
  46 #include <sys/shm.h>
  47
  48 #include "arch/sparc/predecoder.hh"
  49 #include "arch/sparc/regfile.hh"
  50 #include "arch/sparc/utility.hh"
  51 #include "base/socket.hh"
  52 #include "cpu/base.hh"
  53 #include "cpu/legiontrace.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "params/LegionTrace.hh"
  57 #include "sim/system.hh"
  58
  59 #if FULL_SYSTEM
  60 #include "arch/tlb.hh"
  61 #endif
  62
  63 //XXX This is temporary
  64 #include "cpu/m5legion_interface.h"
  65
  66 using namespace std;
  67 using namespace TheISA;
  68
  69 #if FULL_SYSTEM
  70 static int diffcount = 0;
  71 static bool wasMicro = false;
  72 #endif
  73
  74 namespace Trace {
  75 SharedData *shared_data = NULL;
  76
  77 void
  78 setupSharedData()
  79 {
  80     int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
  81     if (shmfd < 0)
  82         fatal("Couldn't get shared memory fd. Is Legion running?");
  83
  84     shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
  85     if (shared_data == (SharedData*)-1)
  86         fatal("Couldn't allocate shared memory");
  87
  88     if (shared_data->flags != OWN_M5)
  89         fatal("Shared memory has invalid owner");
  90
  91     if (shared_data->version != VERSION)
  92         fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
  93               shared_data->version);
  94
  95     // step legion forward one cycle so we can get register values
  96     shared_data->flags = OWN_LEGION;
  97 }
  98
  99 ////////////////////////////////////////////////////////////////////////
 100 //
 101 //  Utility methods for pretty printing a report about a difference
 102 //
 103
 104 inline char * genCenteredLabel(int length, char * buffer, char * label)
 105 {
 106     int labelLength = strlen(label);
 107     assert(labelLength <= length);
 108     int leftPad = (length - labelLength) / 2;
 109     int rightPad = length - leftPad - labelLength;
 110     char format[64];
 111     sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
 112     sprintf(buffer, format, "", label, "");
 113     return buffer;
 114 }
 115
 116 inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
 117 {
 118     ccprintf(os, "  %16s  |  %#018x   %s   %#-018x  \n",
 119             title, a, (a == b) ? "|" : "X", b);
 120 }
 121
 122 inline void printColumnLabels(ostream & os)
 123 {
 124     static char * regLabel = genCenteredLabel(16, new char[17], "Register");
 125     static char * m5Label = genCenteredLabel(18, new char[18], "M5");
 126     static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
 127     ccprintf(os, "  %s  |  %s   |   %s  \n", regLabel, m5Label, legionLabel);
 128     ccprintf(os, "--------------------+-----------------------+-----------------------\n");
 129 }
 130
 131 inline void printSectionHeader(ostream & os, char * name)
 132 {
 133     char sectionString[70];
 134     genCenteredLabel(69, sectionString, name);
 135     ccprintf(os, "====================================================================\n");
 136     ccprintf(os, "%69s\n", sectionString);
 137     ccprintf(os, "====================================================================\n");
 138 }
 139
 140 inline void printLevelHeader(ostream & os, int level)
 141 {
 142     char sectionString[70];
 143     char levelName[70];
 144     sprintf(levelName, "Trap stack level %d", level);
 145     genCenteredLabel(69, sectionString, levelName);
 146     ccprintf(os, "====================================================================\n");
 147     ccprintf(os, "%69s\n", sectionString);
 148     ccprintf(os, "====================================================================\n");
 149 }
 150
 151 void
 152 Trace::LegionTraceRecord::dump()
 153 {
 154     ostream &outs = Trace::output();
 155
 156     static TheISA::Predecoder predecoder(NULL);
 157     // Compare
 158     bool compared = false;
 159     bool diffPC   = false;
 160     bool diffCC   = false;
 161     bool diffInst = false;
 162     bool diffIntRegs = false;
 163     bool diffFpRegs = false;
 164     bool diffTpc = false;
 165     bool diffTnpc = false;
 166     bool diffTstate = false;
 167     bool diffTt = false;
 168     bool diffTba = false;
 169     bool diffHpstate = false;
 170     bool diffHtstate = false;
 171     bool diffHtba = false;
 172     bool diffPstate = false;
 173     bool diffY = false;
 174     bool diffFsr = false;
 175     bool diffCcr = false;
 176     bool diffTl = false;
 177     bool diffGl = false;
 178     bool diffAsi = false;
 179     bool diffPil = false;
 180     bool diffCwp = false;
 181     bool diffCansave = false;
 182     bool diffCanrestore = false;
 183     bool diffOtherwin = false;
 184     bool diffCleanwin = false;
 185     bool diffTlb = false;
 186     Addr m5Pc, lgnPc;
 187
 188     if (!shared_data)
 189         setupSharedData();
 190
 191     // We took a trap on a micro-op...
 192     if (wasMicro && !staticInst->isMicroop())
 193     {
 194         // let's skip comparing this tick
 195         while (!compared)
 196             if (shared_data->flags == OWN_M5) {
 197                 shared_data->flags = OWN_LEGION;
 198                 compared = true;
 199             }
 200         compared = false;
 201         wasMicro = false;
 202     }
 203
 204     if (staticInst->isLastMicroop())
 205         wasMicro = false;
 206     else if (staticInst->isMicroop())
 207         wasMicro = true;
 208
 209
 210     if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
 211         while (!compared) {
 212             if (shared_data->flags == OWN_M5) {
 213                 m5Pc = PC & SparcISA::PAddrImplMask;
 214                 if (bits(shared_data->pstate,3,3)) {
 215                     m5Pc &= mask(32);
 216                 }
 217                 lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
 218                 if (lgnPc != m5Pc)
 219                    diffPC = true;
 220
 221                 if (shared_data->cycle_count !=
 222                         thread->getCpuPtr()->instCount())
 223                     diffCC = true;
 224
 225                 if (shared_data->instruction !=
 226                         (SparcISA::MachInst)staticInst->machInst) {
 227                     diffInst = true;
 228                 }
 229                 // assume we have %g0 working correctly
 230                 for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
 231                     if (thread->readIntReg(i) != shared_data->intregs[i]) {
 232                         diffIntRegs = true;
 233                     }
 234                 }
 235                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
 236                     if (thread->readFloatRegBits(i*2,
 237                                 FloatRegFile::DoubleWidth) !=
 238                             shared_data->fpregs[i]) {
 239                         diffFpRegs = true;
 240                     }
 241                 }
 242                         uint64_t oldTl =
 243                             thread->readMiscRegNoEffect(MISCREG_TL);
 244                 if (oldTl != shared_data->tl)
 245                     diffTl = true;
 246                 for (int i = 1; i <= MaxTL; i++) {
 247                     thread->setMiscRegNoEffect(MISCREG_TL, i);
 248                     if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
 249                             shared_data->tpc[i-1])
 250                         diffTpc = true;
 251                     if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
 252                             shared_data->tnpc[i-1])
 253                         diffTnpc = true;
 254                     if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
 255                             shared_data->tstate[i-1])
 256                         diffTstate = true;
 257                     if (thread->readMiscRegNoEffect(MISCREG_TT) !=
 258                             shared_data->tt[i-1])
 259                         diffTt = true;
 260                     if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
 261                             shared_data->htstate[i-1])
 262                         diffHtstate = true;
 263                 }
 264                 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 265
 266                 if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
 267                     diffTba = true;
 268                 //When the hpstate register is read by an instruction,
 269                 //legion has bit 11 set. When it's in storage, it doesn't.
 270                 //Since we don't directly support seperate interpretations
 271                 //of the registers like that, the bit is always set to 1 and
 272                 //we just don't compare it. It's not supposed to matter
 273                 //anyway.
 274                 if((shared_data->hpstate | (1 << 11)) !=
 275                         thread->readMiscRegNoEffect(MISCREG_HPSTATE))
 276                     diffHpstate = true;
 277                 if(shared_data->htba !=
 278                         thread->readMiscRegNoEffect(MISCREG_HTBA))
 279                     diffHtba = true;
 280                 if(shared_data->pstate !=
 281                         thread->readMiscRegNoEffect(MISCREG_PSTATE))
 282                     diffPstate = true;
 283                 //if(shared_data->y !=
 284                 //        thread->readMiscRegNoEffect(MISCREG_Y))
 285                 if(shared_data->y !=
 286                         thread->readIntReg(NumIntArchRegs + 1))
 287                     diffY = true;
 288                 if(shared_data->fsr !=
 289                         thread->readMiscRegNoEffect(MISCREG_FSR)) {
 290                     diffFsr = true;
 291                     if (mbits(shared_data->fsr, 63,10) ==
 292                             mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
 293                                 63,10)) {
 294                         thread->setMiscRegNoEffect(MISCREG_FSR,
 295                                 shared_data->fsr);
 296                         diffFsr = false;
 297                     }
 298                 }
 299                 //if(shared_data->ccr !=
 300                 //        thread->readMiscRegNoEffect(MISCREG_CCR))
 301                 if(shared_data->ccr !=
 302                         thread->readIntReg(NumIntArchRegs + 2))
 303                     diffCcr = true;
 304                 if(shared_data->gl !=
 305                         thread->readMiscRegNoEffect(MISCREG_GL))
 306                     diffGl = true;
 307                 if(shared_data->asi !=
 308                         thread->readMiscRegNoEffect(MISCREG_ASI))
 309                     diffAsi = true;
 310                 if(shared_data->pil !=
 311                         thread->readMiscRegNoEffect(MISCREG_PIL))
 312                     diffPil = true;
 313                 if(shared_data->cwp !=
 314                         thread->readMiscRegNoEffect(MISCREG_CWP))
 315                     diffCwp = true;
 316                 //if(shared_data->cansave !=
 317                 //        thread->readMiscRegNoEffect(MISCREG_CANSAVE))
 318                 if(shared_data->cansave !=
 319                         thread->readIntReg(NumIntArchRegs + 3))
 320                     diffCansave = true;
 321                 //if(shared_data->canrestore !=
 322                 //        thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
 323                 if(shared_data->canrestore !=
 324                         thread->readIntReg(NumIntArchRegs + 4))
 325                     diffCanrestore = true;
 326                 //if(shared_data->otherwin !=
 327                 //        thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
 328                 if(shared_data->otherwin !=
 329                         thread->readIntReg(NumIntArchRegs + 6))
 330                     diffOtherwin = true;
 331                 //if(shared_data->cleanwin !=
 332                 //        thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
 333                 if(shared_data->cleanwin !=
 334                         thread->readIntReg(NumIntArchRegs + 5))
 335                     diffCleanwin = true;
 336
 337                 for (int i = 0; i < 64; i++) {
 338                     if (shared_data->itb[i] !=
 339                             thread->getITBPtr()->TteRead(i))
 340                         diffTlb = true;
 341                     if (shared_data->dtb[i] !=
 342                             thread->getDTBPtr()->TteRead(i))
 343                         diffTlb = true;
 344                 }
 345
 346                 if (diffPC || diffCC || diffInst ||
 347                     diffIntRegs || diffFpRegs ||
 348                     diffTpc || diffTnpc || diffTstate || diffTt ||
 349                     diffHpstate || diffHtstate || diffHtba ||
 350                     diffPstate || diffY || diffCcr || diffTl || diffFsr ||
 351                     diffGl || diffAsi || diffPil || diffCwp ||
 352                     diffCansave || diffCanrestore ||
 353                     diffOtherwin || diffCleanwin || diffTlb) {
 354
 355                     outs << "Differences found between M5 and Legion:";
 356                     if (diffPC)
 357                         outs << " [PC]";
 358                     if (diffCC)
 359                         outs << " [CC]";
 360                     if (diffInst)
 361                         outs << " [Instruction]";
 362                     if (diffIntRegs)
 363                         outs << " [IntRegs]";
 364                     if (diffFpRegs)
 365                         outs << " [FpRegs]";
 366                     if (diffTpc)
 367                         outs << " [Tpc]";
 368                     if (diffTnpc)
 369                         outs << " [Tnpc]";
 370                     if (diffTstate)
 371                         outs << " [Tstate]";
 372                     if (diffTt)
 373                         outs << " [Tt]";
 374                     if (diffHpstate)
 375                         outs << " [Hpstate]";
 376                     if (diffHtstate)
 377                         outs << " [Htstate]";
 378                     if (diffHtba)
 379                         outs << " [Htba]";
 380                     if (diffPstate)
 381                         outs << " [Pstate]";
 382                     if (diffY)
 383                         outs << " [Y]";
 384                     if (diffFsr)
 385                         outs << " [FSR]";
 386                     if (diffCcr)
 387                         outs << " [Ccr]";
 388                     if (diffTl)
 389                         outs << " [Tl]";
 390                     if (diffGl)
 391                         outs << " [Gl]";
 392                     if (diffAsi)
 393                         outs << " [Asi]";
 394                     if (diffPil)
 395                         outs << " [Pil]";
 396                     if (diffCwp)
 397                         outs << " [Cwp]";
 398                     if (diffCansave)
 399                         outs << " [Cansave]";
 400                     if (diffCanrestore)
 401                         outs << " [Canrestore]";
 402                     if (diffOtherwin)
 403                         outs << " [Otherwin]";
 404                     if (diffCleanwin)
 405                         outs << " [Cleanwin]";
 406                     if (diffTlb)
 407                         outs << " [Tlb]";
 408                     outs << endl << endl;
 409
 410                     outs << right << setfill(' ') << setw(15)
 411                          << "M5 PC: " << "0x"<< setw(16) << setfill('0')
 412                          << hex << m5Pc << endl;
 413                     outs << setfill(' ') << setw(15)
 414                          << "Legion PC: " << "0x"
 415                          << setw(16) << setfill('0') << hex
 416                          << lgnPc << endl << endl;
 417
 418                     outs << right << setfill(' ') << setw(15)
 419                          << "M5 CC: " << "0x"
 420                          << setw(16) << setfill('0') << hex
 421                          << thread->getCpuPtr()->instCount() << endl;
 422                     outs << setfill(' ') << setw(15)
 423                          << "Legion CC: " << "0x"
 424                          << setw(16) << setfill('0') << hex
 425                          << shared_data->cycle_count << endl << endl;
 426
 427                     outs << setfill(' ') << setw(15)
 428                          << "M5 Inst: " << "0x"
 429                          << setw(8) << setfill('0') << hex
 430                          << staticInst->machInst
 431                          << staticInst->disassemble(m5Pc, debugSymbolTable)
 432                          << endl;
 433
 434                     predecoder.setTC(thread);
 435                     predecoder.moreBytes(m5Pc, m5Pc,
 436                             shared_data->instruction);
 437
 438                     assert(predecoder.extMachInstReady());
 439
 440                     StaticInstPtr legionInst =
 441                         StaticInst::decode(predecoder.getExtMachInst(), lgnPc);
 442                     outs << setfill(' ') << setw(15)
 443                          << " Legion Inst: "
 444                          << "0x" << setw(8) << setfill('0') << hex
 445                          << shared_data->instruction
 446                          << legionInst->disassemble(lgnPc, debugSymbolTable)
 447                          << endl << endl;
 448
 449                     printSectionHeader(outs, "General State");
 450                     printColumnLabels(outs);
 451                     printRegPair(outs, "HPstate",
 452                             thread->readMiscRegNoEffect(MISCREG_HPSTATE),
 453                             shared_data->hpstate | (1 << 11));
 454                     printRegPair(outs, "Htba",
 455                             thread->readMiscRegNoEffect(MISCREG_HTBA),
 456                             shared_data->htba);
 457                     printRegPair(outs, "Pstate",
 458                             thread->readMiscRegNoEffect(MISCREG_PSTATE),
 459                             shared_data->pstate);
 460                     printRegPair(outs, "Y",
 461                             //thread->readMiscRegNoEffect(MISCREG_Y),
 462                             thread->readIntReg(NumIntArchRegs + 1),
 463                             shared_data->y);
 464                     printRegPair(outs, "FSR",
 465                             thread->readMiscRegNoEffect(MISCREG_FSR),
 466                             shared_data->fsr);
 467                     printRegPair(outs, "Ccr",
 468                             //thread->readMiscRegNoEffect(MISCREG_CCR),
 469                             thread->readIntReg(NumIntArchRegs + 2),
 470                             shared_data->ccr);
 471                     printRegPair(outs, "Tl",
 472                             thread->readMiscRegNoEffect(MISCREG_TL),
 473                             shared_data->tl);
 474                     printRegPair(outs, "Gl",
 475                             thread->readMiscRegNoEffect(MISCREG_GL),
 476                             shared_data->gl);
 477                     printRegPair(outs, "Asi",
 478                             thread->readMiscRegNoEffect(MISCREG_ASI),
 479                             shared_data->asi);
 480                     printRegPair(outs, "Pil",
 481                             thread->readMiscRegNoEffect(MISCREG_PIL),
 482                             shared_data->pil);
 483                     printRegPair(outs, "Cwp",
 484                             thread->readMiscRegNoEffect(MISCREG_CWP),
 485                             shared_data->cwp);
 486                     printRegPair(outs, "Cansave",
 487                             //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
 488                             thread->readIntReg(NumIntArchRegs + 3),
 489                             shared_data->cansave);
 490                     printRegPair(outs, "Canrestore",
 491                             //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
 492                             thread->readIntReg(NumIntArchRegs + 4),
 493                             shared_data->canrestore);
 494                     printRegPair(outs, "Otherwin",
 495                             //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
 496                             thread->readIntReg(NumIntArchRegs + 6),
 497                             shared_data->otherwin);
 498                     printRegPair(outs, "Cleanwin",
 499                             //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
 500                             thread->readIntReg(NumIntArchRegs + 5),
 501                             shared_data->cleanwin);
 502                     outs << endl;
 503                     for (int i = 1; i <= MaxTL; i++) {
 504                         printLevelHeader(outs, i);
 505                         printColumnLabels(outs);
 506                         thread->setMiscRegNoEffect(MISCREG_TL, i);
 507                         printRegPair(outs, "Tpc",
 508                                 thread->readMiscRegNoEffect(MISCREG_TPC),
 509                                 shared_data->tpc[i-1]);
 510                         printRegPair(outs, "Tnpc",
 511                                 thread->readMiscRegNoEffect(MISCREG_TNPC),
 512                                 shared_data->tnpc[i-1]);
 513                         printRegPair(outs, "Tstate",
 514                                 thread->readMiscRegNoEffect(MISCREG_TSTATE),
 515                                 shared_data->tstate[i-1]);
 516                         printRegPair(outs, "Tt",
 517                                 thread->readMiscRegNoEffect(MISCREG_TT),
 518                                 shared_data->tt[i-1]);
 519                         printRegPair(outs, "Htstate",
 520                                 thread->readMiscRegNoEffect(MISCREG_HTSTATE),
 521                                 shared_data->htstate[i-1]);
 522                     }
 523                     thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 524                     outs << endl;
 525
 526                     printSectionHeader(outs, "General Purpose Registers");
 527                     static const char * regtypes[4] =
 528                         {"%g", "%o", "%l", "%i"};
 529                     for(int y = 0; y < 4; y++) {
 530                         for(int x = 0; x < 8; x++) {
 531                             char label[8];
 532                             sprintf(label, "%s%d", regtypes[y], x);
 533                             printRegPair(outs, label,
 534                                     thread->readIntReg(y*8+x),
 535                                     shared_data->intregs[y*8+x]);
 536                         }
 537                     }
 538                     if (diffFpRegs) {
 539                         for (int x = 0; x < 32; x++) {
 540                             char label[8];
 541                             sprintf(label, "%%f%d", x);
 542                             printRegPair(outs, label,
 543                                 thread->readFloatRegBits(x*2,
 544                                     FloatRegFile::DoubleWidth),
 545                                 shared_data->fpregs[x]);
 546                         }
 547                     }
 548                     if (diffTlb) {
 549                         printColumnLabels(outs);
 550                         char label[8];
 551                         for (int x = 0; x < 64; x++) {
 552                             if (shared_data->itb[x] !=
 553                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 554                                 thread->getITBPtr()->TteRead(x) !=
 555                                 ULL(0xFFFFFFFFFFFFFFFF)) {
 556                                     sprintf(label, "I-TLB:%02d", x);
 557                                     printRegPair(outs, label,
 558                                             thread->getITBPtr()->TteRead(x),
 559                                             shared_data->itb[x]);
 560                             }
 561                         }
 562                         for (int x = 0; x < 64; x++) {
 563                             if (shared_data->dtb[x] !=
 564                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 565                                 thread->getDTBPtr()->TteRead(x) !=
 566                                 ULL(0xFFFFFFFFFFFFFFFF))  {
 567                                     sprintf(label, "D-TLB:%02d", x);
 568                                     printRegPair(outs, label,
 569                                             thread->getDTBPtr()->TteRead(x),
 570                                             shared_data->dtb[x]);
 571                             }
 572                         }
 573                         thread->getITBPtr()->dumpAll();
 574                         thread->getDTBPtr()->dumpAll();
 575                     }
 576
 577                     diffcount++;
 578                     if (diffcount > 3)
 579                         fatal("Differences found between Legion and M5\n");
 580                 } else
 581                     diffcount = 0;
 582
 583                 compared = true;
 584                 shared_data->flags = OWN_LEGION;
 585             }
 586         } // while
 587     } // if not microop
 588 }
 589
 590 /* namespace Trace */ }
 591
 592 ////////////////////////////////////////////////////////////////////////
 593 //
 594 //  ExeTracer Simulation Object
 595 //
 596 Trace::LegionTrace *
 597 LegionTraceParams::create()
 598 {
 599     return new Trace::LegionTrace(name);
 600 };