2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
34 #include "arch/isa_specific.hh"
35 #if THE_ISA != SPARC_ISA
36 #error Legion tracing only works with SPARC simulations!
39 #include "config/full_system.hh"
41 #error Legion tracing only works in full system!
48 #include "arch/sparc/predecoder.hh"
49 #include "arch/sparc/registers.hh"
50 #include "arch/sparc/utility.hh"
51 #include "base/socket.hh"
52 #include "cpu/base.hh"
53 #include "cpu/legiontrace.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
56 #include "sim/system.hh"
59 #include "arch/tlb.hh"
62 //XXX This is temporary
63 #include "cpu/m5legion_interface.h"
66 using namespace TheISA
;
69 static int diffcount
= 0;
70 static bool wasMicro
= false;
74 SharedData
*shared_data
= NULL
;
79 int shmfd
= shmget('M' << 24 | getuid(), sizeof(SharedData
), 0777);
81 fatal("Couldn't get shared memory fd. Is Legion running?");
83 shared_data
= (SharedData
*)shmat(shmfd
, NULL
, SHM_RND
);
84 if (shared_data
== (SharedData
*)-1)
85 fatal("Couldn't allocate shared memory");
87 if (shared_data
->flags
!= OWN_M5
)
88 fatal("Shared memory has invalid owner");
90 if (shared_data
->version
!= VERSION
)
91 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION
,
92 shared_data
->version
);
94 // step legion forward one cycle so we can get register values
95 shared_data
->flags
= OWN_LEGION
;
98 ////////////////////////////////////////////////////////////////////////
100 // Utility methods for pretty printing a report about a difference
103 inline char * genCenteredLabel(int length
, char * buffer
, const char * label
)
105 int labelLength
= strlen(label
);
106 assert(labelLength
<= length
);
107 int leftPad
= (length
- labelLength
) / 2;
108 int rightPad
= length
- leftPad
- labelLength
;
110 sprintf(format
, "%%%ds%%s%%%ds", leftPad
, rightPad
);
111 sprintf(buffer
, format
, "", label
, "");
115 inline void printRegPair(ostream
& os
, char const * title
, uint64_t a
, uint64_t b
)
117 ccprintf(os
, " %16s | %#018x %s %#-018x \n",
118 title
, a
, (a
== b
) ? "|" : "X", b
);
121 inline void printColumnLabels(ostream
& os
)
123 static char * regLabel
= genCenteredLabel(16, new char[17], "Register");
124 static char * m5Label
= genCenteredLabel(18, new char[18], "M5");
125 static char * legionLabel
= genCenteredLabel(18, new char[18], "Legion");
126 ccprintf(os
, " %s | %s | %s \n", regLabel
, m5Label
, legionLabel
);
127 ccprintf(os
, "--------------------+-----------------------+-----------------------\n");
130 inline void printSectionHeader(ostream
& os
, const char * name
)
132 char sectionString
[70];
133 genCenteredLabel(69, sectionString
, name
);
134 ccprintf(os
, "====================================================================\n");
135 ccprintf(os
, "%69s\n", sectionString
);
136 ccprintf(os
, "====================================================================\n");
139 inline void printLevelHeader(ostream
& os
, int level
)
141 char sectionString
[70];
143 sprintf(levelName
, "Trap stack level %d", level
);
144 genCenteredLabel(69, sectionString
, levelName
);
145 ccprintf(os
, "====================================================================\n");
146 ccprintf(os
, "%69s\n", sectionString
);
147 ccprintf(os
, "====================================================================\n");
151 Trace::LegionTraceRecord::dump()
153 ostream
&outs
= Trace::output();
155 static TheISA::Predecoder
predecoder(NULL
);
157 bool compared
= false;
160 bool diffInst
= false;
161 bool diffIntRegs
= false;
162 bool diffFpRegs
= false;
163 bool diffTpc
= false;
164 bool diffTnpc
= false;
165 bool diffTstate
= false;
167 bool diffTba
= false;
168 bool diffHpstate
= false;
169 bool diffHtstate
= false;
170 bool diffHtba
= false;
171 bool diffPstate
= false;
173 bool diffFsr
= false;
174 bool diffCcr
= false;
177 bool diffAsi
= false;
178 bool diffPil
= false;
179 bool diffCwp
= false;
180 bool diffCansave
= false;
181 bool diffCanrestore
= false;
182 bool diffOtherwin
= false;
183 bool diffCleanwin
= false;
184 bool diffTlb
= false;
190 // We took a trap on a micro-op...
191 if (wasMicro
&& !staticInst
->isMicroop())
193 // let's skip comparing this tick
195 if (shared_data
->flags
== OWN_M5
) {
196 shared_data
->flags
= OWN_LEGION
;
203 if (staticInst
->isLastMicroop())
205 else if (staticInst
->isMicroop())
209 if(!staticInst
->isMicroop() || staticInst
->isLastMicroop()) {
211 if (shared_data
->flags
== OWN_M5
) {
212 m5Pc
= PC
& SparcISA::PAddrImplMask
;
213 if (bits(shared_data
->pstate
,3,3)) {
216 lgnPc
= shared_data
->pc
& SparcISA::PAddrImplMask
;
220 if (shared_data
->cycle_count
!=
221 thread
->getCpuPtr()->instCount())
224 if (shared_data
->instruction
!=
225 (SparcISA::MachInst
)staticInst
->machInst
) {
228 // assume we have %g0 working correctly
229 for (int i
= 1; i
< TheISA::NumIntArchRegs
; i
++) {
230 if (thread
->readIntReg(i
) != shared_data
->intregs
[i
]) {
234 for (int i
= 0; i
< TheISA::NumFloatRegs
/2; i
++) {
235 if (thread
->readFloatRegBits(i
*2) !=
236 shared_data
->fpregs
[i
]) {
241 thread
->readMiscRegNoEffect(MISCREG_TL
);
242 if (oldTl
!= shared_data
->tl
)
244 for (int i
= 1; i
<= MaxTL
; i
++) {
245 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
246 if (thread
->readMiscRegNoEffect(MISCREG_TPC
) !=
247 shared_data
->tpc
[i
-1])
249 if (thread
->readMiscRegNoEffect(MISCREG_TNPC
) !=
250 shared_data
->tnpc
[i
-1])
252 if (thread
->readMiscRegNoEffect(MISCREG_TSTATE
) !=
253 shared_data
->tstate
[i
-1])
255 if (thread
->readMiscRegNoEffect(MISCREG_TT
) !=
256 shared_data
->tt
[i
-1])
258 if (thread
->readMiscRegNoEffect(MISCREG_HTSTATE
) !=
259 shared_data
->htstate
[i
-1])
262 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
264 if(shared_data
->tba
!= thread
->readMiscRegNoEffect(MISCREG_TBA
))
266 //When the hpstate register is read by an instruction,
267 //legion has bit 11 set. When it's in storage, it doesn't.
268 //Since we don't directly support seperate interpretations
269 //of the registers like that, the bit is always set to 1 and
270 //we just don't compare it. It's not supposed to matter
272 if((shared_data
->hpstate
| (1 << 11)) !=
273 thread
->readMiscRegNoEffect(MISCREG_HPSTATE
))
275 if(shared_data
->htba
!=
276 thread
->readMiscRegNoEffect(MISCREG_HTBA
))
278 if(shared_data
->pstate
!=
279 thread
->readMiscRegNoEffect(MISCREG_PSTATE
))
281 //if(shared_data->y !=
282 // thread->readMiscRegNoEffect(MISCREG_Y))
284 thread
->readIntReg(NumIntArchRegs
+ 1))
286 if(shared_data
->fsr
!=
287 thread
->readMiscRegNoEffect(MISCREG_FSR
)) {
289 if (mbits(shared_data
->fsr
, 63,10) ==
290 mbits(thread
->readMiscRegNoEffect(MISCREG_FSR
),
292 thread
->setMiscRegNoEffect(MISCREG_FSR
,
297 //if(shared_data->ccr !=
298 // thread->readMiscRegNoEffect(MISCREG_CCR))
299 if(shared_data
->ccr
!=
300 thread
->readIntReg(NumIntArchRegs
+ 2))
302 if(shared_data
->gl
!=
303 thread
->readMiscRegNoEffect(MISCREG_GL
))
305 if(shared_data
->asi
!=
306 thread
->readMiscRegNoEffect(MISCREG_ASI
))
308 if(shared_data
->pil
!=
309 thread
->readMiscRegNoEffect(MISCREG_PIL
))
311 if(shared_data
->cwp
!=
312 thread
->readMiscRegNoEffect(MISCREG_CWP
))
314 //if(shared_data->cansave !=
315 // thread->readMiscRegNoEffect(MISCREG_CANSAVE))
316 if(shared_data
->cansave
!=
317 thread
->readIntReg(NumIntArchRegs
+ 3))
319 //if(shared_data->canrestore !=
320 // thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
321 if(shared_data
->canrestore
!=
322 thread
->readIntReg(NumIntArchRegs
+ 4))
323 diffCanrestore
= true;
324 //if(shared_data->otherwin !=
325 // thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
326 if(shared_data
->otherwin
!=
327 thread
->readIntReg(NumIntArchRegs
+ 6))
329 //if(shared_data->cleanwin !=
330 // thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
331 if(shared_data
->cleanwin
!=
332 thread
->readIntReg(NumIntArchRegs
+ 5))
335 for (int i
= 0; i
< 64; i
++) {
336 if (shared_data
->itb
[i
] !=
337 thread
->getITBPtr()->TteRead(i
))
339 if (shared_data
->dtb
[i
] !=
340 thread
->getDTBPtr()->TteRead(i
))
344 if (diffPC
|| diffCC
|| diffInst
||
345 diffIntRegs
|| diffFpRegs
||
346 diffTpc
|| diffTnpc
|| diffTstate
|| diffTt
||
347 diffHpstate
|| diffHtstate
|| diffHtba
||
348 diffPstate
|| diffY
|| diffCcr
|| diffTl
|| diffFsr
||
349 diffGl
|| diffAsi
|| diffPil
|| diffCwp
||
350 diffCansave
|| diffCanrestore
||
351 diffOtherwin
|| diffCleanwin
|| diffTlb
) {
353 outs
<< "Differences found between M5 and Legion:";
359 outs
<< " [Instruction]";
361 outs
<< " [IntRegs]";
373 outs
<< " [Hpstate]";
375 outs
<< " [Htstate]";
397 outs
<< " [Cansave]";
399 outs
<< " [Canrestore]";
401 outs
<< " [Otherwin]";
403 outs
<< " [Cleanwin]";
406 outs
<< endl
<< endl
;
408 outs
<< right
<< setfill(' ') << setw(15)
409 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
410 << hex
<< m5Pc
<< endl
;
411 outs
<< setfill(' ') << setw(15)
412 << "Legion PC: " << "0x"
413 << setw(16) << setfill('0') << hex
414 << lgnPc
<< endl
<< endl
;
416 outs
<< right
<< setfill(' ') << setw(15)
418 << setw(16) << setfill('0') << hex
419 << thread
->getCpuPtr()->instCount() << endl
;
420 outs
<< setfill(' ') << setw(15)
421 << "Legion CC: " << "0x"
422 << setw(16) << setfill('0') << hex
423 << shared_data
->cycle_count
<< endl
<< endl
;
425 outs
<< setfill(' ') << setw(15)
426 << "M5 Inst: " << "0x"
427 << setw(8) << setfill('0') << hex
428 << staticInst
->machInst
429 << staticInst
->disassemble(m5Pc
, debugSymbolTable
)
432 predecoder
.setTC(thread
);
433 predecoder
.moreBytes(m5Pc
, m5Pc
,
434 shared_data
->instruction
);
436 assert(predecoder
.extMachInstReady());
438 StaticInstPtr legionInst
=
439 StaticInst::decode(predecoder
.getExtMachInst(), lgnPc
);
440 outs
<< setfill(' ') << setw(15)
442 << "0x" << setw(8) << setfill('0') << hex
443 << shared_data
->instruction
444 << legionInst
->disassemble(lgnPc
, debugSymbolTable
)
447 printSectionHeader(outs
, "General State");
448 printColumnLabels(outs
);
449 printRegPair(outs
, "HPstate",
450 thread
->readMiscRegNoEffect(MISCREG_HPSTATE
),
451 shared_data
->hpstate
| (1 << 11));
452 printRegPair(outs
, "Htba",
453 thread
->readMiscRegNoEffect(MISCREG_HTBA
),
455 printRegPair(outs
, "Pstate",
456 thread
->readMiscRegNoEffect(MISCREG_PSTATE
),
457 shared_data
->pstate
);
458 printRegPair(outs
, "Y",
459 //thread->readMiscRegNoEffect(MISCREG_Y),
460 thread
->readIntReg(NumIntArchRegs
+ 1),
462 printRegPair(outs
, "FSR",
463 thread
->readMiscRegNoEffect(MISCREG_FSR
),
465 printRegPair(outs
, "Ccr",
466 //thread->readMiscRegNoEffect(MISCREG_CCR),
467 thread
->readIntReg(NumIntArchRegs
+ 2),
469 printRegPair(outs
, "Tl",
470 thread
->readMiscRegNoEffect(MISCREG_TL
),
472 printRegPair(outs
, "Gl",
473 thread
->readMiscRegNoEffect(MISCREG_GL
),
475 printRegPair(outs
, "Asi",
476 thread
->readMiscRegNoEffect(MISCREG_ASI
),
478 printRegPair(outs
, "Pil",
479 thread
->readMiscRegNoEffect(MISCREG_PIL
),
481 printRegPair(outs
, "Cwp",
482 thread
->readMiscRegNoEffect(MISCREG_CWP
),
484 printRegPair(outs
, "Cansave",
485 //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
486 thread
->readIntReg(NumIntArchRegs
+ 3),
487 shared_data
->cansave
);
488 printRegPair(outs
, "Canrestore",
489 //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
490 thread
->readIntReg(NumIntArchRegs
+ 4),
491 shared_data
->canrestore
);
492 printRegPair(outs
, "Otherwin",
493 //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
494 thread
->readIntReg(NumIntArchRegs
+ 6),
495 shared_data
->otherwin
);
496 printRegPair(outs
, "Cleanwin",
497 //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
498 thread
->readIntReg(NumIntArchRegs
+ 5),
499 shared_data
->cleanwin
);
501 for (int i
= 1; i
<= MaxTL
; i
++) {
502 printLevelHeader(outs
, i
);
503 printColumnLabels(outs
);
504 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
505 printRegPair(outs
, "Tpc",
506 thread
->readMiscRegNoEffect(MISCREG_TPC
),
507 shared_data
->tpc
[i
-1]);
508 printRegPair(outs
, "Tnpc",
509 thread
->readMiscRegNoEffect(MISCREG_TNPC
),
510 shared_data
->tnpc
[i
-1]);
511 printRegPair(outs
, "Tstate",
512 thread
->readMiscRegNoEffect(MISCREG_TSTATE
),
513 shared_data
->tstate
[i
-1]);
514 printRegPair(outs
, "Tt",
515 thread
->readMiscRegNoEffect(MISCREG_TT
),
516 shared_data
->tt
[i
-1]);
517 printRegPair(outs
, "Htstate",
518 thread
->readMiscRegNoEffect(MISCREG_HTSTATE
),
519 shared_data
->htstate
[i
-1]);
521 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
524 printSectionHeader(outs
, "General Purpose Registers");
525 static const char * regtypes
[4] =
526 {"%g", "%o", "%l", "%i"};
527 for(int y
= 0; y
< 4; y
++) {
528 for(int x
= 0; x
< 8; x
++) {
530 sprintf(label
, "%s%d", regtypes
[y
], x
);
531 printRegPair(outs
, label
,
532 thread
->readIntReg(y
*8+x
),
533 shared_data
->intregs
[y
*8+x
]);
537 for (int x
= 0; x
< 32; x
++) {
539 sprintf(label
, "%%f%d", x
);
540 printRegPair(outs
, label
,
541 thread
->readFloatRegBits(x
*2),
542 shared_data
->fpregs
[x
]);
546 printColumnLabels(outs
);
548 for (int x
= 0; x
< 64; x
++) {
549 if (shared_data
->itb
[x
] !=
550 ULL(0xFFFFFFFFFFFFFFFF) ||
551 thread
->getITBPtr()->TteRead(x
) !=
552 ULL(0xFFFFFFFFFFFFFFFF)) {
553 sprintf(label
, "I-TLB:%02d", x
);
554 printRegPair(outs
, label
,
555 thread
->getITBPtr()->TteRead(x
),
556 shared_data
->itb
[x
]);
559 for (int x
= 0; x
< 64; x
++) {
560 if (shared_data
->dtb
[x
] !=
561 ULL(0xFFFFFFFFFFFFFFFF) ||
562 thread
->getDTBPtr()->TteRead(x
) !=
563 ULL(0xFFFFFFFFFFFFFFFF)) {
564 sprintf(label
, "D-TLB:%02d", x
);
565 printRegPair(outs
, label
,
566 thread
->getDTBPtr()->TteRead(x
),
567 shared_data
->dtb
[x
]);
570 thread
->getITBPtr()->dumpAll();
571 thread
->getDTBPtr()->dumpAll();
576 fatal("Differences found between Legion and M5\n");
581 shared_data
->flags
= OWN_LEGION
;
587 /* namespace Trace */ }
589 ////////////////////////////////////////////////////////////////////////
591 // ExeTracer Simulation Object
594 LegionTraceParams::create()
596 return new Trace::LegionTrace(this);