2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
34 #include "config/the_isa.hh"
35 #if THE_ISA != SPARC_ISA
36 #error Legion tracing only works with SPARC simulations!
45 #include "arch/sparc/decoder.hh"
46 #include "arch/sparc/registers.hh"
47 #include "arch/sparc/utility.hh"
48 #include "arch/tlb.hh"
49 #include "base/socket.hh"
50 #include "cpu/base.hh"
51 #include "cpu/legiontrace.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 #include "sim/full_system.hh"
55 #include "sim/system.hh"
57 //XXX This is temporary
58 #include "cpu/m5legion_interface.h"
61 using namespace TheISA
;
63 static int diffcount
= 0;
64 static bool wasMicro
= false;
67 SharedData
*shared_data
= NULL
;
72 int shmfd
= shmget('M' << 24 | getuid(), sizeof(SharedData
), 0777);
74 fatal("Couldn't get shared memory fd. Is Legion running?");
76 shared_data
= (SharedData
*)shmat(shmfd
, NULL
, SHM_RND
);
77 if (shared_data
== (SharedData
*)-1)
78 fatal("Couldn't allocate shared memory");
80 if (shared_data
->flags
!= OWN_M5
)
81 fatal("Shared memory has invalid owner");
83 if (shared_data
->version
!= VERSION
)
84 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION
,
85 shared_data
->version
);
87 // step legion forward one cycle so we can get register values
88 shared_data
->flags
= OWN_LEGION
;
91 ////////////////////////////////////////////////////////////////////////
93 // Utility methods for pretty printing a report about a difference
96 inline char * genCenteredLabel(int length
, char * buffer
, const char * label
)
98 int labelLength
= strlen(label
);
99 assert(labelLength
<= length
);
100 int leftPad
= (length
- labelLength
) / 2;
101 int rightPad
= length
- leftPad
- labelLength
;
103 sprintf(format
, "%%%ds%%s%%%ds", leftPad
, rightPad
);
104 sprintf(buffer
, format
, "", label
, "");
108 inline void printRegPair(ostream
& os
, char const * title
, uint64_t a
, uint64_t b
)
110 ccprintf(os
, " %16s | %#018x %s %#-018x \n",
111 title
, a
, (a
== b
) ? "|" : "X", b
);
114 inline void printColumnLabels(ostream
& os
)
116 static char * regLabel
= genCenteredLabel(16, new char[17], "Register");
117 static char * m5Label
= genCenteredLabel(18, new char[18], "M5");
118 static char * legionLabel
= genCenteredLabel(18, new char[18], "Legion");
119 ccprintf(os
, " %s | %s | %s \n", regLabel
, m5Label
, legionLabel
);
120 ccprintf(os
, "--------------------+-----------------------+-----------------------\n");
123 inline void printSectionHeader(ostream
& os
, const char * name
)
125 char sectionString
[70];
126 genCenteredLabel(69, sectionString
, name
);
127 ccprintf(os
, "====================================================================\n");
128 ccprintf(os
, "%69s\n", sectionString
);
129 ccprintf(os
, "====================================================================\n");
132 inline void printLevelHeader(ostream
& os
, int level
)
134 char sectionString
[70];
136 sprintf(levelName
, "Trap stack level %d", level
);
137 genCenteredLabel(69, sectionString
, levelName
);
138 ccprintf(os
, "====================================================================\n");
139 ccprintf(os
, "%69s\n", sectionString
);
140 ccprintf(os
, "====================================================================\n");
144 Trace::LegionTraceRecord::dump()
146 ostream
&outs
= Trace::output();
149 bool compared
= false;
152 bool diffInst
= false;
153 bool diffIntRegs
= false;
154 bool diffFpRegs
= false;
155 bool diffTpc
= false;
156 bool diffTnpc
= false;
157 bool diffTstate
= false;
159 bool diffTba M5_VAR_USED
= false;
160 bool diffHpstate
= false;
161 bool diffHtstate
= false;
162 bool diffHtba
= false;
163 bool diffPstate
= false;
165 bool diffFsr
= false;
166 bool diffCcr
= false;
169 bool diffAsi
= false;
170 bool diffPil
= false;
171 bool diffCwp
= false;
172 bool diffCansave
= false;
173 bool diffCanrestore
= false;
174 bool diffOtherwin
= false;
175 bool diffCleanwin
= false;
176 bool diffTlb
= false;
182 // We took a trap on a micro-op...
183 if (wasMicro
&& !staticInst
->isMicroop())
185 // let's skip comparing this tick
187 if (shared_data
->flags
== OWN_M5
) {
188 shared_data
->flags
= OWN_LEGION
;
195 if (staticInst
->isLastMicroop())
197 else if (staticInst
->isMicroop())
201 if(!staticInst
->isMicroop() || staticInst
->isLastMicroop()) {
203 if (shared_data
->flags
== OWN_M5
) {
204 m5Pc
= pc
.instAddr() & SparcISA::PAddrImplMask
;
205 if (bits(shared_data
->pstate
,3,3)) {
208 lgnPc
= shared_data
->pc
& SparcISA::PAddrImplMask
;
212 if (shared_data
->cycle_count
!=
213 thread
->getCpuPtr()->instCount())
216 if (shared_data
->instruction
!=
217 (SparcISA::MachInst
)staticInst
->machInst
) {
220 // assume we have %g0 working correctly
221 for (int i
= 1; i
< TheISA::NumIntArchRegs
; i
++) {
222 if (thread
->readIntReg(i
) != shared_data
->intregs
[i
]) {
226 for (int i
= 0; i
< TheISA::NumFloatRegs
/2; i
++) {
227 if (thread
->readFloatRegBits(i
*2) !=
228 shared_data
->fpregs
[i
]) {
233 thread
->readMiscRegNoEffect(MISCREG_TL
);
234 if (oldTl
!= shared_data
->tl
)
236 for (int i
= 1; i
<= MaxTL
; i
++) {
237 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
238 if (thread
->readMiscRegNoEffect(MISCREG_TPC
) !=
239 shared_data
->tpc
[i
-1])
241 if (thread
->readMiscRegNoEffect(MISCREG_TNPC
) !=
242 shared_data
->tnpc
[i
-1])
244 if (thread
->readMiscRegNoEffect(MISCREG_TSTATE
) !=
245 shared_data
->tstate
[i
-1])
247 if (thread
->readMiscRegNoEffect(MISCREG_TT
) !=
248 shared_data
->tt
[i
-1])
250 if (thread
->readMiscRegNoEffect(MISCREG_HTSTATE
) !=
251 shared_data
->htstate
[i
-1])
254 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
256 if(shared_data
->tba
!= thread
->readMiscRegNoEffect(MISCREG_TBA
))
258 //When the hpstate register is read by an instruction,
259 //legion has bit 11 set. When it's in storage, it doesn't.
260 //Since we don't directly support seperate interpretations
261 //of the registers like that, the bit is always set to 1 and
262 //we just don't compare it. It's not supposed to matter
264 if((shared_data
->hpstate
| (1 << 11)) !=
265 thread
->readMiscRegNoEffect(MISCREG_HPSTATE
))
267 if(shared_data
->htba
!=
268 thread
->readMiscRegNoEffect(MISCREG_HTBA
))
270 if(shared_data
->pstate
!=
271 thread
->readMiscRegNoEffect(MISCREG_PSTATE
))
273 //if(shared_data->y !=
274 // thread->readMiscRegNoEffect(MISCREG_Y))
276 thread
->readIntReg(NumIntArchRegs
+ 1))
278 if(shared_data
->fsr
!=
279 thread
->readMiscRegNoEffect(MISCREG_FSR
)) {
281 if (mbits(shared_data
->fsr
, 63,10) ==
282 mbits(thread
->readMiscRegNoEffect(MISCREG_FSR
),
284 thread
->setMiscRegNoEffect(MISCREG_FSR
,
289 //if(shared_data->ccr !=
290 // thread->readMiscRegNoEffect(MISCREG_CCR))
291 if(shared_data
->ccr
!=
292 thread
->readIntReg(NumIntArchRegs
+ 2))
294 if(shared_data
->gl
!=
295 thread
->readMiscRegNoEffect(MISCREG_GL
))
297 if(shared_data
->asi
!=
298 thread
->readMiscRegNoEffect(MISCREG_ASI
))
300 if(shared_data
->pil
!=
301 thread
->readMiscRegNoEffect(MISCREG_PIL
))
303 if(shared_data
->cwp
!=
304 thread
->readMiscRegNoEffect(MISCREG_CWP
))
306 //if(shared_data->cansave !=
307 // thread->readMiscRegNoEffect(MISCREG_CANSAVE))
308 if(shared_data
->cansave
!=
309 thread
->readIntReg(NumIntArchRegs
+ 3))
311 //if(shared_data->canrestore !=
312 // thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
313 if(shared_data
->canrestore
!=
314 thread
->readIntReg(NumIntArchRegs
+ 4))
315 diffCanrestore
= true;
316 //if(shared_data->otherwin !=
317 // thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
318 if(shared_data
->otherwin
!=
319 thread
->readIntReg(NumIntArchRegs
+ 6))
321 //if(shared_data->cleanwin !=
322 // thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
323 if(shared_data
->cleanwin
!=
324 thread
->readIntReg(NumIntArchRegs
+ 5))
327 for (int i
= 0; i
< 64; i
++) {
328 if (shared_data
->itb
[i
] !=
329 thread
->getITBPtr()->TteRead(i
))
331 if (shared_data
->dtb
[i
] !=
332 thread
->getDTBPtr()->TteRead(i
))
336 if (diffPC
|| diffCC
|| diffInst
||
337 diffIntRegs
|| diffFpRegs
||
338 diffTpc
|| diffTnpc
|| diffTstate
|| diffTt
||
339 diffHpstate
|| diffHtstate
|| diffHtba
||
340 diffPstate
|| diffY
|| diffCcr
|| diffTl
|| diffFsr
||
341 diffGl
|| diffAsi
|| diffPil
|| diffCwp
||
342 diffCansave
|| diffCanrestore
||
343 diffOtherwin
|| diffCleanwin
|| diffTlb
) {
345 outs
<< "Differences found between M5 and Legion:";
351 outs
<< " [Instruction]";
353 outs
<< " [IntRegs]";
365 outs
<< " [Hpstate]";
367 outs
<< " [Htstate]";
389 outs
<< " [Cansave]";
391 outs
<< " [Canrestore]";
393 outs
<< " [Otherwin]";
395 outs
<< " [Cleanwin]";
398 outs
<< endl
<< endl
;
400 outs
<< right
<< setfill(' ') << setw(15)
401 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
402 << hex
<< m5Pc
<< endl
;
403 outs
<< setfill(' ') << setw(15)
404 << "Legion PC: " << "0x"
405 << setw(16) << setfill('0') << hex
406 << lgnPc
<< endl
<< endl
;
408 outs
<< right
<< setfill(' ') << setw(15)
410 << setw(16) << setfill('0') << hex
411 << thread
->getCpuPtr()->instCount() << endl
;
412 outs
<< setfill(' ') << setw(15)
413 << "Legion CC: " << "0x"
414 << setw(16) << setfill('0') << hex
415 << shared_data
->cycle_count
<< endl
<< endl
;
417 outs
<< setfill(' ') << setw(15)
418 << "M5 Inst: " << "0x"
419 << setw(8) << setfill('0') << hex
420 << staticInst
->machInst
421 << staticInst
->disassemble(m5Pc
, debugSymbolTable
)
424 TheISA::Decoder
*decoder
= thread
->getDecoderPtr();
425 decoder
->setTC(thread
);
426 decoder
->moreBytes(m5Pc
, m5Pc
, shared_data
->instruction
);
428 assert(decoder
->instReady());
431 StaticInstPtr legionInst
= decoder
->decode(tempPC
);
432 outs
<< setfill(' ') << setw(15)
434 << "0x" << setw(8) << setfill('0') << hex
435 << shared_data
->instruction
436 << legionInst
->disassemble(lgnPc
, debugSymbolTable
)
439 printSectionHeader(outs
, "General State");
440 printColumnLabels(outs
);
441 printRegPair(outs
, "HPstate",
442 thread
->readMiscRegNoEffect(MISCREG_HPSTATE
),
443 shared_data
->hpstate
| (1 << 11));
444 printRegPair(outs
, "Htba",
445 thread
->readMiscRegNoEffect(MISCREG_HTBA
),
447 printRegPair(outs
, "Pstate",
448 thread
->readMiscRegNoEffect(MISCREG_PSTATE
),
449 shared_data
->pstate
);
450 printRegPair(outs
, "Y",
451 //thread->readMiscRegNoEffect(MISCREG_Y),
452 thread
->readIntReg(NumIntArchRegs
+ 1),
454 printRegPair(outs
, "FSR",
455 thread
->readMiscRegNoEffect(MISCREG_FSR
),
457 printRegPair(outs
, "Ccr",
458 //thread->readMiscRegNoEffect(MISCREG_CCR),
459 thread
->readIntReg(NumIntArchRegs
+ 2),
461 printRegPair(outs
, "Tl",
462 thread
->readMiscRegNoEffect(MISCREG_TL
),
464 printRegPair(outs
, "Gl",
465 thread
->readMiscRegNoEffect(MISCREG_GL
),
467 printRegPair(outs
, "Asi",
468 thread
->readMiscRegNoEffect(MISCREG_ASI
),
470 printRegPair(outs
, "Pil",
471 thread
->readMiscRegNoEffect(MISCREG_PIL
),
473 printRegPair(outs
, "Cwp",
474 thread
->readMiscRegNoEffect(MISCREG_CWP
),
476 printRegPair(outs
, "Cansave",
477 //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
478 thread
->readIntReg(NumIntArchRegs
+ 3),
479 shared_data
->cansave
);
480 printRegPair(outs
, "Canrestore",
481 //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
482 thread
->readIntReg(NumIntArchRegs
+ 4),
483 shared_data
->canrestore
);
484 printRegPair(outs
, "Otherwin",
485 //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
486 thread
->readIntReg(NumIntArchRegs
+ 6),
487 shared_data
->otherwin
);
488 printRegPair(outs
, "Cleanwin",
489 //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
490 thread
->readIntReg(NumIntArchRegs
+ 5),
491 shared_data
->cleanwin
);
493 for (int i
= 1; i
<= MaxTL
; i
++) {
494 printLevelHeader(outs
, i
);
495 printColumnLabels(outs
);
496 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
497 printRegPair(outs
, "Tpc",
498 thread
->readMiscRegNoEffect(MISCREG_TPC
),
499 shared_data
->tpc
[i
-1]);
500 printRegPair(outs
, "Tnpc",
501 thread
->readMiscRegNoEffect(MISCREG_TNPC
),
502 shared_data
->tnpc
[i
-1]);
503 printRegPair(outs
, "Tstate",
504 thread
->readMiscRegNoEffect(MISCREG_TSTATE
),
505 shared_data
->tstate
[i
-1]);
506 printRegPair(outs
, "Tt",
507 thread
->readMiscRegNoEffect(MISCREG_TT
),
508 shared_data
->tt
[i
-1]);
509 printRegPair(outs
, "Htstate",
510 thread
->readMiscRegNoEffect(MISCREG_HTSTATE
),
511 shared_data
->htstate
[i
-1]);
513 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
516 printSectionHeader(outs
, "General Purpose Registers");
517 static const char * regtypes
[4] =
518 {"%g", "%o", "%l", "%i"};
519 for(int y
= 0; y
< 4; y
++) {
520 for(int x
= 0; x
< 8; x
++) {
522 sprintf(label
, "%s%d", regtypes
[y
], x
);
523 printRegPair(outs
, label
,
524 thread
->readIntReg(y
*8+x
),
525 shared_data
->intregs
[y
*8+x
]);
529 for (int x
= 0; x
< 32; x
++) {
531 sprintf(label
, "%%f%d", x
);
532 printRegPair(outs
, label
,
533 thread
->readFloatRegBits(x
*2),
534 shared_data
->fpregs
[x
]);
538 printColumnLabels(outs
);
540 for (int x
= 0; x
< 64; x
++) {
541 if (shared_data
->itb
[x
] !=
542 ULL(0xFFFFFFFFFFFFFFFF) ||
543 thread
->getITBPtr()->TteRead(x
) !=
544 ULL(0xFFFFFFFFFFFFFFFF)) {
545 sprintf(label
, "I-TLB:%02d", x
);
546 printRegPair(outs
, label
,
547 thread
->getITBPtr()->TteRead(x
),
548 shared_data
->itb
[x
]);
551 for (int x
= 0; x
< 64; x
++) {
552 if (shared_data
->dtb
[x
] !=
553 ULL(0xFFFFFFFFFFFFFFFF) ||
554 thread
->getDTBPtr()->TteRead(x
) !=
555 ULL(0xFFFFFFFFFFFFFFFF)) {
556 sprintf(label
, "D-TLB:%02d", x
);
557 printRegPair(outs
, label
,
558 thread
->getDTBPtr()->TteRead(x
),
559 shared_data
->dtb
[x
]);
562 thread
->getITBPtr()->dumpAll();
563 thread
->getDTBPtr()->dumpAll();
568 fatal("Differences found between Legion and M5\n");
573 shared_data
->flags
= OWN_LEGION
;
581 ////////////////////////////////////////////////////////////////////////
583 // ExeTracer Simulation Object
586 LegionTraceParams::create()
589 panic("Legion tracing only works in full system!");
590 return new Trace::LegionTrace(this);