src/cpu/legiontrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include "arch/isa_specific.hh"
  35 #if THE_ISA != SPARC_ISA
  36     #error Legion tracing only works with SPARC simulations!
  37 #endif
  38
  39 #include "config/full_system.hh"
  40 #if !FULL_SYSTEM
  41     #error Legion tracing only works in full system!
  42 #endif
  43
  44 #include <iomanip>
  45 #include <sys/ipc.h>
  46 #include <sys/shm.h>
  47
  48 #include "arch/sparc/predecoder.hh"
  49 #include "arch/sparc/regfile.hh"
  50 #include "arch/sparc/utility.hh"
  51 #include "base/socket.hh"
  52 #include "cpu/base.hh"
  53 #include "cpu/legiontrace.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "sim/system.hh"
  57
  58 #if FULL_SYSTEM
  59 #include "arch/tlb.hh"
  60 #endif
  61
  62 //XXX This is temporary
  63 #include "cpu/m5legion_interface.h"
  64
  65 using namespace std;
  66 using namespace TheISA;
  67
  68 #if FULL_SYSTEM
  69 static int diffcount = 0;
  70 static bool wasMicro = false;
  71 #endif
  72
  73 namespace Trace {
  74 SharedData *shared_data = NULL;
  75
  76 void
  77 setupSharedData()
  78 {
  79     int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
  80     if (shmfd < 0)
  81         fatal("Couldn't get shared memory fd. Is Legion running?");
  82
  83     shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
  84     if (shared_data == (SharedData*)-1)
  85         fatal("Couldn't allocate shared memory");
  86
  87     if (shared_data->flags != OWN_M5)
  88         fatal("Shared memory has invalid owner");
  89
  90     if (shared_data->version != VERSION)
  91         fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
  92               shared_data->version);
  93
  94     // step legion forward one cycle so we can get register values
  95     shared_data->flags = OWN_LEGION;
  96 }
  97
  98 ////////////////////////////////////////////////////////////////////////
  99 //
 100 //  Utility methods for pretty printing a report about a difference
 101 //
 102
 103 inline char * genCenteredLabel(int length, char * buffer, char * label)
 104 {
 105     int labelLength = strlen(label);
 106     assert(labelLength <= length);
 107     int leftPad = (length - labelLength) / 2;
 108     int rightPad = length - leftPad - labelLength;
 109     char format[64];
 110     sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
 111     sprintf(buffer, format, "", label, "");
 112     return buffer;
 113 }
 114
 115 inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
 116 {
 117     ccprintf(os, "  %16s  |  %#018x   %s   %#-018x  \n",
 118             title, a, (a == b) ? "|" : "X", b);
 119 }
 120
 121 inline void printColumnLabels(ostream & os)
 122 {
 123     static char * regLabel = genCenteredLabel(16, new char[17], "Register");
 124     static char * m5Label = genCenteredLabel(18, new char[18], "M5");
 125     static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
 126     ccprintf(os, "  %s  |  %s   |   %s  \n", regLabel, m5Label, legionLabel);
 127     ccprintf(os, "--------------------+-----------------------+-----------------------\n");
 128 }
 129
 130 inline void printSectionHeader(ostream & os, char * name)
 131 {
 132     char sectionString[70];
 133     genCenteredLabel(69, sectionString, name);
 134     ccprintf(os, "====================================================================\n");
 135     ccprintf(os, "%69s\n", sectionString);
 136     ccprintf(os, "====================================================================\n");
 137 }
 138
 139 inline void printLevelHeader(ostream & os, int level)
 140 {
 141     char sectionString[70];
 142     char levelName[70];
 143     sprintf(levelName, "Trap stack level %d", level);
 144     genCenteredLabel(69, sectionString, levelName);
 145     ccprintf(os, "====================================================================\n");
 146     ccprintf(os, "%69s\n", sectionString);
 147     ccprintf(os, "====================================================================\n");
 148 }
 149
 150 void
 151 Trace::LegionTraceRecord::dump()
 152 {
 153     ostream &outs = Trace::output();
 154
 155     static TheISA::Predecoder predecoder(NULL);
 156     // Compare
 157     bool compared = false;
 158     bool diffPC   = false;
 159     bool diffCC   = false;
 160     bool diffInst = false;
 161     bool diffIntRegs = false;
 162     bool diffFpRegs = false;
 163     bool diffTpc = false;
 164     bool diffTnpc = false;
 165     bool diffTstate = false;
 166     bool diffTt = false;
 167     bool diffTba = false;
 168     bool diffHpstate = false;
 169     bool diffHtstate = false;
 170     bool diffHtba = false;
 171     bool diffPstate = false;
 172     bool diffY = false;
 173     bool diffFsr = false;
 174     bool diffCcr = false;
 175     bool diffTl = false;
 176     bool diffGl = false;
 177     bool diffAsi = false;
 178     bool diffPil = false;
 179     bool diffCwp = false;
 180     bool diffCansave = false;
 181     bool diffCanrestore = false;
 182     bool diffOtherwin = false;
 183     bool diffCleanwin = false;
 184     bool diffTlb = false;
 185     Addr m5Pc, lgnPc;
 186
 187     if (!shared_data)
 188         setupSharedData();
 189
 190     // We took a trap on a micro-op...
 191     if (wasMicro && !staticInst->isMicroop())
 192     {
 193         // let's skip comparing this tick
 194         while (!compared)
 195             if (shared_data->flags == OWN_M5) {
 196                 shared_data->flags = OWN_LEGION;
 197                 compared = true;
 198             }
 199         compared = false;
 200         wasMicro = false;
 201     }
 202
 203     if (staticInst->isLastMicroop())
 204         wasMicro = false;
 205     else if (staticInst->isMicroop())
 206         wasMicro = true;
 207
 208
 209     if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
 210         while (!compared) {
 211             if (shared_data->flags == OWN_M5) {
 212                 m5Pc = PC & SparcISA::PAddrImplMask;
 213                 if (bits(shared_data->pstate,3,3)) {
 214                     m5Pc &= mask(32);
 215                 }
 216                 lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
 217                 if (lgnPc != m5Pc)
 218                    diffPC = true;
 219
 220                 if (shared_data->cycle_count !=
 221                         thread->getCpuPtr()->instCount())
 222                     diffCC = true;
 223
 224                 if (shared_data->instruction !=
 225                         (SparcISA::MachInst)staticInst->machInst) {
 226                     diffInst = true;
 227                 }
 228                 // assume we have %g0 working correctly
 229                 for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
 230                     if (thread->readIntReg(i) != shared_data->intregs[i]) {
 231                         diffIntRegs = true;
 232                     }
 233                 }
 234                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
 235                     if (thread->readFloatRegBits(i*2,
 236                                 FloatRegFile::DoubleWidth) !=
 237                             shared_data->fpregs[i]) {
 238                         diffFpRegs = true;
 239                     }
 240                 }
 241                         uint64_t oldTl =
 242                             thread->readMiscRegNoEffect(MISCREG_TL);
 243                 if (oldTl != shared_data->tl)
 244                     diffTl = true;
 245                 for (int i = 1; i <= MaxTL; i++) {
 246                     thread->setMiscRegNoEffect(MISCREG_TL, i);
 247                     if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
 248                             shared_data->tpc[i-1])
 249                         diffTpc = true;
 250                     if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
 251                             shared_data->tnpc[i-1])
 252                         diffTnpc = true;
 253                     if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
 254                             shared_data->tstate[i-1])
 255                         diffTstate = true;
 256                     if (thread->readMiscRegNoEffect(MISCREG_TT) !=
 257                             shared_data->tt[i-1])
 258                         diffTt = true;
 259                     if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
 260                             shared_data->htstate[i-1])
 261                         diffHtstate = true;
 262                 }
 263                 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 264
 265                 if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
 266                     diffTba = true;
 267                 //When the hpstate register is read by an instruction,
 268                 //legion has bit 11 set. When it's in storage, it doesn't.
 269                 //Since we don't directly support seperate interpretations
 270                 //of the registers like that, the bit is always set to 1 and
 271                 //we just don't compare it. It's not supposed to matter
 272                 //anyway.
 273                 if((shared_data->hpstate | (1 << 11)) !=
 274                         thread->readMiscRegNoEffect(MISCREG_HPSTATE))
 275                     diffHpstate = true;
 276                 if(shared_data->htba !=
 277                         thread->readMiscRegNoEffect(MISCREG_HTBA))
 278                     diffHtba = true;
 279                 if(shared_data->pstate !=
 280                         thread->readMiscRegNoEffect(MISCREG_PSTATE))
 281                     diffPstate = true;
 282                 //if(shared_data->y !=
 283                 //        thread->readMiscRegNoEffect(MISCREG_Y))
 284                 if(shared_data->y !=
 285                         thread->readIntReg(NumIntArchRegs + 1))
 286                     diffY = true;
 287                 if(shared_data->fsr !=
 288                         thread->readMiscRegNoEffect(MISCREG_FSR)) {
 289                     diffFsr = true;
 290                     if (mbits(shared_data->fsr, 63,10) ==
 291                             mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
 292                                 63,10)) {
 293                         thread->setMiscRegNoEffect(MISCREG_FSR,
 294                                 shared_data->fsr);
 295                         diffFsr = false;
 296                     }
 297                 }
 298                 //if(shared_data->ccr !=
 299                 //        thread->readMiscRegNoEffect(MISCREG_CCR))
 300                 if(shared_data->ccr !=
 301                         thread->readIntReg(NumIntArchRegs + 2))
 302                     diffCcr = true;
 303                 if(shared_data->gl !=
 304                         thread->readMiscRegNoEffect(MISCREG_GL))
 305                     diffGl = true;
 306                 if(shared_data->asi !=
 307                         thread->readMiscRegNoEffect(MISCREG_ASI))
 308                     diffAsi = true;
 309                 if(shared_data->pil !=
 310                         thread->readMiscRegNoEffect(MISCREG_PIL))
 311                     diffPil = true;
 312                 if(shared_data->cwp !=
 313                         thread->readMiscRegNoEffect(MISCREG_CWP))
 314                     diffCwp = true;
 315                 //if(shared_data->cansave !=
 316                 //        thread->readMiscRegNoEffect(MISCREG_CANSAVE))
 317                 if(shared_data->cansave !=
 318                         thread->readIntReg(NumIntArchRegs + 3))
 319                     diffCansave = true;
 320                 //if(shared_data->canrestore !=
 321                 //        thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
 322                 if(shared_data->canrestore !=
 323                         thread->readIntReg(NumIntArchRegs + 4))
 324                     diffCanrestore = true;
 325                 //if(shared_data->otherwin !=
 326                 //        thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
 327                 if(shared_data->otherwin !=
 328                         thread->readIntReg(NumIntArchRegs + 6))
 329                     diffOtherwin = true;
 330                 //if(shared_data->cleanwin !=
 331                 //        thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
 332                 if(shared_data->cleanwin !=
 333                         thread->readIntReg(NumIntArchRegs + 5))
 334                     diffCleanwin = true;
 335
 336                 for (int i = 0; i < 64; i++) {
 337                     if (shared_data->itb[i] !=
 338                             thread->getITBPtr()->TteRead(i))
 339                         diffTlb = true;
 340                     if (shared_data->dtb[i] !=
 341                             thread->getDTBPtr()->TteRead(i))
 342                         diffTlb = true;
 343                 }
 344
 345                 if (diffPC || diffCC || diffInst ||
 346                     diffIntRegs || diffFpRegs ||
 347                     diffTpc || diffTnpc || diffTstate || diffTt ||
 348                     diffHpstate || diffHtstate || diffHtba ||
 349                     diffPstate || diffY || diffCcr || diffTl || diffFsr ||
 350                     diffGl || diffAsi || diffPil || diffCwp ||
 351                     diffCansave || diffCanrestore ||
 352                     diffOtherwin || diffCleanwin || diffTlb) {
 353
 354                     outs << "Differences found between M5 and Legion:";
 355                     if (diffPC)
 356                         outs << " [PC]";
 357                     if (diffCC)
 358                         outs << " [CC]";
 359                     if (diffInst)
 360                         outs << " [Instruction]";
 361                     if (diffIntRegs)
 362                         outs << " [IntRegs]";
 363                     if (diffFpRegs)
 364                         outs << " [FpRegs]";
 365                     if (diffTpc)
 366                         outs << " [Tpc]";
 367                     if (diffTnpc)
 368                         outs << " [Tnpc]";
 369                     if (diffTstate)
 370                         outs << " [Tstate]";
 371                     if (diffTt)
 372                         outs << " [Tt]";
 373                     if (diffHpstate)
 374                         outs << " [Hpstate]";
 375                     if (diffHtstate)
 376                         outs << " [Htstate]";
 377                     if (diffHtba)
 378                         outs << " [Htba]";
 379                     if (diffPstate)
 380                         outs << " [Pstate]";
 381                     if (diffY)
 382                         outs << " [Y]";
 383                     if (diffFsr)
 384                         outs << " [FSR]";
 385                     if (diffCcr)
 386                         outs << " [Ccr]";
 387                     if (diffTl)
 388                         outs << " [Tl]";
 389                     if (diffGl)
 390                         outs << " [Gl]";
 391                     if (diffAsi)
 392                         outs << " [Asi]";
 393                     if (diffPil)
 394                         outs << " [Pil]";
 395                     if (diffCwp)
 396                         outs << " [Cwp]";
 397                     if (diffCansave)
 398                         outs << " [Cansave]";
 399                     if (diffCanrestore)
 400                         outs << " [Canrestore]";
 401                     if (diffOtherwin)
 402                         outs << " [Otherwin]";
 403                     if (diffCleanwin)
 404                         outs << " [Cleanwin]";
 405                     if (diffTlb)
 406                         outs << " [Tlb]";
 407                     outs << endl << endl;
 408
 409                     outs << right << setfill(' ') << setw(15)
 410                          << "M5 PC: " << "0x"<< setw(16) << setfill('0')
 411                          << hex << m5Pc << endl;
 412                     outs << setfill(' ') << setw(15)
 413                          << "Legion PC: " << "0x"
 414                          << setw(16) << setfill('0') << hex
 415                          << lgnPc << endl << endl;
 416
 417                     outs << right << setfill(' ') << setw(15)
 418                          << "M5 CC: " << "0x"
 419                          << setw(16) << setfill('0') << hex
 420                          << thread->getCpuPtr()->instCount() << endl;
 421                     outs << setfill(' ') << setw(15)
 422                          << "Legion CC: " << "0x"
 423                          << setw(16) << setfill('0') << hex
 424                          << shared_data->cycle_count << endl << endl;
 425
 426                     outs << setfill(' ') << setw(15)
 427                          << "M5 Inst: " << "0x"
 428                          << setw(8) << setfill('0') << hex
 429                          << staticInst->machInst
 430                          << staticInst->disassemble(m5Pc, debugSymbolTable)
 431                          << endl;
 432
 433                     predecoder.setTC(thread);
 434                     predecoder.moreBytes(m5Pc, m5Pc,
 435                             shared_data->instruction);
 436
 437                     assert(predecoder.extMachInstReady());
 438
 439                     StaticInstPtr legionInst =
 440                         StaticInst::decode(predecoder.getExtMachInst(), lgnPc);
 441                     outs << setfill(' ') << setw(15)
 442                          << " Legion Inst: "
 443                          << "0x" << setw(8) << setfill('0') << hex
 444                          << shared_data->instruction
 445                          << legionInst->disassemble(lgnPc, debugSymbolTable)
 446                          << endl << endl;
 447
 448                     printSectionHeader(outs, "General State");
 449                     printColumnLabels(outs);
 450                     printRegPair(outs, "HPstate",
 451                             thread->readMiscRegNoEffect(MISCREG_HPSTATE),
 452                             shared_data->hpstate | (1 << 11));
 453                     printRegPair(outs, "Htba",
 454                             thread->readMiscRegNoEffect(MISCREG_HTBA),
 455                             shared_data->htba);
 456                     printRegPair(outs, "Pstate",
 457                             thread->readMiscRegNoEffect(MISCREG_PSTATE),
 458                             shared_data->pstate);
 459                     printRegPair(outs, "Y",
 460                             //thread->readMiscRegNoEffect(MISCREG_Y),
 461                             thread->readIntReg(NumIntArchRegs + 1),
 462                             shared_data->y);
 463                     printRegPair(outs, "FSR",
 464                             thread->readMiscRegNoEffect(MISCREG_FSR),
 465                             shared_data->fsr);
 466                     printRegPair(outs, "Ccr",
 467                             //thread->readMiscRegNoEffect(MISCREG_CCR),
 468                             thread->readIntReg(NumIntArchRegs + 2),
 469                             shared_data->ccr);
 470                     printRegPair(outs, "Tl",
 471                             thread->readMiscRegNoEffect(MISCREG_TL),
 472                             shared_data->tl);
 473                     printRegPair(outs, "Gl",
 474                             thread->readMiscRegNoEffect(MISCREG_GL),
 475                             shared_data->gl);
 476                     printRegPair(outs, "Asi",
 477                             thread->readMiscRegNoEffect(MISCREG_ASI),
 478                             shared_data->asi);
 479                     printRegPair(outs, "Pil",
 480                             thread->readMiscRegNoEffect(MISCREG_PIL),
 481                             shared_data->pil);
 482                     printRegPair(outs, "Cwp",
 483                             thread->readMiscRegNoEffect(MISCREG_CWP),
 484                             shared_data->cwp);
 485                     printRegPair(outs, "Cansave",
 486                             //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
 487                             thread->readIntReg(NumIntArchRegs + 3),
 488                             shared_data->cansave);
 489                     printRegPair(outs, "Canrestore",
 490                             //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
 491                             thread->readIntReg(NumIntArchRegs + 4),
 492                             shared_data->canrestore);
 493                     printRegPair(outs, "Otherwin",
 494                             //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
 495                             thread->readIntReg(NumIntArchRegs + 6),
 496                             shared_data->otherwin);
 497                     printRegPair(outs, "Cleanwin",
 498                             //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
 499                             thread->readIntReg(NumIntArchRegs + 5),
 500                             shared_data->cleanwin);
 501                     outs << endl;
 502                     for (int i = 1; i <= MaxTL; i++) {
 503                         printLevelHeader(outs, i);
 504                         printColumnLabels(outs);
 505                         thread->setMiscRegNoEffect(MISCREG_TL, i);
 506                         printRegPair(outs, "Tpc",
 507                                 thread->readMiscRegNoEffect(MISCREG_TPC),
 508                                 shared_data->tpc[i-1]);
 509                         printRegPair(outs, "Tnpc",
 510                                 thread->readMiscRegNoEffect(MISCREG_TNPC),
 511                                 shared_data->tnpc[i-1]);
 512                         printRegPair(outs, "Tstate",
 513                                 thread->readMiscRegNoEffect(MISCREG_TSTATE),
 514                                 shared_data->tstate[i-1]);
 515                         printRegPair(outs, "Tt",
 516                                 thread->readMiscRegNoEffect(MISCREG_TT),
 517                                 shared_data->tt[i-1]);
 518                         printRegPair(outs, "Htstate",
 519                                 thread->readMiscRegNoEffect(MISCREG_HTSTATE),
 520                                 shared_data->htstate[i-1]);
 521                     }
 522                     thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 523                     outs << endl;
 524
 525                     printSectionHeader(outs, "General Purpose Registers");
 526                     static const char * regtypes[4] =
 527                         {"%g", "%o", "%l", "%i"};
 528                     for(int y = 0; y < 4; y++) {
 529                         for(int x = 0; x < 8; x++) {
 530                             char label[8];
 531                             sprintf(label, "%s%d", regtypes[y], x);
 532                             printRegPair(outs, label,
 533                                     thread->readIntReg(y*8+x),
 534                                     shared_data->intregs[y*8+x]);
 535                         }
 536                     }
 537                     if (diffFpRegs) {
 538                         for (int x = 0; x < 32; x++) {
 539                             char label[8];
 540                             sprintf(label, "%%f%d", x);
 541                             printRegPair(outs, label,
 542                                 thread->readFloatRegBits(x*2,
 543                                     FloatRegFile::DoubleWidth),
 544                                 shared_data->fpregs[x]);
 545                         }
 546                     }
 547                     if (diffTlb) {
 548                         printColumnLabels(outs);
 549                         char label[8];
 550                         for (int x = 0; x < 64; x++) {
 551                             if (shared_data->itb[x] !=
 552                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 553                                 thread->getITBPtr()->TteRead(x) !=
 554                                 ULL(0xFFFFFFFFFFFFFFFF)) {
 555                                     sprintf(label, "I-TLB:%02d", x);
 556                                     printRegPair(outs, label,
 557                                             thread->getITBPtr()->TteRead(x),
 558                                             shared_data->itb[x]);
 559                             }
 560                         }
 561                         for (int x = 0; x < 64; x++) {
 562                             if (shared_data->dtb[x] !=
 563                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 564                                 thread->getDTBPtr()->TteRead(x) !=
 565                                 ULL(0xFFFFFFFFFFFFFFFF))  {
 566                                     sprintf(label, "D-TLB:%02d", x);
 567                                     printRegPair(outs, label,
 568                                             thread->getDTBPtr()->TteRead(x),
 569                                             shared_data->dtb[x]);
 570                             }
 571                         }
 572                         thread->getITBPtr()->dumpAll();
 573                         thread->getDTBPtr()->dumpAll();
 574                     }
 575
 576                     diffcount++;
 577                     if (diffcount > 3)
 578                         fatal("Differences found between Legion and M5\n");
 579                 } else
 580                     diffcount = 0;
 581
 582                 compared = true;
 583                 shared_data->flags = OWN_LEGION;
 584             }
 585         } // while
 586     } // if not microop
 587 }
 588
 589 /* namespace Trace */ }
 590
 591 ////////////////////////////////////////////////////////////////////////
 592 //
 593 //  ExeTracer Simulation Object
 594 //
 595 Trace::LegionTrace *
 596 LegionTraceParams::create()
 597 {
 598     return new Trace::LegionTrace(this);
 599 };