src/cpu/legiontrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include "config/the_isa.hh"
  35 #if THE_ISA != SPARC_ISA
  36     #error Legion tracing only works with SPARC simulations!
  37 #endif
  38
  39 #include "config/full_system.hh"
  40 #if !FULL_SYSTEM
  41     #error Legion tracing only works in full system!
  42 #endif
  43
  44 #include <sys/ipc.h>
  45 #include <sys/shm.h>
  46
  47 #include <cstdio>
  48 #include <iomanip>
  49
  50 #include "arch/sparc/predecoder.hh"
  51 #include "arch/sparc/registers.hh"
  52 #include "arch/sparc/utility.hh"
  53 #include "base/socket.hh"
  54 #include "cpu/base.hh"
  55 #include "cpu/decode.hh"
  56 #include "cpu/legiontrace.hh"
  57 #include "cpu/static_inst.hh"
  58 #include "cpu/thread_context.hh"
  59 #include "sim/system.hh"
  60
  61 #if FULL_SYSTEM
  62 #include "arch/tlb.hh"
  63 #endif
  64
  65 //XXX This is temporary
  66 #include "cpu/m5legion_interface.h"
  67
  68 using namespace std;
  69 using namespace TheISA;
  70
  71 #if FULL_SYSTEM
  72 static int diffcount = 0;
  73 static bool wasMicro = false;
  74 #endif
  75
  76 namespace Trace {
  77 SharedData *shared_data = NULL;
  78
  79 void
  80 setupSharedData()
  81 {
  82     int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
  83     if (shmfd < 0)
  84         fatal("Couldn't get shared memory fd. Is Legion running?");
  85
  86     shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
  87     if (shared_data == (SharedData*)-1)
  88         fatal("Couldn't allocate shared memory");
  89
  90     if (shared_data->flags != OWN_M5)
  91         fatal("Shared memory has invalid owner");
  92
  93     if (shared_data->version != VERSION)
  94         fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
  95               shared_data->version);
  96
  97     // step legion forward one cycle so we can get register values
  98     shared_data->flags = OWN_LEGION;
  99 }
 100
 101 ////////////////////////////////////////////////////////////////////////
 102 //
 103 //  Utility methods for pretty printing a report about a difference
 104 //
 105
 106 inline char * genCenteredLabel(int length, char * buffer, const char * label)
 107 {
 108     int labelLength = strlen(label);
 109     assert(labelLength <= length);
 110     int leftPad = (length - labelLength) / 2;
 111     int rightPad = length - leftPad - labelLength;
 112     char format[64];
 113     sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
 114     sprintf(buffer, format, "", label, "");
 115     return buffer;
 116 }
 117
 118 inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
 119 {
 120     ccprintf(os, "  %16s  |  %#018x   %s   %#-018x  \n",
 121             title, a, (a == b) ? "|" : "X", b);
 122 }
 123
 124 inline void printColumnLabels(ostream & os)
 125 {
 126     static char * regLabel = genCenteredLabel(16, new char[17], "Register");
 127     static char * m5Label = genCenteredLabel(18, new char[18], "M5");
 128     static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
 129     ccprintf(os, "  %s  |  %s   |   %s  \n", regLabel, m5Label, legionLabel);
 130     ccprintf(os, "--------------------+-----------------------+-----------------------\n");
 131 }
 132
 133 inline void printSectionHeader(ostream & os, const char * name)
 134 {
 135     char sectionString[70];
 136     genCenteredLabel(69, sectionString, name);
 137     ccprintf(os, "====================================================================\n");
 138     ccprintf(os, "%69s\n", sectionString);
 139     ccprintf(os, "====================================================================\n");
 140 }
 141
 142 inline void printLevelHeader(ostream & os, int level)
 143 {
 144     char sectionString[70];
 145     char levelName[70];
 146     sprintf(levelName, "Trap stack level %d", level);
 147     genCenteredLabel(69, sectionString, levelName);
 148     ccprintf(os, "====================================================================\n");
 149     ccprintf(os, "%69s\n", sectionString);
 150     ccprintf(os, "====================================================================\n");
 151 }
 152
 153 void
 154 Trace::LegionTraceRecord::dump()
 155 {
 156     ostream &outs = Trace::output();
 157
 158     static TheISA::Predecoder predecoder(NULL);
 159     // Compare
 160     bool compared = false;
 161     bool diffPC   = false;
 162     bool diffCC   = false;
 163     bool diffInst = false;
 164     bool diffIntRegs = false;
 165     bool diffFpRegs = false;
 166     bool diffTpc = false;
 167     bool diffTnpc = false;
 168     bool diffTstate = false;
 169     bool diffTt = false;
 170     bool diffTba = false;
 171     bool diffHpstate = false;
 172     bool diffHtstate = false;
 173     bool diffHtba = false;
 174     bool diffPstate = false;
 175     bool diffY = false;
 176     bool diffFsr = false;
 177     bool diffCcr = false;
 178     bool diffTl = false;
 179     bool diffGl = false;
 180     bool diffAsi = false;
 181     bool diffPil = false;
 182     bool diffCwp = false;
 183     bool diffCansave = false;
 184     bool diffCanrestore = false;
 185     bool diffOtherwin = false;
 186     bool diffCleanwin = false;
 187     bool diffTlb = false;
 188     Addr m5Pc, lgnPc;
 189
 190     if (!shared_data)
 191         setupSharedData();
 192
 193     // We took a trap on a micro-op...
 194     if (wasMicro && !staticInst->isMicroop())
 195     {
 196         // let's skip comparing this tick
 197         while (!compared)
 198             if (shared_data->flags == OWN_M5) {
 199                 shared_data->flags = OWN_LEGION;
 200                 compared = true;
 201             }
 202         compared = false;
 203         wasMicro = false;
 204     }
 205
 206     if (staticInst->isLastMicroop())
 207         wasMicro = false;
 208     else if (staticInst->isMicroop())
 209         wasMicro = true;
 210
 211
 212     if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
 213         while (!compared) {
 214             if (shared_data->flags == OWN_M5) {
 215                 m5Pc = pc.instAddr() & SparcISA::PAddrImplMask;
 216                 if (bits(shared_data->pstate,3,3)) {
 217                     m5Pc &= mask(32);
 218                 }
 219                 lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
 220                 if (lgnPc != m5Pc)
 221                    diffPC = true;
 222
 223                 if (shared_data->cycle_count !=
 224                         thread->getCpuPtr()->instCount())
 225                     diffCC = true;
 226
 227                 if (shared_data->instruction !=
 228                         (SparcISA::MachInst)staticInst->machInst) {
 229                     diffInst = true;
 230                 }
 231                 // assume we have %g0 working correctly
 232                 for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
 233                     if (thread->readIntReg(i) != shared_data->intregs[i]) {
 234                         diffIntRegs = true;
 235                     }
 236                 }
 237                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
 238                     if (thread->readFloatRegBits(i*2) !=
 239                             shared_data->fpregs[i]) {
 240                         diffFpRegs = true;
 241                     }
 242                 }
 243                         uint64_t oldTl =
 244                             thread->readMiscRegNoEffect(MISCREG_TL);
 245                 if (oldTl != shared_data->tl)
 246                     diffTl = true;
 247                 for (int i = 1; i <= MaxTL; i++) {
 248                     thread->setMiscRegNoEffect(MISCREG_TL, i);
 249                     if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
 250                             shared_data->tpc[i-1])
 251                         diffTpc = true;
 252                     if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
 253                             shared_data->tnpc[i-1])
 254                         diffTnpc = true;
 255                     if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
 256                             shared_data->tstate[i-1])
 257                         diffTstate = true;
 258                     if (thread->readMiscRegNoEffect(MISCREG_TT) !=
 259                             shared_data->tt[i-1])
 260                         diffTt = true;
 261                     if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
 262                             shared_data->htstate[i-1])
 263                         diffHtstate = true;
 264                 }
 265                 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 266
 267                 if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
 268                     diffTba = true;
 269                 //When the hpstate register is read by an instruction,
 270                 //legion has bit 11 set. When it's in storage, it doesn't.
 271                 //Since we don't directly support seperate interpretations
 272                 //of the registers like that, the bit is always set to 1 and
 273                 //we just don't compare it. It's not supposed to matter
 274                 //anyway.
 275                 if((shared_data->hpstate | (1 << 11)) !=
 276                         thread->readMiscRegNoEffect(MISCREG_HPSTATE))
 277                     diffHpstate = true;
 278                 if(shared_data->htba !=
 279                         thread->readMiscRegNoEffect(MISCREG_HTBA))
 280                     diffHtba = true;
 281                 if(shared_data->pstate !=
 282                         thread->readMiscRegNoEffect(MISCREG_PSTATE))
 283                     diffPstate = true;
 284                 //if(shared_data->y !=
 285                 //        thread->readMiscRegNoEffect(MISCREG_Y))
 286                 if(shared_data->y !=
 287                         thread->readIntReg(NumIntArchRegs + 1))
 288                     diffY = true;
 289                 if(shared_data->fsr !=
 290                         thread->readMiscRegNoEffect(MISCREG_FSR)) {
 291                     diffFsr = true;
 292                     if (mbits(shared_data->fsr, 63,10) ==
 293                             mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
 294                                 63,10)) {
 295                         thread->setMiscRegNoEffect(MISCREG_FSR,
 296                                 shared_data->fsr);
 297                         diffFsr = false;
 298                     }
 299                 }
 300                 //if(shared_data->ccr !=
 301                 //        thread->readMiscRegNoEffect(MISCREG_CCR))
 302                 if(shared_data->ccr !=
 303                         thread->readIntReg(NumIntArchRegs + 2))
 304                     diffCcr = true;
 305                 if(shared_data->gl !=
 306                         thread->readMiscRegNoEffect(MISCREG_GL))
 307                     diffGl = true;
 308                 if(shared_data->asi !=
 309                         thread->readMiscRegNoEffect(MISCREG_ASI))
 310                     diffAsi = true;
 311                 if(shared_data->pil !=
 312                         thread->readMiscRegNoEffect(MISCREG_PIL))
 313                     diffPil = true;
 314                 if(shared_data->cwp !=
 315                         thread->readMiscRegNoEffect(MISCREG_CWP))
 316                     diffCwp = true;
 317                 //if(shared_data->cansave !=
 318                 //        thread->readMiscRegNoEffect(MISCREG_CANSAVE))
 319                 if(shared_data->cansave !=
 320                         thread->readIntReg(NumIntArchRegs + 3))
 321                     diffCansave = true;
 322                 //if(shared_data->canrestore !=
 323                 //        thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
 324                 if(shared_data->canrestore !=
 325                         thread->readIntReg(NumIntArchRegs + 4))
 326                     diffCanrestore = true;
 327                 //if(shared_data->otherwin !=
 328                 //        thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
 329                 if(shared_data->otherwin !=
 330                         thread->readIntReg(NumIntArchRegs + 6))
 331                     diffOtherwin = true;
 332                 //if(shared_data->cleanwin !=
 333                 //        thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
 334                 if(shared_data->cleanwin !=
 335                         thread->readIntReg(NumIntArchRegs + 5))
 336                     diffCleanwin = true;
 337
 338                 for (int i = 0; i < 64; i++) {
 339                     if (shared_data->itb[i] !=
 340                             thread->getITBPtr()->TteRead(i))
 341                         diffTlb = true;
 342                     if (shared_data->dtb[i] !=
 343                             thread->getDTBPtr()->TteRead(i))
 344                         diffTlb = true;
 345                 }
 346
 347                 if (diffPC || diffCC || diffInst ||
 348                     diffIntRegs || diffFpRegs ||
 349                     diffTpc || diffTnpc || diffTstate || diffTt ||
 350                     diffHpstate || diffHtstate || diffHtba ||
 351                     diffPstate || diffY || diffCcr || diffTl || diffFsr ||
 352                     diffGl || diffAsi || diffPil || diffCwp ||
 353                     diffCansave || diffCanrestore ||
 354                     diffOtherwin || diffCleanwin || diffTlb) {
 355
 356                     outs << "Differences found between M5 and Legion:";
 357                     if (diffPC)
 358                         outs << " [PC]";
 359                     if (diffCC)
 360                         outs << " [CC]";
 361                     if (diffInst)
 362                         outs << " [Instruction]";
 363                     if (diffIntRegs)
 364                         outs << " [IntRegs]";
 365                     if (diffFpRegs)
 366                         outs << " [FpRegs]";
 367                     if (diffTpc)
 368                         outs << " [Tpc]";
 369                     if (diffTnpc)
 370                         outs << " [Tnpc]";
 371                     if (diffTstate)
 372                         outs << " [Tstate]";
 373                     if (diffTt)
 374                         outs << " [Tt]";
 375                     if (diffHpstate)
 376                         outs << " [Hpstate]";
 377                     if (diffHtstate)
 378                         outs << " [Htstate]";
 379                     if (diffHtba)
 380                         outs << " [Htba]";
 381                     if (diffPstate)
 382                         outs << " [Pstate]";
 383                     if (diffY)
 384                         outs << " [Y]";
 385                     if (diffFsr)
 386                         outs << " [FSR]";
 387                     if (diffCcr)
 388                         outs << " [Ccr]";
 389                     if (diffTl)
 390                         outs << " [Tl]";
 391                     if (diffGl)
 392                         outs << " [Gl]";
 393                     if (diffAsi)
 394                         outs << " [Asi]";
 395                     if (diffPil)
 396                         outs << " [Pil]";
 397                     if (diffCwp)
 398                         outs << " [Cwp]";
 399                     if (diffCansave)
 400                         outs << " [Cansave]";
 401                     if (diffCanrestore)
 402                         outs << " [Canrestore]";
 403                     if (diffOtherwin)
 404                         outs << " [Otherwin]";
 405                     if (diffCleanwin)
 406                         outs << " [Cleanwin]";
 407                     if (diffTlb)
 408                         outs << " [Tlb]";
 409                     outs << endl << endl;
 410
 411                     outs << right << setfill(' ') << setw(15)
 412                          << "M5 PC: " << "0x"<< setw(16) << setfill('0')
 413                          << hex << m5Pc << endl;
 414                     outs << setfill(' ') << setw(15)
 415                          << "Legion PC: " << "0x"
 416                          << setw(16) << setfill('0') << hex
 417                          << lgnPc << endl << endl;
 418
 419                     outs << right << setfill(' ') << setw(15)
 420                          << "M5 CC: " << "0x"
 421                          << setw(16) << setfill('0') << hex
 422                          << thread->getCpuPtr()->instCount() << endl;
 423                     outs << setfill(' ') << setw(15)
 424                          << "Legion CC: " << "0x"
 425                          << setw(16) << setfill('0') << hex
 426                          << shared_data->cycle_count << endl << endl;
 427
 428                     outs << setfill(' ') << setw(15)
 429                          << "M5 Inst: " << "0x"
 430                          << setw(8) << setfill('0') << hex
 431                          << staticInst->machInst
 432                          << staticInst->disassemble(m5Pc, debugSymbolTable)
 433                          << endl;
 434
 435                     predecoder.setTC(thread);
 436                     predecoder.moreBytes(m5Pc, m5Pc, shared_data->instruction);
 437
 438                     assert(predecoder.extMachInstReady());
 439
 440                     PCState tempPC = pc;
 441                     StaticInstPtr legionInst =
 442                         thread->getDecoderPtr()->decode(
 443                                 predecoder.getExtMachInst(tempPC), lgnPc);
 444                     outs << setfill(' ') << setw(15)
 445                          << " Legion Inst: "
 446                          << "0x" << setw(8) << setfill('0') << hex
 447                          << shared_data->instruction
 448                          << legionInst->disassemble(lgnPc, debugSymbolTable)
 449                          << endl << endl;
 450
 451                     printSectionHeader(outs, "General State");
 452                     printColumnLabels(outs);
 453                     printRegPair(outs, "HPstate",
 454                             thread->readMiscRegNoEffect(MISCREG_HPSTATE),
 455                             shared_data->hpstate | (1 << 11));
 456                     printRegPair(outs, "Htba",
 457                             thread->readMiscRegNoEffect(MISCREG_HTBA),
 458                             shared_data->htba);
 459                     printRegPair(outs, "Pstate",
 460                             thread->readMiscRegNoEffect(MISCREG_PSTATE),
 461                             shared_data->pstate);
 462                     printRegPair(outs, "Y",
 463                             //thread->readMiscRegNoEffect(MISCREG_Y),
 464                             thread->readIntReg(NumIntArchRegs + 1),
 465                             shared_data->y);
 466                     printRegPair(outs, "FSR",
 467                             thread->readMiscRegNoEffect(MISCREG_FSR),
 468                             shared_data->fsr);
 469                     printRegPair(outs, "Ccr",
 470                             //thread->readMiscRegNoEffect(MISCREG_CCR),
 471                             thread->readIntReg(NumIntArchRegs + 2),
 472                             shared_data->ccr);
 473                     printRegPair(outs, "Tl",
 474                             thread->readMiscRegNoEffect(MISCREG_TL),
 475                             shared_data->tl);
 476                     printRegPair(outs, "Gl",
 477                             thread->readMiscRegNoEffect(MISCREG_GL),
 478                             shared_data->gl);
 479                     printRegPair(outs, "Asi",
 480                             thread->readMiscRegNoEffect(MISCREG_ASI),
 481                             shared_data->asi);
 482                     printRegPair(outs, "Pil",
 483                             thread->readMiscRegNoEffect(MISCREG_PIL),
 484                             shared_data->pil);
 485                     printRegPair(outs, "Cwp",
 486                             thread->readMiscRegNoEffect(MISCREG_CWP),
 487                             shared_data->cwp);
 488                     printRegPair(outs, "Cansave",
 489                             //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
 490                             thread->readIntReg(NumIntArchRegs + 3),
 491                             shared_data->cansave);
 492                     printRegPair(outs, "Canrestore",
 493                             //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
 494                             thread->readIntReg(NumIntArchRegs + 4),
 495                             shared_data->canrestore);
 496                     printRegPair(outs, "Otherwin",
 497                             //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
 498                             thread->readIntReg(NumIntArchRegs + 6),
 499                             shared_data->otherwin);
 500                     printRegPair(outs, "Cleanwin",
 501                             //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
 502                             thread->readIntReg(NumIntArchRegs + 5),
 503                             shared_data->cleanwin);
 504                     outs << endl;
 505                     for (int i = 1; i <= MaxTL; i++) {
 506                         printLevelHeader(outs, i);
 507                         printColumnLabels(outs);
 508                         thread->setMiscRegNoEffect(MISCREG_TL, i);
 509                         printRegPair(outs, "Tpc",
 510                                 thread->readMiscRegNoEffect(MISCREG_TPC),
 511                                 shared_data->tpc[i-1]);
 512                         printRegPair(outs, "Tnpc",
 513                                 thread->readMiscRegNoEffect(MISCREG_TNPC),
 514                                 shared_data->tnpc[i-1]);
 515                         printRegPair(outs, "Tstate",
 516                                 thread->readMiscRegNoEffect(MISCREG_TSTATE),
 517                                 shared_data->tstate[i-1]);
 518                         printRegPair(outs, "Tt",
 519                                 thread->readMiscRegNoEffect(MISCREG_TT),
 520                                 shared_data->tt[i-1]);
 521                         printRegPair(outs, "Htstate",
 522                                 thread->readMiscRegNoEffect(MISCREG_HTSTATE),
 523                                 shared_data->htstate[i-1]);
 524                     }
 525                     thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 526                     outs << endl;
 527
 528                     printSectionHeader(outs, "General Purpose Registers");
 529                     static const char * regtypes[4] =
 530                         {"%g", "%o", "%l", "%i"};
 531                     for(int y = 0; y < 4; y++) {
 532                         for(int x = 0; x < 8; x++) {
 533                             char label[8];
 534                             sprintf(label, "%s%d", regtypes[y], x);
 535                             printRegPair(outs, label,
 536                                     thread->readIntReg(y*8+x),
 537                                     shared_data->intregs[y*8+x]);
 538                         }
 539                     }
 540                     if (diffFpRegs) {
 541                         for (int x = 0; x < 32; x++) {
 542                             char label[8];
 543                             sprintf(label, "%%f%d", x);
 544                             printRegPair(outs, label,
 545                                 thread->readFloatRegBits(x*2),
 546                                 shared_data->fpregs[x]);
 547                         }
 548                     }
 549                     if (diffTlb) {
 550                         printColumnLabels(outs);
 551                         char label[8];
 552                         for (int x = 0; x < 64; x++) {
 553                             if (shared_data->itb[x] !=
 554                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 555                                 thread->getITBPtr()->TteRead(x) !=
 556                                 ULL(0xFFFFFFFFFFFFFFFF)) {
 557                                     sprintf(label, "I-TLB:%02d", x);
 558                                     printRegPair(outs, label,
 559                                             thread->getITBPtr()->TteRead(x),
 560                                             shared_data->itb[x]);
 561                             }
 562                         }
 563                         for (int x = 0; x < 64; x++) {
 564                             if (shared_data->dtb[x] !=
 565                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 566                                 thread->getDTBPtr()->TteRead(x) !=
 567                                 ULL(0xFFFFFFFFFFFFFFFF))  {
 568                                     sprintf(label, "D-TLB:%02d", x);
 569                                     printRegPair(outs, label,
 570                                             thread->getDTBPtr()->TteRead(x),
 571                                             shared_data->dtb[x]);
 572                             }
 573                         }
 574                         thread->getITBPtr()->dumpAll();
 575                         thread->getDTBPtr()->dumpAll();
 576                     }
 577
 578                     diffcount++;
 579                     if (diffcount > 3)
 580                         fatal("Differences found between Legion and M5\n");
 581                 } else
 582                     diffcount = 0;
 583
 584                 compared = true;
 585                 shared_data->flags = OWN_LEGION;
 586             }
 587         } // while
 588     } // if not microop
 589 }
 590
 591 } // namespace Trace
 592
 593 ////////////////////////////////////////////////////////////////////////
 594 //
 595 //  ExeTracer Simulation Object
 596 //
 597 Trace::LegionTrace *
 598 LegionTraceParams::create()
 599 {
 600     return new Trace::LegionTrace(this);
 601 };