src/cpu/legiontrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include "config/the_isa.hh"
  35 #if THE_ISA != SPARC_ISA
  36     #error Legion tracing only works with SPARC simulations!
  37 #endif
  38
  39 #include <sys/ipc.h>
  40 #include <sys/shm.h>
  41
  42 #include <cstdio>
  43 #include <iomanip>
  44
  45 #include "arch/sparc/predecoder.hh"
  46 #include "arch/sparc/registers.hh"
  47 #include "arch/sparc/utility.hh"
  48 #include "arch/tlb.hh"
  49 #include "base/socket.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/decode.hh"
  52 #include "cpu/legiontrace.hh"
  53 #include "cpu/static_inst.hh"
  54 #include "cpu/thread_context.hh"
  55 #include "sim/full_system.hh"
  56 #include "sim/system.hh"
  57
  58 //XXX This is temporary
  59 #include "cpu/m5legion_interface.h"
  60
  61 using namespace std;
  62 using namespace TheISA;
  63
  64 static int diffcount = 0;
  65 static bool wasMicro = false;
  66
  67 namespace Trace {
  68 SharedData *shared_data = NULL;
  69
  70 void
  71 setupSharedData()
  72 {
  73     int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
  74     if (shmfd < 0)
  75         fatal("Couldn't get shared memory fd. Is Legion running?");
  76
  77     shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
  78     if (shared_data == (SharedData*)-1)
  79         fatal("Couldn't allocate shared memory");
  80
  81     if (shared_data->flags != OWN_M5)
  82         fatal("Shared memory has invalid owner");
  83
  84     if (shared_data->version != VERSION)
  85         fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
  86               shared_data->version);
  87
  88     // step legion forward one cycle so we can get register values
  89     shared_data->flags = OWN_LEGION;
  90 }
  91
  92 ////////////////////////////////////////////////////////////////////////
  93 //
  94 //  Utility methods for pretty printing a report about a difference
  95 //
  96
  97 inline char * genCenteredLabel(int length, char * buffer, const char * label)
  98 {
  99     int labelLength = strlen(label);
 100     assert(labelLength <= length);
 101     int leftPad = (length - labelLength) / 2;
 102     int rightPad = length - leftPad - labelLength;
 103     char format[64];
 104     sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
 105     sprintf(buffer, format, "", label, "");
 106     return buffer;
 107 }
 108
 109 inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
 110 {
 111     ccprintf(os, "  %16s  |  %#018x   %s   %#-018x  \n",
 112             title, a, (a == b) ? "|" : "X", b);
 113 }
 114
 115 inline void printColumnLabels(ostream & os)
 116 {
 117     static char * regLabel = genCenteredLabel(16, new char[17], "Register");
 118     static char * m5Label = genCenteredLabel(18, new char[18], "M5");
 119     static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
 120     ccprintf(os, "  %s  |  %s   |   %s  \n", regLabel, m5Label, legionLabel);
 121     ccprintf(os, "--------------------+-----------------------+-----------------------\n");
 122 }
 123
 124 inline void printSectionHeader(ostream & os, const char * name)
 125 {
 126     char sectionString[70];
 127     genCenteredLabel(69, sectionString, name);
 128     ccprintf(os, "====================================================================\n");
 129     ccprintf(os, "%69s\n", sectionString);
 130     ccprintf(os, "====================================================================\n");
 131 }
 132
 133 inline void printLevelHeader(ostream & os, int level)
 134 {
 135     char sectionString[70];
 136     char levelName[70];
 137     sprintf(levelName, "Trap stack level %d", level);
 138     genCenteredLabel(69, sectionString, levelName);
 139     ccprintf(os, "====================================================================\n");
 140     ccprintf(os, "%69s\n", sectionString);
 141     ccprintf(os, "====================================================================\n");
 142 }
 143
 144 void
 145 Trace::LegionTraceRecord::dump()
 146 {
 147     ostream &outs = Trace::output();
 148
 149     static TheISA::Predecoder predecoder(NULL);
 150     // Compare
 151     bool compared = false;
 152     bool diffPC   = false;
 153     bool diffCC   = false;
 154     bool diffInst = false;
 155     bool diffIntRegs = false;
 156     bool diffFpRegs = false;
 157     bool diffTpc = false;
 158     bool diffTnpc = false;
 159     bool diffTstate = false;
 160     bool diffTt = false;
 161     bool diffTba M5_VAR_USED = false;
 162     bool diffHpstate = false;
 163     bool diffHtstate = false;
 164     bool diffHtba = false;
 165     bool diffPstate = false;
 166     bool diffY = false;
 167     bool diffFsr = false;
 168     bool diffCcr = false;
 169     bool diffTl = false;
 170     bool diffGl = false;
 171     bool diffAsi = false;
 172     bool diffPil = false;
 173     bool diffCwp = false;
 174     bool diffCansave = false;
 175     bool diffCanrestore = false;
 176     bool diffOtherwin = false;
 177     bool diffCleanwin = false;
 178     bool diffTlb = false;
 179     Addr m5Pc, lgnPc;
 180
 181     if (!shared_data)
 182         setupSharedData();
 183
 184     // We took a trap on a micro-op...
 185     if (wasMicro && !staticInst->isMicroop())
 186     {
 187         // let's skip comparing this tick
 188         while (!compared)
 189             if (shared_data->flags == OWN_M5) {
 190                 shared_data->flags = OWN_LEGION;
 191                 compared = true;
 192             }
 193         compared = false;
 194         wasMicro = false;
 195     }
 196
 197     if (staticInst->isLastMicroop())
 198         wasMicro = false;
 199     else if (staticInst->isMicroop())
 200         wasMicro = true;
 201
 202
 203     if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
 204         while (!compared) {
 205             if (shared_data->flags == OWN_M5) {
 206                 m5Pc = pc.instAddr() & SparcISA::PAddrImplMask;
 207                 if (bits(shared_data->pstate,3,3)) {
 208                     m5Pc &= mask(32);
 209                 }
 210                 lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
 211                 if (lgnPc != m5Pc)
 212                    diffPC = true;
 213
 214                 if (shared_data->cycle_count !=
 215                         thread->getCpuPtr()->instCount())
 216                     diffCC = true;
 217
 218                 if (shared_data->instruction !=
 219                         (SparcISA::MachInst)staticInst->machInst) {
 220                     diffInst = true;
 221                 }
 222                 // assume we have %g0 working correctly
 223                 for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
 224                     if (thread->readIntReg(i) != shared_data->intregs[i]) {
 225                         diffIntRegs = true;
 226                     }
 227                 }
 228                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
 229                     if (thread->readFloatRegBits(i*2) !=
 230                             shared_data->fpregs[i]) {
 231                         diffFpRegs = true;
 232                     }
 233                 }
 234                         uint64_t oldTl =
 235                             thread->readMiscRegNoEffect(MISCREG_TL);
 236                 if (oldTl != shared_data->tl)
 237                     diffTl = true;
 238                 for (int i = 1; i <= MaxTL; i++) {
 239                     thread->setMiscRegNoEffect(MISCREG_TL, i);
 240                     if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
 241                             shared_data->tpc[i-1])
 242                         diffTpc = true;
 243                     if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
 244                             shared_data->tnpc[i-1])
 245                         diffTnpc = true;
 246                     if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
 247                             shared_data->tstate[i-1])
 248                         diffTstate = true;
 249                     if (thread->readMiscRegNoEffect(MISCREG_TT) !=
 250                             shared_data->tt[i-1])
 251                         diffTt = true;
 252                     if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
 253                             shared_data->htstate[i-1])
 254                         diffHtstate = true;
 255                 }
 256                 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 257
 258                 if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
 259                     diffTba = true;
 260                 //When the hpstate register is read by an instruction,
 261                 //legion has bit 11 set. When it's in storage, it doesn't.
 262                 //Since we don't directly support seperate interpretations
 263                 //of the registers like that, the bit is always set to 1 and
 264                 //we just don't compare it. It's not supposed to matter
 265                 //anyway.
 266                 if((shared_data->hpstate | (1 << 11)) !=
 267                         thread->readMiscRegNoEffect(MISCREG_HPSTATE))
 268                     diffHpstate = true;
 269                 if(shared_data->htba !=
 270                         thread->readMiscRegNoEffect(MISCREG_HTBA))
 271                     diffHtba = true;
 272                 if(shared_data->pstate !=
 273                         thread->readMiscRegNoEffect(MISCREG_PSTATE))
 274                     diffPstate = true;
 275                 //if(shared_data->y !=
 276                 //        thread->readMiscRegNoEffect(MISCREG_Y))
 277                 if(shared_data->y !=
 278                         thread->readIntReg(NumIntArchRegs + 1))
 279                     diffY = true;
 280                 if(shared_data->fsr !=
 281                         thread->readMiscRegNoEffect(MISCREG_FSR)) {
 282                     diffFsr = true;
 283                     if (mbits(shared_data->fsr, 63,10) ==
 284                             mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
 285                                 63,10)) {
 286                         thread->setMiscRegNoEffect(MISCREG_FSR,
 287                                 shared_data->fsr);
 288                         diffFsr = false;
 289                     }
 290                 }
 291                 //if(shared_data->ccr !=
 292                 //        thread->readMiscRegNoEffect(MISCREG_CCR))
 293                 if(shared_data->ccr !=
 294                         thread->readIntReg(NumIntArchRegs + 2))
 295                     diffCcr = true;
 296                 if(shared_data->gl !=
 297                         thread->readMiscRegNoEffect(MISCREG_GL))
 298                     diffGl = true;
 299                 if(shared_data->asi !=
 300                         thread->readMiscRegNoEffect(MISCREG_ASI))
 301                     diffAsi = true;
 302                 if(shared_data->pil !=
 303                         thread->readMiscRegNoEffect(MISCREG_PIL))
 304                     diffPil = true;
 305                 if(shared_data->cwp !=
 306                         thread->readMiscRegNoEffect(MISCREG_CWP))
 307                     diffCwp = true;
 308                 //if(shared_data->cansave !=
 309                 //        thread->readMiscRegNoEffect(MISCREG_CANSAVE))
 310                 if(shared_data->cansave !=
 311                         thread->readIntReg(NumIntArchRegs + 3))
 312                     diffCansave = true;
 313                 //if(shared_data->canrestore !=
 314                 //        thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
 315                 if(shared_data->canrestore !=
 316                         thread->readIntReg(NumIntArchRegs + 4))
 317                     diffCanrestore = true;
 318                 //if(shared_data->otherwin !=
 319                 //        thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
 320                 if(shared_data->otherwin !=
 321                         thread->readIntReg(NumIntArchRegs + 6))
 322                     diffOtherwin = true;
 323                 //if(shared_data->cleanwin !=
 324                 //        thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
 325                 if(shared_data->cleanwin !=
 326                         thread->readIntReg(NumIntArchRegs + 5))
 327                     diffCleanwin = true;
 328
 329                 for (int i = 0; i < 64; i++) {
 330                     if (shared_data->itb[i] !=
 331                             thread->getITBPtr()->TteRead(i))
 332                         diffTlb = true;
 333                     if (shared_data->dtb[i] !=
 334                             thread->getDTBPtr()->TteRead(i))
 335                         diffTlb = true;
 336                 }
 337
 338                 if (diffPC || diffCC || diffInst ||
 339                     diffIntRegs || diffFpRegs ||
 340                     diffTpc || diffTnpc || diffTstate || diffTt ||
 341                     diffHpstate || diffHtstate || diffHtba ||
 342                     diffPstate || diffY || diffCcr || diffTl || diffFsr ||
 343                     diffGl || diffAsi || diffPil || diffCwp ||
 344                     diffCansave || diffCanrestore ||
 345                     diffOtherwin || diffCleanwin || diffTlb) {
 346
 347                     outs << "Differences found between M5 and Legion:";
 348                     if (diffPC)
 349                         outs << " [PC]";
 350                     if (diffCC)
 351                         outs << " [CC]";
 352                     if (diffInst)
 353                         outs << " [Instruction]";
 354                     if (diffIntRegs)
 355                         outs << " [IntRegs]";
 356                     if (diffFpRegs)
 357                         outs << " [FpRegs]";
 358                     if (diffTpc)
 359                         outs << " [Tpc]";
 360                     if (diffTnpc)
 361                         outs << " [Tnpc]";
 362                     if (diffTstate)
 363                         outs << " [Tstate]";
 364                     if (diffTt)
 365                         outs << " [Tt]";
 366                     if (diffHpstate)
 367                         outs << " [Hpstate]";
 368                     if (diffHtstate)
 369                         outs << " [Htstate]";
 370                     if (diffHtba)
 371                         outs << " [Htba]";
 372                     if (diffPstate)
 373                         outs << " [Pstate]";
 374                     if (diffY)
 375                         outs << " [Y]";
 376                     if (diffFsr)
 377                         outs << " [FSR]";
 378                     if (diffCcr)
 379                         outs << " [Ccr]";
 380                     if (diffTl)
 381                         outs << " [Tl]";
 382                     if (diffGl)
 383                         outs << " [Gl]";
 384                     if (diffAsi)
 385                         outs << " [Asi]";
 386                     if (diffPil)
 387                         outs << " [Pil]";
 388                     if (diffCwp)
 389                         outs << " [Cwp]";
 390                     if (diffCansave)
 391                         outs << " [Cansave]";
 392                     if (diffCanrestore)
 393                         outs << " [Canrestore]";
 394                     if (diffOtherwin)
 395                         outs << " [Otherwin]";
 396                     if (diffCleanwin)
 397                         outs << " [Cleanwin]";
 398                     if (diffTlb)
 399                         outs << " [Tlb]";
 400                     outs << endl << endl;
 401
 402                     outs << right << setfill(' ') << setw(15)
 403                          << "M5 PC: " << "0x"<< setw(16) << setfill('0')
 404                          << hex << m5Pc << endl;
 405                     outs << setfill(' ') << setw(15)
 406                          << "Legion PC: " << "0x"
 407                          << setw(16) << setfill('0') << hex
 408                          << lgnPc << endl << endl;
 409
 410                     outs << right << setfill(' ') << setw(15)
 411                          << "M5 CC: " << "0x"
 412                          << setw(16) << setfill('0') << hex
 413                          << thread->getCpuPtr()->instCount() << endl;
 414                     outs << setfill(' ') << setw(15)
 415                          << "Legion CC: " << "0x"
 416                          << setw(16) << setfill('0') << hex
 417                          << shared_data->cycle_count << endl << endl;
 418
 419                     outs << setfill(' ') << setw(15)
 420                          << "M5 Inst: " << "0x"
 421                          << setw(8) << setfill('0') << hex
 422                          << staticInst->machInst
 423                          << staticInst->disassemble(m5Pc, debugSymbolTable)
 424                          << endl;
 425
 426                     predecoder.setTC(thread);
 427                     predecoder.moreBytes(m5Pc, m5Pc, shared_data->instruction);
 428
 429                     assert(predecoder.extMachInstReady());
 430
 431                     PCState tempPC = pc;
 432                     StaticInstPtr legionInst =
 433                         thread->getDecoderPtr()->decode(
 434                                 predecoder.getExtMachInst(tempPC), lgnPc);
 435                     outs << setfill(' ') << setw(15)
 436                          << " Legion Inst: "
 437                          << "0x" << setw(8) << setfill('0') << hex
 438                          << shared_data->instruction
 439                          << legionInst->disassemble(lgnPc, debugSymbolTable)
 440                          << endl << endl;
 441
 442                     printSectionHeader(outs, "General State");
 443                     printColumnLabels(outs);
 444                     printRegPair(outs, "HPstate",
 445                             thread->readMiscRegNoEffect(MISCREG_HPSTATE),
 446                             shared_data->hpstate | (1 << 11));
 447                     printRegPair(outs, "Htba",
 448                             thread->readMiscRegNoEffect(MISCREG_HTBA),
 449                             shared_data->htba);
 450                     printRegPair(outs, "Pstate",
 451                             thread->readMiscRegNoEffect(MISCREG_PSTATE),
 452                             shared_data->pstate);
 453                     printRegPair(outs, "Y",
 454                             //thread->readMiscRegNoEffect(MISCREG_Y),
 455                             thread->readIntReg(NumIntArchRegs + 1),
 456                             shared_data->y);
 457                     printRegPair(outs, "FSR",
 458                             thread->readMiscRegNoEffect(MISCREG_FSR),
 459                             shared_data->fsr);
 460                     printRegPair(outs, "Ccr",
 461                             //thread->readMiscRegNoEffect(MISCREG_CCR),
 462                             thread->readIntReg(NumIntArchRegs + 2),
 463                             shared_data->ccr);
 464                     printRegPair(outs, "Tl",
 465                             thread->readMiscRegNoEffect(MISCREG_TL),
 466                             shared_data->tl);
 467                     printRegPair(outs, "Gl",
 468                             thread->readMiscRegNoEffect(MISCREG_GL),
 469                             shared_data->gl);
 470                     printRegPair(outs, "Asi",
 471                             thread->readMiscRegNoEffect(MISCREG_ASI),
 472                             shared_data->asi);
 473                     printRegPair(outs, "Pil",
 474                             thread->readMiscRegNoEffect(MISCREG_PIL),
 475                             shared_data->pil);
 476                     printRegPair(outs, "Cwp",
 477                             thread->readMiscRegNoEffect(MISCREG_CWP),
 478                             shared_data->cwp);
 479                     printRegPair(outs, "Cansave",
 480                             //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
 481                             thread->readIntReg(NumIntArchRegs + 3),
 482                             shared_data->cansave);
 483                     printRegPair(outs, "Canrestore",
 484                             //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
 485                             thread->readIntReg(NumIntArchRegs + 4),
 486                             shared_data->canrestore);
 487                     printRegPair(outs, "Otherwin",
 488                             //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
 489                             thread->readIntReg(NumIntArchRegs + 6),
 490                             shared_data->otherwin);
 491                     printRegPair(outs, "Cleanwin",
 492                             //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
 493                             thread->readIntReg(NumIntArchRegs + 5),
 494                             shared_data->cleanwin);
 495                     outs << endl;
 496                     for (int i = 1; i <= MaxTL; i++) {
 497                         printLevelHeader(outs, i);
 498                         printColumnLabels(outs);
 499                         thread->setMiscRegNoEffect(MISCREG_TL, i);
 500                         printRegPair(outs, "Tpc",
 501                                 thread->readMiscRegNoEffect(MISCREG_TPC),
 502                                 shared_data->tpc[i-1]);
 503                         printRegPair(outs, "Tnpc",
 504                                 thread->readMiscRegNoEffect(MISCREG_TNPC),
 505                                 shared_data->tnpc[i-1]);
 506                         printRegPair(outs, "Tstate",
 507                                 thread->readMiscRegNoEffect(MISCREG_TSTATE),
 508                                 shared_data->tstate[i-1]);
 509                         printRegPair(outs, "Tt",
 510                                 thread->readMiscRegNoEffect(MISCREG_TT),
 511                                 shared_data->tt[i-1]);
 512                         printRegPair(outs, "Htstate",
 513                                 thread->readMiscRegNoEffect(MISCREG_HTSTATE),
 514                                 shared_data->htstate[i-1]);
 515                     }
 516                     thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 517                     outs << endl;
 518
 519                     printSectionHeader(outs, "General Purpose Registers");
 520                     static const char * regtypes[4] =
 521                         {"%g", "%o", "%l", "%i"};
 522                     for(int y = 0; y < 4; y++) {
 523                         for(int x = 0; x < 8; x++) {
 524                             char label[8];
 525                             sprintf(label, "%s%d", regtypes[y], x);
 526                             printRegPair(outs, label,
 527                                     thread->readIntReg(y*8+x),
 528                                     shared_data->intregs[y*8+x]);
 529                         }
 530                     }
 531                     if (diffFpRegs) {
 532                         for (int x = 0; x < 32; x++) {
 533                             char label[8];
 534                             sprintf(label, "%%f%d", x);
 535                             printRegPair(outs, label,
 536                                 thread->readFloatRegBits(x*2),
 537                                 shared_data->fpregs[x]);
 538                         }
 539                     }
 540                     if (diffTlb) {
 541                         printColumnLabels(outs);
 542                         char label[8];
 543                         for (int x = 0; x < 64; x++) {
 544                             if (shared_data->itb[x] !=
 545                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 546                                 thread->getITBPtr()->TteRead(x) !=
 547                                 ULL(0xFFFFFFFFFFFFFFFF)) {
 548                                     sprintf(label, "I-TLB:%02d", x);
 549                                     printRegPair(outs, label,
 550                                             thread->getITBPtr()->TteRead(x),
 551                                             shared_data->itb[x]);
 552                             }
 553                         }
 554                         for (int x = 0; x < 64; x++) {
 555                             if (shared_data->dtb[x] !=
 556                                     ULL(0xFFFFFFFFFFFFFFFF) ||
 557                                 thread->getDTBPtr()->TteRead(x) !=
 558                                 ULL(0xFFFFFFFFFFFFFFFF))  {
 559                                     sprintf(label, "D-TLB:%02d", x);
 560                                     printRegPair(outs, label,
 561                                             thread->getDTBPtr()->TteRead(x),
 562                                             shared_data->dtb[x]);
 563                             }
 564                         }
 565                         thread->getITBPtr()->dumpAll();
 566                         thread->getDTBPtr()->dumpAll();
 567                     }
 568
 569                     diffcount++;
 570                     if (diffcount > 3)
 571                         fatal("Differences found between Legion and M5\n");
 572                 } else
 573                     diffcount = 0;
 574
 575                 compared = true;
 576                 shared_data->flags = OWN_LEGION;
 577             }
 578         } // while
 579     } // if not microop
 580 }
 581
 582 } // namespace Trace
 583
 584 ////////////////////////////////////////////////////////////////////////
 585 //
 586 //  ExeTracer Simulation Object
 587 //
 588 Trace::LegionTrace *
 589 LegionTraceParams::create()
 590 {
 591     if (!FullSystem)
 592         panic("Legion tracing only works in full system!");
 593     return new Trace::LegionTrace(this);
 594 };