src/cpu/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  */
  31
  32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  33
  34 #include <iomanip>
  35 #include <set>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/misc.hh"
  40 #include "base/statistics.hh"
  41 //#include "cpu/simple_thread.hh"
  42 #include "cpu/memtest/memtest.hh"
  43 //#include "mem/cache/base_cache.hh"
  44 //#include "mem/physical.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/sim_events.hh"
  47 #include "sim/stats.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/request.hh"
  50 #include "mem/port.hh"
  51 #include "mem/mem_object.hh"
  52
  53 using namespace std;
  54
  55 int TESTER_ALLOCATOR=0;
  56
  57 bool
  58 MemTest::CpuPort::recvTiming(Packet *pkt)
  59 {
  60     memtest->completeRequest(pkt);
  61     return true;
  62 }
  63
  64 Tick
  65 MemTest::CpuPort::recvAtomic(Packet *pkt)
  66 {
  67     panic("MemTest doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 void
  72 MemTest::CpuPort::recvFunctional(Packet *pkt)
  73 {
  74     memtest->completeRequest(pkt);
  75 }
  76
  77 void
  78 MemTest::CpuPort::recvStatusChange(Status status)
  79 {
  80     if (status == RangeChange)
  81         return;
  82
  83     panic("MemTest doesn't expect recvStatusChange callback!");
  84 }
  85
  86 void
  87 MemTest::CpuPort::recvRetry()
  88 {
  89     memtest->doRetry();
  90 }
  91
  92 MemTest::MemTest(const string &name,
  93 //               MemInterface *_cache_interface,
  94 //               PhysicalMemory *main_mem,
  95 //               PhysicalMemory *check_mem,
  96                  unsigned _memorySize,
  97                  unsigned _percentReads,
  98 //               unsigned _percentCopies,
  99                  unsigned _percentUncacheable,
 100                  unsigned _progressInterval,
 101                  unsigned _percentSourceUnaligned,
 102                  unsigned _percentDestUnaligned,
 103                  Addr _traceAddr,
 104                  Counter _max_loads)
 105     : MemObject(name),
 106       tickEvent(this),
 107       cachePort("test", this),
 108       funcPort("functional", this),
 109       retryPkt(NULL),
 110 //      mainMem(main_mem),
 111 //      checkMem(check_mem),
 112       size(_memorySize),
 113       percentReads(_percentReads),
 114 //      percentCopies(_percentCopies),
 115       percentUncacheable(_percentUncacheable),
 116       progressInterval(_progressInterval),
 117       nextProgressMessage(_progressInterval),
 118       percentSourceUnaligned(_percentSourceUnaligned),
 119       percentDestUnaligned(percentDestUnaligned),
 120       maxLoads(_max_loads)
 121 {
 122     vector<string> cmd;
 123     cmd.push_back("/bin/ls");
 124     vector<string> null_vec;
 125     //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
 126     curTick = 0;
 127
 128     // Needs to be masked off once we know the block size.
 129     traceBlockAddr = _traceAddr;
 130     baseAddr1 = 0x100000;
 131     baseAddr2 = 0x400000;
 132     uncacheAddr = 0x800000;
 133
 134     // set up counters
 135     noResponseCycles = 0;
 136     numReads = 0;
 137     tickEvent.schedule(0);
 138
 139     id = TESTER_ALLOCATOR++;
 140     if (TESTER_ALLOCATOR > 8)
 141         panic("False sharing memtester only allows up to 8 testers");
 142
 143     accessRetry = false;
 144 }
 145
 146 Port *
 147 MemTest::getPort(const std::string &if_name, int idx)
 148 {
 149     if (if_name == "functional")
 150         return &funcPort;
 151     else if (if_name == "test")
 152         return &cachePort;
 153     else
 154         panic("No Such Port\n");
 155 }
 156
 157 void
 158 MemTest::init()
 159 {
 160     // By the time init() is called, the ports should be hooked up.
 161     blockSize = cachePort.peerBlockSize();
 162     blockAddrMask = blockSize - 1;
 163     traceBlockAddr = blockAddr(traceBlockAddr);
 164
 165     // set up intial memory contents here
 166
 167     cachePort.memsetBlob(baseAddr1, 1, size);
 168     funcPort.memsetBlob(baseAddr1, 1, size);
 169     cachePort.memsetBlob(baseAddr2, 2, size);
 170     funcPort.memsetBlob(baseAddr2, 2, size);
 171     cachePort.memsetBlob(uncacheAddr, 3, size);
 172     funcPort.memsetBlob(uncacheAddr, 3, size);
 173 }
 174
 175 static void
 176 printData(ostream &os, uint8_t *data, int nbytes)
 177 {
 178     os << hex << setfill('0');
 179     // assume little-endian: print bytes from highest address to lowest
 180     for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
 181         os << setw(2) << (unsigned)*dp;
 182     }
 183     os << dec;
 184 }
 185
 186 void
 187 MemTest::completeRequest(Packet *pkt)
 188 {
 189     MemTestSenderState *state =
 190         dynamic_cast<MemTestSenderState *>(pkt->senderState);
 191
 192     uint8_t *data = state->data;
 193     uint8_t *pkt_data = pkt->getPtr<uint8_t>();
 194     Request *req = pkt->req;
 195
 196     //Remove the address from the list of outstanding
 197     std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
 198     assert(removeAddr != outstandingAddrs.end());
 199     outstandingAddrs.erase(removeAddr);
 200
 201     switch (pkt->cmd) {
 202       case Packet::ReadResp:
 203
 204         if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
 205             cerr << name() << ": on read of 0x" << hex << req->getPaddr()
 206                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 207                  << "@ cycle " << dec << curTick
 208                  << ", cache returns 0x";
 209             printData(cerr, pkt_data, pkt->getSize());
 210             cerr << ", expected 0x";
 211             printData(cerr, data, pkt->getSize());
 212             cerr << endl;
 213             fatal("");
 214         }
 215
 216         numReads++;
 217         numReadsStat++;
 218
 219         if (numReads == nextProgressMessage) {
 220             ccprintf(cerr, "%s: completed %d read accesses @%d\n",
 221                      name(), numReads, curTick);
 222             nextProgressMessage += progressInterval;
 223         }
 224
 225         if (numReads >= maxLoads)
 226             exitSimLoop("Maximum number of loads reached!");
 227         break;
 228
 229       case Packet::WriteResp:
 230         numWritesStat++;
 231         break;
 232 /*
 233       case Copy:
 234         //Also remove dest from outstanding list
 235         removeAddr = outstandingAddrs.find(req->dest);
 236         assert(removeAddr != outstandingAddrs.end());
 237         outstandingAddrs.erase(removeAddr);
 238         numCopiesStat++;
 239         break;
 240 */
 241       default:
 242         panic("invalid command");
 243     }
 244
 245     if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 246         cerr << name() << ": completed "
 247              << (pkt->isWrite() ? "write" : "read")
 248              << " access of "
 249              << dec << pkt->getSize() << " bytes at address 0x"
 250              << hex << req->getPaddr()
 251              << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 252              << ", value = 0x";
 253         printData(cerr, pkt_data, pkt->getSize());
 254         cerr << " @ cycle " << dec << curTick;
 255
 256         cerr << endl;
 257     }
 258
 259     noResponseCycles = 0;
 260     delete state;
 261     delete [] data;
 262     delete pkt->req;
 263     delete pkt;
 264 }
 265
 266 void
 267 MemTest::regStats()
 268 {
 269     using namespace Stats;
 270
 271     numReadsStat
 272         .name(name() + ".num_reads")
 273         .desc("number of read accesses completed")
 274         ;
 275
 276     numWritesStat
 277         .name(name() + ".num_writes")
 278         .desc("number of write accesses completed")
 279         ;
 280
 281     numCopiesStat
 282         .name(name() + ".num_copies")
 283         .desc("number of copy accesses completed")
 284         ;
 285 }
 286
 287 void
 288 MemTest::tick()
 289 {
 290     if (!tickEvent.scheduled())
 291         tickEvent.schedule(curTick + cycles(1));
 292
 293     if (++noResponseCycles >= 500000) {
 294         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 295         fatal("");
 296     }
 297
 298     if (accessRetry) {
 299         return;
 300     }
 301
 302     //make new request
 303     unsigned cmd = random() % 100;
 304     unsigned offset = random() % size;
 305     unsigned base = random() % 2;
 306     uint64_t data = random();
 307     unsigned access_size = random() % 4;
 308     unsigned cacheable = random() % 100;
 309
 310     //If we aren't doing copies, use id as offset, and do a false sharing
 311     //mem tester
 312     //We can eliminate the lower bits of the offset, and then use the id
 313     //to offset within the blks
 314     offset &= ~63; //Not the low order bits
 315     offset += id;
 316     access_size = 0;
 317
 318     Request *req = new Request();
 319     uint32_t flags = 0;
 320     Addr paddr;
 321
 322     if (cacheable < percentUncacheable) {
 323         flags |= UNCACHEABLE;
 324         paddr = uncacheAddr + offset;
 325     } else {
 326         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
 327     }
 328     // bool probe = (random() % 2 == 1) && !req->isUncacheable();
 329     bool probe = false;
 330
 331     paddr &= ~((1 << access_size) - 1);
 332     req->setPhys(paddr, 1 << access_size, flags);
 333     req->setThreadContext(id,0);
 334
 335     uint8_t *result = new uint8_t[8];
 336
 337     if (cmd < percentReads) {
 338         // read
 339
 340         //For now we only allow one outstanding request per addreess per tester
 341         //This means we assume CPU does write forwarding to reads that alias something
 342         //in the cpu store buffer.
 343         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 344         else outstandingAddrs.insert(paddr);
 345
 346         // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
 347         funcPort.readBlob(req->getPaddr(), result, req->getSize());
 348
 349         if (blockAddr(paddr) == traceBlockAddr) {
 350             cerr << name()
 351                  << ": initiating read "
 352                  << ((probe) ? "probe of " : "access of ")
 353                  << dec << req->getSize() << " bytes from addr 0x"
 354                  << hex << paddr
 355                  << " (0x" << hex << blockAddr(paddr) << ")"
 356                  << " at cycle "
 357                  << dec << curTick << endl;
 358         }
 359
 360         Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
 361         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
 362         MemTestSenderState *state = new MemTestSenderState(result);
 363         pkt->senderState = state;
 364
 365         if (probe) {
 366             cachePort.sendFunctional(pkt);
 367 //          completeRequest(pkt, result);
 368         } else {
 369 //          req->completionEvent = new MemCompleteEvent(req, result, this);
 370             if (!cachePort.sendTiming(pkt)) {
 371                 accessRetry = true;
 372                 retryPkt = pkt;
 373             }
 374         }
 375     } else {
 376         // write
 377
 378         //For now we only allow one outstanding request per addreess per tester
 379         //This means we assume CPU does write forwarding to reads that alias something
 380         //in the cpu store buffer.
 381         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 382         else outstandingAddrs.insert(paddr);
 383
 384 /*
 385         if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 386             cerr << name() << ": initiating write "
 387                  << ((probe)?"probe of ":"access of ")
 388                  << dec << req->getSize() << " bytes (value = 0x";
 389             printData(cerr, data_pkt->getPtr(), req->getSize());
 390             cerr << ") to addr 0x"
 391                  << hex << req->getPaddr()
 392                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 393                  << " at cycle "
 394                  << dec << curTick << endl;
 395         }
 396 */
 397         Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 398         uint8_t *pkt_data = new uint8_t[req->getSize()];
 399         pkt->dataDynamicArray(pkt_data);
 400         memcpy(pkt_data, &data, req->getSize());
 401         MemTestSenderState *state = new MemTestSenderState(result);
 402         pkt->senderState = state;
 403
 404         funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
 405
 406         if (probe) {
 407             cachePort.sendFunctional(pkt);
 408 //          completeRequest(req, NULL);
 409         } else {
 410 //          req->completionEvent = new MemCompleteEvent(req, NULL, this);
 411             if (!cachePort.sendTiming(pkt)) {
 412                 accessRetry = true;
 413                 retryPkt = pkt;
 414             }
 415         }
 416     }
 417 /*    else {
 418         // copy
 419         unsigned source_align = random() % 100;
 420         unsigned dest_align = random() % 100;
 421         unsigned offset2 = random() % size;
 422
 423         Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
 424         Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
 425         if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
 426         else outstandingAddrs.insert(source);
 427         if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
 428         else outstandingAddrs.insert(dest);
 429
 430         if (source_align >= percentSourceUnaligned) {
 431             source = blockAddr(source);
 432         }
 433         if (dest_align >= percentDestUnaligned) {
 434             dest = blockAddr(dest);
 435         }
 436         req->cmd = Copy;
 437         req->flags &= ~UNCACHEABLE;
 438         req->paddr = source;
 439         req->dest = dest;
 440         delete [] req->data;
 441         req->data = new uint8_t[blockSize];
 442         req->size = blockSize;
 443         if (source == traceBlockAddr || dest == traceBlockAddr) {
 444             cerr << name()
 445                  << ": initiating copy of "
 446                  << dec << req->size << " bytes from addr 0x"
 447                  << hex << source
 448                  << " (0x" << hex << blockAddr(source) << ")"
 449                  << " to addr 0x"
 450                  << hex << dest
 451                  << " (0x" << hex << blockAddr(dest) << ")"
 452                  << " at cycle "
 453                  << dec << curTick << endl;
 454         }*
 455         cacheInterface->access(req);
 456         uint8_t result[blockSize];
 457         checkMem->access(Read, source, &result, blockSize);
 458         checkMem->access(Write, dest, &result, blockSize);
 459     }
 460 */
 461 }
 462
 463 void
 464 MemTest::doRetry()
 465 {
 466     if (cachePort.sendTiming(retryPkt)) {
 467         accessRetry = false;
 468         retryPkt = NULL;
 469     }
 470 }
 471
 472 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 473
 474 //    SimObjectParam<BaseCache *> cache;
 475 //    SimObjectParam<PhysicalMemory *> main_mem;
 476 //    SimObjectParam<PhysicalMemory *> check_mem;
 477     Param<unsigned> memory_size;
 478     Param<unsigned> percent_reads;
 479 //    Param<unsigned> percent_copies;
 480     Param<unsigned> percent_uncacheable;
 481     Param<unsigned> progress_interval;
 482     Param<unsigned> percent_source_unaligned;
 483     Param<unsigned> percent_dest_unaligned;
 484     Param<Addr> trace_addr;
 485     Param<Counter> max_loads;
 486
 487 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 488
 489
 490 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 491
 492 //    INIT_PARAM(cache, "L1 cache"),
 493 //    INIT_PARAM(main_mem, "hierarchical memory"),
 494 //    INIT_PARAM(check_mem, "check memory"),
 495     INIT_PARAM(memory_size, "memory size"),
 496     INIT_PARAM(percent_reads, "target read percentage"),
 497 //    INIT_PARAM(percent_copies, "target copy percentage"),
 498     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
 499     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
 500     INIT_PARAM(percent_source_unaligned,
 501                "percent of copy source address that are unaligned"),
 502     INIT_PARAM(percent_dest_unaligned,
 503                "percent of copy dest address that are unaligned"),
 504     INIT_PARAM(trace_addr, "address to trace"),
 505     INIT_PARAM(max_loads, "terminate when we have reached this load count")
 506
 507 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 508
 509
 510 CREATE_SIM_OBJECT(MemTest)
 511 {
 512     return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
 513                        /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
 514                        percent_uncacheable, progress_interval,
 515                        percent_source_unaligned, percent_dest_unaligned,
 516                        trace_addr, max_loads);
 517 }
 518
 519 REGISTER_SIM_OBJECT("MemTest", MemTest)