src/cpu/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  */
  31
  32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  33
  34 #include <iomanip>
  35 #include <set>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/misc.hh"
  40 #include "base/statistics.hh"
  41 //#include "cpu/simple_thread.hh"
  42 #include "cpu/memtest/memtest.hh"
  43 //#include "mem/cache/base_cache.hh"
  44 //#include "mem/physical.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/sim_events.hh"
  47 #include "sim/stats.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/request.hh"
  50 #include "mem/port.hh"
  51 #include "mem/mem_object.hh"
  52
  53 using namespace std;
  54
  55 int TESTER_ALLOCATOR=0;
  56
  57 bool
  58 MemTest::CpuPort::recvTiming(Packet *pkt)
  59 {
  60     memtest->completeRequest(pkt);
  61     return true;
  62 }
  63
  64 Tick
  65 MemTest::CpuPort::recvAtomic(Packet *pkt)
  66 {
  67     panic("MemTest doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 void
  72 MemTest::CpuPort::recvFunctional(Packet *pkt)
  73 {
  74     //Do nothing if we see one come through
  75     return;
  76 }
  77
  78 void
  79 MemTest::CpuPort::recvStatusChange(Status status)
  80 {
  81     if (status == RangeChange)
  82         return;
  83
  84     panic("MemTest doesn't expect recvStatusChange callback!");
  85 }
  86
  87 void
  88 MemTest::CpuPort::recvRetry()
  89 {
  90     memtest->doRetry();
  91 }
  92
  93 MemTest::MemTest(const string &name,
  94 //               MemInterface *_cache_interface,
  95 //               PhysicalMemory *main_mem,
  96 //               PhysicalMemory *check_mem,
  97                  unsigned _memorySize,
  98                  unsigned _percentReads,
  99 //               unsigned _percentCopies,
 100                  unsigned _percentUncacheable,
 101                  unsigned _progressInterval,
 102                  unsigned _percentSourceUnaligned,
 103                  unsigned _percentDestUnaligned,
 104                  Addr _traceAddr,
 105                  Counter _max_loads)
 106     : MemObject(name),
 107       tickEvent(this),
 108       cachePort("test", this),
 109       funcPort("functional", this),
 110       retryPkt(NULL),
 111 //      mainMem(main_mem),
 112 //      checkMem(check_mem),
 113       size(_memorySize),
 114       percentReads(_percentReads),
 115 //      percentCopies(_percentCopies),
 116       percentUncacheable(_percentUncacheable),
 117       progressInterval(_progressInterval),
 118       nextProgressMessage(_progressInterval),
 119       percentSourceUnaligned(_percentSourceUnaligned),
 120       percentDestUnaligned(percentDestUnaligned),
 121       maxLoads(_max_loads)
 122 {
 123     vector<string> cmd;
 124     cmd.push_back("/bin/ls");
 125     vector<string> null_vec;
 126     //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
 127     curTick = 0;
 128
 129     // Needs to be masked off once we know the block size.
 130     traceBlockAddr = _traceAddr;
 131     baseAddr1 = 0x100000;
 132     baseAddr2 = 0x400000;
 133     uncacheAddr = 0x800000;
 134
 135     // set up counters
 136     noResponseCycles = 0;
 137     numReads = 0;
 138     tickEvent.schedule(0);
 139
 140     id = TESTER_ALLOCATOR++;
 141     if (TESTER_ALLOCATOR > 8)
 142         panic("False sharing memtester only allows up to 8 testers");
 143
 144     accessRetry = false;
 145 }
 146
 147 Port *
 148 MemTest::getPort(const std::string &if_name, int idx)
 149 {
 150     if (if_name == "functional")
 151         return &funcPort;
 152     else if (if_name == "test")
 153         return &cachePort;
 154     else
 155         panic("No Such Port\n");
 156 }
 157
 158 void
 159 MemTest::init()
 160 {
 161     // By the time init() is called, the ports should be hooked up.
 162     blockSize = cachePort.peerBlockSize();
 163     blockAddrMask = blockSize - 1;
 164     traceBlockAddr = blockAddr(traceBlockAddr);
 165
 166     // set up intial memory contents here
 167
 168     cachePort.memsetBlob(baseAddr1, 1, size);
 169     funcPort.memsetBlob(baseAddr1, 1, size);
 170     cachePort.memsetBlob(baseAddr2, 2, size);
 171     funcPort.memsetBlob(baseAddr2, 2, size);
 172     cachePort.memsetBlob(uncacheAddr, 3, size);
 173     funcPort.memsetBlob(uncacheAddr, 3, size);
 174 }
 175
 176 static void
 177 printData(ostream &os, uint8_t *data, int nbytes)
 178 {
 179     os << hex << setfill('0');
 180     // assume little-endian: print bytes from highest address to lowest
 181     for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
 182         os << setw(2) << (unsigned)*dp;
 183     }
 184     os << dec;
 185 }
 186
 187 void
 188 MemTest::completeRequest(Packet *pkt)
 189 {
 190     MemTestSenderState *state =
 191         dynamic_cast<MemTestSenderState *>(pkt->senderState);
 192
 193     uint8_t *data = state->data;
 194     uint8_t *pkt_data = pkt->getPtr<uint8_t>();
 195     Request *req = pkt->req;
 196
 197     //Remove the address from the list of outstanding
 198     std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
 199     assert(removeAddr != outstandingAddrs.end());
 200     outstandingAddrs.erase(removeAddr);
 201
 202     switch (pkt->cmd) {
 203       case Packet::ReadResp:
 204
 205         if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
 206             cerr << name() << ": on read of 0x" << hex << req->getPaddr()
 207                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 208                  << "@ cycle " << dec << curTick
 209                  << ", cache returns 0x";
 210             printData(cerr, pkt_data, pkt->getSize());
 211             cerr << ", expected 0x";
 212             printData(cerr, data, pkt->getSize());
 213             cerr << endl;
 214             fatal("");
 215         }
 216
 217         numReads++;
 218         numReadsStat++;
 219
 220         if (numReads == nextProgressMessage) {
 221             ccprintf(cerr, "%s: completed %d read accesses @%d\n",
 222                      name(), numReads, curTick);
 223             nextProgressMessage += progressInterval;
 224         }
 225
 226         if (numReads >= maxLoads)
 227             exitSimLoop("Maximum number of loads reached!");
 228         break;
 229
 230       case Packet::WriteResp:
 231         numWritesStat++;
 232         break;
 233 /*
 234       case Copy:
 235         //Also remove dest from outstanding list
 236         removeAddr = outstandingAddrs.find(req->dest);
 237         assert(removeAddr != outstandingAddrs.end());
 238         outstandingAddrs.erase(removeAddr);
 239         numCopiesStat++;
 240         break;
 241 */
 242       default:
 243         panic("invalid command");
 244     }
 245
 246     if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 247         cerr << name() << ": completed "
 248              << (pkt->isWrite() ? "write" : "read")
 249              << " access of "
 250              << dec << pkt->getSize() << " bytes at address 0x"
 251              << hex << req->getPaddr()
 252              << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 253              << ", value = 0x";
 254         printData(cerr, pkt_data, pkt->getSize());
 255         cerr << " @ cycle " << dec << curTick;
 256
 257         cerr << endl;
 258     }
 259
 260     noResponseCycles = 0;
 261     delete state;
 262     delete [] data;
 263     delete pkt->req;
 264     delete pkt;
 265 }
 266
 267 void
 268 MemTest::regStats()
 269 {
 270     using namespace Stats;
 271
 272     numReadsStat
 273         .name(name() + ".num_reads")
 274         .desc("number of read accesses completed")
 275         ;
 276
 277     numWritesStat
 278         .name(name() + ".num_writes")
 279         .desc("number of write accesses completed")
 280         ;
 281
 282     numCopiesStat
 283         .name(name() + ".num_copies")
 284         .desc("number of copy accesses completed")
 285         ;
 286 }
 287
 288 void
 289 MemTest::tick()
 290 {
 291     if (!tickEvent.scheduled())
 292         tickEvent.schedule(curTick + cycles(1));
 293
 294     if (++noResponseCycles >= 500000) {
 295         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 296         fatal("");
 297     }
 298
 299     if (accessRetry) {
 300         return;
 301     }
 302
 303     //make new request
 304     unsigned cmd = random() % 100;
 305     unsigned offset = random() % size;
 306     unsigned base = random() % 2;
 307     uint64_t data = random();
 308     unsigned access_size = random() % 4;
 309     unsigned cacheable = random() % 100;
 310
 311     //If we aren't doing copies, use id as offset, and do a false sharing
 312     //mem tester
 313     //We can eliminate the lower bits of the offset, and then use the id
 314     //to offset within the blks
 315     offset &= ~63; //Not the low order bits
 316     offset += id;
 317     access_size = 0;
 318
 319     Request *req = new Request();
 320     uint32_t flags = 0;
 321     Addr paddr;
 322
 323     if (cacheable < percentUncacheable) {
 324         flags |= UNCACHEABLE;
 325         paddr = uncacheAddr + offset;
 326     } else {
 327         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
 328     }
 329     //bool probe = (random() % 2 == 1) && !req->isUncacheable();
 330     bool probe = false;
 331
 332     paddr &= ~((1 << access_size) - 1);
 333     req->setPhys(paddr, 1 << access_size, flags);
 334     req->setThreadContext(id,0);
 335
 336     uint8_t *result = new uint8_t[8];
 337
 338     if (cmd < percentReads) {
 339         // read
 340
 341         //For now we only allow one outstanding request per addreess per tester
 342         //This means we assume CPU does write forwarding to reads that alias something
 343         //in the cpu store buffer.
 344         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 345         else outstandingAddrs.insert(paddr);
 346
 347         // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
 348         funcPort.readBlob(req->getPaddr(), result, req->getSize());
 349
 350         if (blockAddr(paddr) == traceBlockAddr) {
 351             cerr << name()
 352                  << ": initiating read "
 353                  << ((probe) ? "probe of " : "access of ")
 354                  << dec << req->getSize() << " bytes from addr 0x"
 355                  << hex << paddr
 356                  << " (0x" << hex << blockAddr(paddr) << ")"
 357                  << " at cycle "
 358                  << dec << curTick << endl;
 359         }
 360
 361         Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
 362         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
 363         MemTestSenderState *state = new MemTestSenderState(result);
 364         pkt->senderState = state;
 365
 366         if (probe) {
 367             cachePort.sendFunctional(pkt);
 368             completeRequest(pkt);
 369         } else {
 370 //          req->completionEvent = new MemCompleteEvent(req, result, this);
 371             if (!cachePort.sendTiming(pkt)) {
 372                 accessRetry = true;
 373                 retryPkt = pkt;
 374             }
 375         }
 376     } else {
 377         // write
 378
 379         //For now we only allow one outstanding request per addreess per tester
 380         //This means we assume CPU does write forwarding to reads that alias something
 381         //in the cpu store buffer.
 382         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 383         else outstandingAddrs.insert(paddr);
 384
 385 /*
 386         if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 387             cerr << name() << ": initiating write "
 388                  << ((probe)?"probe of ":"access of ")
 389                  << dec << req->getSize() << " bytes (value = 0x";
 390             printData(cerr, data_pkt->getPtr(), req->getSize());
 391             cerr << ") to addr 0x"
 392                  << hex << req->getPaddr()
 393                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 394                  << " at cycle "
 395                  << dec << curTick << endl;
 396         }
 397 */
 398         Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 399         uint8_t *pkt_data = new uint8_t[req->getSize()];
 400         pkt->dataDynamicArray(pkt_data);
 401         memcpy(pkt_data, &data, req->getSize());
 402         MemTestSenderState *state = new MemTestSenderState(result);
 403         pkt->senderState = state;
 404
 405         funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
 406
 407         if (probe) {
 408             cachePort.sendFunctional(pkt);
 409 //          completeRequest(req, NULL);
 410         } else {
 411 //          req->completionEvent = new MemCompleteEvent(req, NULL, this);
 412             if (!cachePort.sendTiming(pkt)) {
 413                 accessRetry = true;
 414                 retryPkt = pkt;
 415             }
 416         }
 417     }
 418 /*    else {
 419         // copy
 420         unsigned source_align = random() % 100;
 421         unsigned dest_align = random() % 100;
 422         unsigned offset2 = random() % size;
 423
 424         Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
 425         Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
 426         if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
 427         else outstandingAddrs.insert(source);
 428         if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
 429         else outstandingAddrs.insert(dest);
 430
 431         if (source_align >= percentSourceUnaligned) {
 432             source = blockAddr(source);
 433         }
 434         if (dest_align >= percentDestUnaligned) {
 435             dest = blockAddr(dest);
 436         }
 437         req->cmd = Copy;
 438         req->flags &= ~UNCACHEABLE;
 439         req->paddr = source;
 440         req->dest = dest;
 441         delete [] req->data;
 442         req->data = new uint8_t[blockSize];
 443         req->size = blockSize;
 444         if (source == traceBlockAddr || dest == traceBlockAddr) {
 445             cerr << name()
 446                  << ": initiating copy of "
 447                  << dec << req->size << " bytes from addr 0x"
 448                  << hex << source
 449                  << " (0x" << hex << blockAddr(source) << ")"
 450                  << " to addr 0x"
 451                  << hex << dest
 452                  << " (0x" << hex << blockAddr(dest) << ")"
 453                  << " at cycle "
 454                  << dec << curTick << endl;
 455         }*
 456         cacheInterface->access(req);
 457         uint8_t result[blockSize];
 458         checkMem->access(Read, source, &result, blockSize);
 459         checkMem->access(Write, dest, &result, blockSize);
 460     }
 461 */
 462 }
 463
 464 void
 465 MemTest::doRetry()
 466 {
 467     if (cachePort.sendTiming(retryPkt)) {
 468         accessRetry = false;
 469         retryPkt = NULL;
 470     }
 471 }
 472
 473 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 474
 475 //    SimObjectParam<BaseCache *> cache;
 476 //    SimObjectParam<PhysicalMemory *> main_mem;
 477 //    SimObjectParam<PhysicalMemory *> check_mem;
 478     Param<unsigned> memory_size;
 479     Param<unsigned> percent_reads;
 480 //    Param<unsigned> percent_copies;
 481     Param<unsigned> percent_uncacheable;
 482     Param<unsigned> progress_interval;
 483     Param<unsigned> percent_source_unaligned;
 484     Param<unsigned> percent_dest_unaligned;
 485     Param<Addr> trace_addr;
 486     Param<Counter> max_loads;
 487
 488 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 489
 490
 491 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 492
 493 //    INIT_PARAM(cache, "L1 cache"),
 494 //    INIT_PARAM(main_mem, "hierarchical memory"),
 495 //    INIT_PARAM(check_mem, "check memory"),
 496     INIT_PARAM(memory_size, "memory size"),
 497     INIT_PARAM(percent_reads, "target read percentage"),
 498 //    INIT_PARAM(percent_copies, "target copy percentage"),
 499     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
 500     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
 501     INIT_PARAM(percent_source_unaligned,
 502                "percent of copy source address that are unaligned"),
 503     INIT_PARAM(percent_dest_unaligned,
 504                "percent of copy dest address that are unaligned"),
 505     INIT_PARAM(trace_addr, "address to trace"),
 506     INIT_PARAM(max_loads, "terminate when we have reached this load count")
 507
 508 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 509
 510
 511 CREATE_SIM_OBJECT(MemTest)
 512 {
 513     return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
 514                        /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
 515                        percent_uncacheable, progress_interval,
 516                        percent_source_unaligned, percent_dest_unaligned,
 517                        trace_addr, max_loads);
 518 }
 519
 520 REGISTER_SIM_OBJECT("MemTest", MemTest)