2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
39 #include "base/misc.hh"
40 #include "base/statistics.hh"
41 //#include "cpu/simple_thread.hh"
42 #include "cpu/memtest/memtest.hh"
43 //#include "mem/cache/base_cache.hh"
44 //#include "mem/physical.hh"
45 #include "sim/builder.hh"
46 #include "sim/sim_events.hh"
47 #include "sim/stats.hh"
48 #include "mem/packet.hh"
49 #include "mem/request.hh"
50 #include "mem/port.hh"
51 #include "mem/mem_object.hh"
55 int TESTER_ALLOCATOR
=0;
58 MemTest::CpuPort::recvTiming(Packet
*pkt
)
60 memtest
->completeRequest(pkt
);
65 MemTest::CpuPort::recvAtomic(Packet
*pkt
)
67 panic("MemTest doesn't expect recvAtomic callback!");
72 MemTest::CpuPort::recvFunctional(Packet
*pkt
)
74 //Do nothing if we see one come through
75 if (curTick
!= 0)//Supress warning durring initialization
76 warn("Functional Writes not implemented in MemTester\n");
77 //Need to find any response values that intersect and update
82 MemTest::CpuPort::recvStatusChange(Status status
)
84 if (status
== RangeChange
)
87 panic("MemTest doesn't expect recvStatusChange callback!");
91 MemTest::CpuPort::recvRetry()
97 MemTest::sendPkt(Packet
*pkt
) {
99 cachePort
.sendAtomic(pkt
);
100 pkt
->makeAtomicResponse();
101 completeRequest(pkt
);
103 else if (!cachePort
.sendTiming(pkt
)) {
110 MemTest::MemTest(const string
&name
,
111 // MemInterface *_cache_interface,
112 // PhysicalMemory *main_mem,
113 // PhysicalMemory *check_mem,
114 unsigned _memorySize
,
115 unsigned _percentReads
,
116 // unsigned _percentCopies,
117 unsigned _percentUncacheable
,
118 unsigned _progressInterval
,
119 unsigned _percentSourceUnaligned
,
120 unsigned _percentDestUnaligned
,
126 cachePort("test", this),
127 funcPort("functional", this),
129 // mainMem(main_mem),
130 // checkMem(check_mem),
132 percentReads(_percentReads
),
133 // percentCopies(_percentCopies),
134 percentUncacheable(_percentUncacheable
),
135 progressInterval(_progressInterval
),
136 nextProgressMessage(_progressInterval
),
137 percentSourceUnaligned(_percentSourceUnaligned
),
138 percentDestUnaligned(percentDestUnaligned
),
139 maxLoads(_max_loads
),
143 cmd
.push_back("/bin/ls");
144 vector
<string
> null_vec
;
145 // thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
148 // Needs to be masked off once we know the block size.
149 traceBlockAddr
= _traceAddr
;
150 baseAddr1
= 0x100000;
151 baseAddr2
= 0x400000;
152 uncacheAddr
= 0x800000;
155 noResponseCycles
= 0;
157 tickEvent
.schedule(0);
159 id
= TESTER_ALLOCATOR
++;
160 if (TESTER_ALLOCATOR
> 8)
161 panic("False sharing memtester only allows up to 8 testers");
167 MemTest::getPort(const std::string
&if_name
, int idx
)
169 if (if_name
== "functional")
171 else if (if_name
== "test")
174 panic("No Such Port\n");
180 // By the time init() is called, the ports should be hooked up.
181 blockSize
= cachePort
.peerBlockSize();
182 blockAddrMask
= blockSize
- 1;
183 traceBlockAddr
= blockAddr(traceBlockAddr
);
185 // set up intial memory contents here
187 cachePort
.memsetBlob(baseAddr1
, 1, size
);
188 funcPort
.memsetBlob(baseAddr1
, 1, size
);
189 cachePort
.memsetBlob(baseAddr2
, 2, size
);
190 funcPort
.memsetBlob(baseAddr2
, 2, size
);
191 cachePort
.memsetBlob(uncacheAddr
, 3, size
);
192 funcPort
.memsetBlob(uncacheAddr
, 3, size
);
196 printData(ostream
&os
, uint8_t *data
, int nbytes
)
198 os
<< hex
<< setfill('0');
199 // assume little-endian: print bytes from highest address to lowest
200 for (uint8_t *dp
= data
+ nbytes
- 1; dp
>= data
; --dp
) {
201 os
<< setw(2) << (unsigned)*dp
;
207 MemTest::completeRequest(Packet
*pkt
)
209 MemTestSenderState
*state
=
210 dynamic_cast<MemTestSenderState
*>(pkt
->senderState
);
212 uint8_t *data
= state
->data
;
213 uint8_t *pkt_data
= pkt
->getPtr
<uint8_t>();
214 Request
*req
= pkt
->req
;
216 //Remove the address from the list of outstanding
217 std::set
<unsigned>::iterator removeAddr
= outstandingAddrs
.find(req
->getPaddr());
218 assert(removeAddr
!= outstandingAddrs
.end());
219 outstandingAddrs
.erase(removeAddr
);
222 case Packet::ReadResp
:
224 if (memcmp(pkt_data
, data
, pkt
->getSize()) != 0) {
225 cerr
<< name() << ": on read of 0x" << hex
<< req
->getPaddr()
226 << " (0x" << hex
<< blockAddr(req
->getPaddr()) << ")"
227 << "@ cycle " << dec
<< curTick
228 << ", cache returns 0x";
229 printData(cerr
, pkt_data
, pkt
->getSize());
230 cerr
<< ", expected 0x";
231 printData(cerr
, data
, pkt
->getSize());
239 if (numReads
== nextProgressMessage
) {
240 ccprintf(cerr
, "%s: completed %d read accesses @%d\n",
241 name(), numReads
, curTick
);
242 nextProgressMessage
+= progressInterval
;
245 if (numReads
>= maxLoads
)
246 exitSimLoop("Maximum number of loads reached!");
249 case Packet::WriteResp
:
254 //Also remove dest from outstanding list
255 removeAddr = outstandingAddrs.find(req->dest);
256 assert(removeAddr != outstandingAddrs.end());
257 outstandingAddrs.erase(removeAddr);
262 panic("invalid command");
265 if (blockAddr(req
->getPaddr()) == traceBlockAddr
) {
266 cerr
<< name() << ": completed "
267 << (pkt
->isWrite() ? "write" : "read")
269 << dec
<< pkt
->getSize() << " bytes at address 0x"
270 << hex
<< req
->getPaddr()
271 << " (0x" << hex
<< blockAddr(req
->getPaddr()) << ")"
273 printData(cerr
, pkt_data
, pkt
->getSize());
274 cerr
<< " @ cycle " << dec
<< curTick
;
279 noResponseCycles
= 0;
289 using namespace Stats
;
292 .name(name() + ".num_reads")
293 .desc("number of read accesses completed")
297 .name(name() + ".num_writes")
298 .desc("number of write accesses completed")
302 .name(name() + ".num_copies")
303 .desc("number of copy accesses completed")
310 if (!tickEvent
.scheduled())
311 tickEvent
.schedule(curTick
+ cycles(1));
313 if (++noResponseCycles
>= 500000) {
314 cerr
<< name() << ": deadlocked at cycle " << curTick
<< endl
;
323 unsigned cmd
= random() % 100;
324 unsigned offset
= random() % size
;
325 unsigned base
= random() % 2;
326 uint64_t data
= random();
327 unsigned access_size
= random() % 4;
328 unsigned cacheable
= random() % 100;
330 //If we aren't doing copies, use id as offset, and do a false sharing
332 //We can eliminate the lower bits of the offset, and then use the id
333 //to offset within the blks
334 offset
&= ~63; //Not the low order bits
338 Request
*req
= new Request();
342 if (cacheable
< percentUncacheable
) {
343 flags
|= UNCACHEABLE
;
344 paddr
= uncacheAddr
+ offset
;
346 paddr
= ((base
) ? baseAddr1
: baseAddr2
) + offset
;
348 //bool probe = (random() % 2 == 1) && !req->isUncacheable();
351 paddr
&= ~((1 << access_size
) - 1);
352 req
->setPhys(paddr
, 1 << access_size
, flags
);
353 req
->setThreadContext(id
,0);
355 uint8_t *result
= new uint8_t[8];
357 if (cmd
< percentReads
) {
360 //For now we only allow one outstanding request per addreess per tester
361 //This means we assume CPU does write forwarding to reads that alias something
362 //in the cpu store buffer.
363 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
368 else outstandingAddrs
.insert(paddr
);
370 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
371 funcPort
.readBlob(req
->getPaddr(), result
, req
->getSize());
373 if (blockAddr(paddr
) == traceBlockAddr
) {
375 << ": initiating read "
376 << ((probe
) ? "probe of " : "access of ")
377 << dec
<< req
->getSize() << " bytes from addr 0x"
379 << " (0x" << hex
<< blockAddr(paddr
) << ")"
381 << dec
<< curTick
<< endl
;
384 Packet
*pkt
= new Packet(req
, Packet::ReadReq
, Packet::Broadcast
);
385 pkt
->dataDynamicArray(new uint8_t[req
->getSize()]);
386 MemTestSenderState
*state
= new MemTestSenderState(result
);
387 pkt
->senderState
= state
;
390 cachePort
.sendFunctional(pkt
);
391 completeRequest(pkt
);
393 // req->completionEvent = new MemCompleteEvent(req, result, this);
399 //For now we only allow one outstanding request per addreess per tester
400 //This means we assume CPU does write forwarding to reads that alias something
401 //in the cpu store buffer.
402 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
408 else outstandingAddrs
.insert(paddr
);
411 if (blockAddr(req->getPaddr()) == traceBlockAddr) {
412 cerr << name() << ": initiating write "
413 << ((probe)?"probe of ":"access of ")
414 << dec << req->getSize() << " bytes (value = 0x";
415 printData(cerr, data_pkt->getPtr(), req->getSize());
416 cerr << ") to addr 0x"
417 << hex << req->getPaddr()
418 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
420 << dec << curTick << endl;
423 Packet
*pkt
= new Packet(req
, Packet::WriteReq
, Packet::Broadcast
);
424 uint8_t *pkt_data
= new uint8_t[req
->getSize()];
425 pkt
->dataDynamicArray(pkt_data
);
426 memcpy(pkt_data
, &data
, req
->getSize());
427 MemTestSenderState
*state
= new MemTestSenderState(result
);
428 pkt
->senderState
= state
;
430 funcPort
.writeBlob(req
->getPaddr(), pkt_data
, req
->getSize());
433 cachePort
.sendFunctional(pkt
);
434 completeRequest(pkt
);
436 // req->completionEvent = new MemCompleteEvent(req, NULL, this);
442 unsigned source_align = random() % 100;
443 unsigned dest_align = random() % 100;
444 unsigned offset2 = random() % size;
446 Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
447 Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
448 if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
449 else outstandingAddrs.insert(source);
450 if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
451 else outstandingAddrs.insert(dest);
453 if (source_align >= percentSourceUnaligned) {
454 source = blockAddr(source);
456 if (dest_align >= percentDestUnaligned) {
457 dest = blockAddr(dest);
460 req->flags &= ~UNCACHEABLE;
464 req->data = new uint8_t[blockSize];
465 req->size = blockSize;
466 if (source == traceBlockAddr || dest == traceBlockAddr) {
468 << ": initiating copy of "
469 << dec << req->size << " bytes from addr 0x"
471 << " (0x" << hex << blockAddr(source) << ")"
474 << " (0x" << hex << blockAddr(dest) << ")"
476 << dec << curTick << endl;
478 cacheInterface->access(req);
479 uint8_t result[blockSize];
480 checkMem->access(Read, source, &result, blockSize);
481 checkMem->access(Write, dest, &result, blockSize);
489 if (cachePort
.sendTiming(retryPkt
)) {
495 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest
)
497 // SimObjectParam<BaseCache *> cache;
498 // SimObjectParam<PhysicalMemory *> main_mem;
499 // SimObjectParam<PhysicalMemory *> check_mem;
500 Param
<unsigned> memory_size
;
501 Param
<unsigned> percent_reads
;
502 // Param<unsigned> percent_copies;
503 Param
<unsigned> percent_uncacheable
;
504 Param
<unsigned> progress_interval
;
505 Param
<unsigned> percent_source_unaligned
;
506 Param
<unsigned> percent_dest_unaligned
;
507 Param
<Addr
> trace_addr
;
508 Param
<Counter
> max_loads
;
511 END_DECLARE_SIM_OBJECT_PARAMS(MemTest
)
514 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest
)
516 // INIT_PARAM(cache, "L1 cache"),
517 // INIT_PARAM(main_mem, "hierarchical memory"),
518 // INIT_PARAM(check_mem, "check memory"),
519 INIT_PARAM(memory_size
, "memory size"),
520 INIT_PARAM(percent_reads
, "target read percentage"),
521 // INIT_PARAM(percent_copies, "target copy percentage"),
522 INIT_PARAM(percent_uncacheable
, "target uncacheable percentage"),
523 INIT_PARAM(progress_interval
, "progress report interval (in accesses)"),
524 INIT_PARAM(percent_source_unaligned
,
525 "percent of copy source address that are unaligned"),
526 INIT_PARAM(percent_dest_unaligned
,
527 "percent of copy dest address that are unaligned"),
528 INIT_PARAM(trace_addr
, "address to trace"),
529 INIT_PARAM(max_loads
, "terminate when we have reached this load count"),
530 INIT_PARAM(atomic
, "Is the tester testing atomic mode (or timing)")
532 END_INIT_SIM_OBJECT_PARAMS(MemTest
)
535 CREATE_SIM_OBJECT(MemTest
)
537 return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
538 /*check_mem,*/ memory_size
, percent_reads
, /*percent_copies,*/
539 percent_uncacheable
, progress_interval
,
540 percent_source_unaligned
, percent_dest_unaligned
,
541 trace_addr
, max_loads
, atomic
);
544 REGISTER_SIM_OBJECT("MemTest", MemTest
)