2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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9 * redistributions in binary form must reproduce the above copyright
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
39 #include "base/misc.hh"
40 #include "base/statistics.hh"
41 #include "cpu/memtest/memtest.hh"
42 //#include "cpu/simple_thread.hh"
43 //#include "mem/cache/base_cache.hh"
44 #include "mem/mem_object.hh"
45 #include "mem/port.hh"
46 #include "mem/packet.hh"
47 //#include "mem/physical.hh"
48 #include "mem/request.hh"
49 #include "sim/sim_events.hh"
50 #include "sim/stats.hh"
54 int TESTER_ALLOCATOR
=0;
57 MemTest::CpuPort::recvTiming(PacketPtr pkt
)
59 if (pkt
->isResponse()) {
60 memtest
->completeRequest(pkt
);
62 // must be snoop upcall
63 assert(pkt
->isRequest());
64 assert(pkt
->getDest() == Packet::Broadcast
);
70 MemTest::CpuPort::recvAtomic(PacketPtr pkt
)
72 // must be snoop upcall
73 assert(pkt
->isRequest());
74 assert(pkt
->getDest() == Packet::Broadcast
);
79 MemTest::CpuPort::recvFunctional(PacketPtr pkt
)
81 //Do nothing if we see one come through
82 // if (curTick != 0)//Supress warning durring initialization
83 // warn("Functional Writes not implemented in MemTester\n");
84 //Need to find any response values that intersect and update
89 MemTest::CpuPort::recvStatusChange(Status status
)
91 if (status
== RangeChange
) {
92 if (!snoopRangeSent
) {
93 snoopRangeSent
= true;
94 sendStatusChange(Port::RangeChange
);
99 panic("MemTest doesn't expect recvStatusChange callback!");
103 MemTest::CpuPort::recvRetry()
109 MemTest::sendPkt(PacketPtr pkt
) {
111 cachePort
.sendAtomic(pkt
);
112 completeRequest(pkt
);
114 else if (!cachePort
.sendTiming(pkt
)) {
121 MemTest::MemTest(const Params
*p
)
124 cachePort("test", this),
125 funcPort("functional", this),
127 // mainMem(main_mem),
128 // checkMem(check_mem),
129 size(p
->memory_size
),
130 percentReads(p
->percent_reads
),
131 percentFunctional(p
->percent_functional
),
132 percentUncacheable(p
->percent_uncacheable
),
133 progressInterval(p
->progress_interval
),
134 nextProgressMessage(p
->progress_interval
),
135 percentSourceUnaligned(p
->percent_source_unaligned
),
136 percentDestUnaligned(p
->percent_dest_unaligned
),
137 maxLoads(p
->max_loads
),
141 cmd
.push_back("/bin/ls");
142 vector
<string
> null_vec
;
143 // thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
146 cachePort
.snoopRangeSent
= false;
147 funcPort
.snoopRangeSent
= true;
149 // Needs to be masked off once we know the block size.
150 traceBlockAddr
= p
->trace_addr
;
151 baseAddr1
= 0x100000;
152 baseAddr2
= 0x400000;
153 uncacheAddr
= 0x800000;
156 noResponseCycles
= 0;
158 tickEvent
.schedule(0);
160 id
= TESTER_ALLOCATOR
++;
166 MemTest::getPort(const std::string
&if_name
, int idx
)
168 if (if_name
== "functional")
170 else if (if_name
== "test")
173 panic("No Such Port\n");
179 // By the time init() is called, the ports should be hooked up.
180 blockSize
= cachePort
.peerBlockSize();
181 blockAddrMask
= blockSize
- 1;
182 traceBlockAddr
= blockAddr(traceBlockAddr
);
184 // initial memory contents for both physical memory and functional
185 // memory should be 0; no need to initialize them.
190 MemTest::completeRequest(PacketPtr pkt
)
192 Request
*req
= pkt
->req
;
194 DPRINTF(MemTest
, "completing %s at address %x (blk %x)\n",
195 pkt
->isWrite() ? "write" : "read",
196 req
->getPaddr(), blockAddr(req
->getPaddr()));
198 MemTestSenderState
*state
=
199 dynamic_cast<MemTestSenderState
*>(pkt
->senderState
);
201 uint8_t *data
= state
->data
;
202 uint8_t *pkt_data
= pkt
->getPtr
<uint8_t>();
204 //Remove the address from the list of outstanding
205 std::set
<unsigned>::iterator removeAddr
=
206 outstandingAddrs
.find(req
->getPaddr());
207 assert(removeAddr
!= outstandingAddrs
.end());
208 outstandingAddrs
.erase(removeAddr
);
210 assert(pkt
->isResponse());
213 if (memcmp(pkt_data
, data
, pkt
->getSize()) != 0) {
214 panic("%s: read of %x (blk %x) @ cycle %d "
215 "returns %x, expected %x\n", name(),
216 req
->getPaddr(), blockAddr(req
->getPaddr()), curTick
,
223 if (numReads
== nextProgressMessage
) {
224 ccprintf(cerr
, "%s: completed %d read accesses @%d\n",
225 name(), numReads
, curTick
);
226 nextProgressMessage
+= progressInterval
;
229 if (maxLoads
!= 0 && numReads
>= maxLoads
)
230 exitSimLoop("maximum number of loads reached");
232 assert(pkt
->isWrite());
236 noResponseCycles
= 0;
246 using namespace Stats
;
249 .name(name() + ".num_reads")
250 .desc("number of read accesses completed")
254 .name(name() + ".num_writes")
255 .desc("number of write accesses completed")
259 .name(name() + ".num_copies")
260 .desc("number of copy accesses completed")
267 if (!tickEvent
.scheduled())
268 tickEvent
.schedule(curTick
+ ticks(1));
270 if (++noResponseCycles
>= 500000) {
271 cerr
<< name() << ": deadlocked at cycle " << curTick
<< endl
;
280 unsigned cmd
= random() % 100;
281 unsigned offset
= random() % size
;
282 unsigned base
= random() % 2;
283 uint64_t data
= random();
284 unsigned access_size
= random() % 4;
285 unsigned cacheable
= random() % 100;
287 //If we aren't doing copies, use id as offset, and do a false sharing
289 //We can eliminate the lower bits of the offset, and then use the id
290 //to offset within the blks
291 offset
= blockAddr(offset
);
295 Request
*req
= new Request();
299 if (cacheable
< percentUncacheable
) {
300 flags
|= UNCACHEABLE
;
301 paddr
= uncacheAddr
+ offset
;
303 paddr
= ((base
) ? baseAddr1
: baseAddr2
) + offset
;
305 bool probe
= (random() % 100 < percentFunctional
) && !(flags
& UNCACHEABLE
);
306 //bool probe = false;
308 paddr
&= ~((1 << access_size
) - 1);
309 req
->setPhys(paddr
, 1 << access_size
, flags
);
310 req
->setThreadContext(id
,0);
312 uint8_t *result
= new uint8_t[8];
314 if (cmd
< percentReads
) {
317 // For now we only allow one outstanding request per address
318 // per tester This means we assume CPU does write forwarding
319 // to reads that alias something in the cpu store buffer.
320 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
326 outstandingAddrs
.insert(paddr
);
328 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
329 funcPort
.readBlob(req
->getPaddr(), result
, req
->getSize());
332 "initiating read at address %x (blk %x) expecting %x\n",
333 req
->getPaddr(), blockAddr(req
->getPaddr()), *result
);
335 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
337 pkt
->dataDynamicArray(new uint8_t[req
->getSize()]);
338 MemTestSenderState
*state
= new MemTestSenderState(result
);
339 pkt
->senderState
= state
;
342 cachePort
.sendFunctional(pkt
);
343 completeRequest(pkt
);
350 // For now we only allow one outstanding request per addreess
351 // per tester. This means we assume CPU does write forwarding
352 // to reads that alias something in the cpu store buffer.
353 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
359 outstandingAddrs
.insert(paddr
);
361 DPRINTF(MemTest
, "initiating write at address %x (blk %x) value %x\n",
362 req
->getPaddr(), blockAddr(req
->getPaddr()), data
& 0xff);
364 PacketPtr pkt
= new Packet(req
, MemCmd::WriteReq
, Packet::Broadcast
);
366 uint8_t *pkt_data
= new uint8_t[req
->getSize()];
367 pkt
->dataDynamicArray(pkt_data
);
368 memcpy(pkt_data
, &data
, req
->getSize());
369 MemTestSenderState
*state
= new MemTestSenderState(result
);
370 pkt
->senderState
= state
;
372 funcPort
.writeBlob(req
->getPaddr(), pkt_data
, req
->getSize());
375 cachePort
.sendFunctional(pkt
);
376 completeRequest(pkt
);
386 if (cachePort
.sendTiming(retryPkt
)) {
394 MemTest::printAddr(Addr a
)
396 cachePort
.printAddr(a
);
401 MemTestParams::create()
403 return new MemTest(this);