src/cpu/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  */
  31
  32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  33
  34 #include <iomanip>
  35 #include <set>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/misc.hh"
  40 #include "base/statistics.hh"
  41 #include "cpu/simple_thread.hh"
  42 #include "cpu/memtest/memtest.hh"
  43 //#include "mem/cache/base_cache.hh"
  44 #include "mem/physical.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/sim_events.hh"
  47 #include "sim/stats.hh"
  48
  49 using namespace std;
  50 using namespace TheISA;
  51
  52 int TESTER_ALLOCATOR=0;
  53
  54 bool
  55 MemTest::CpuPort::recvTiming(Packet *pkt)
  56 {
  57     memtest->completeRequest(pkt);
  58     return true;
  59 }
  60
  61 Tick
  62 MemTest::CpuPort::recvAtomic(Packet *pkt)
  63 {
  64     panic("MemTest doesn't expect recvAtomic callback!");
  65     return curTick;
  66 }
  67
  68 void
  69 MemTest::CpuPort::recvFunctional(Packet *pkt)
  70 {
  71     memtest->completeRequest(pkt);
  72 }
  73
  74 void
  75 MemTest::CpuPort::recvStatusChange(Status status)
  76 {
  77     if (status == RangeChange)
  78         return;
  79
  80     panic("MemTest doesn't expect recvStatusChange callback!");
  81 }
  82
  83 void
  84 MemTest::CpuPort::recvRetry()
  85 {
  86     memtest->doRetry();
  87 }
  88
  89
  90 MemTest::MemTest(const string &name,
  91 //               MemInterface *_cache_interface,
  92                  PhysicalMemory *main_mem,
  93                  PhysicalMemory *check_mem,
  94                  unsigned _memorySize,
  95                  unsigned _percentReads,
  96 //               unsigned _percentCopies,
  97                  unsigned _percentUncacheable,
  98                  unsigned _progressInterval,
  99                  unsigned _percentSourceUnaligned,
 100                  unsigned _percentDestUnaligned,
 101                  Addr _traceAddr,
 102                  Counter _max_loads)
 103     : MemObject(name),
 104       tickEvent(this),
 105       cachePort("dcache", this),
 106       retryPkt(NULL),
 107       mainMem(main_mem),
 108       checkMem(check_mem),
 109       size(_memorySize),
 110       percentReads(_percentReads),
 111 //      percentCopies(_percentCopies),
 112       percentUncacheable(_percentUncacheable),
 113       progressInterval(_progressInterval),
 114       nextProgressMessage(_progressInterval),
 115       percentSourceUnaligned(_percentSourceUnaligned),
 116       percentDestUnaligned(percentDestUnaligned),
 117       maxLoads(_max_loads)
 118 {
 119     vector<string> cmd;
 120     cmd.push_back("/bin/ls");
 121     vector<string> null_vec;
 122     thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
 123     curTick = 0;
 124
 125     // Needs to be masked off once we know the block size.
 126     traceBlockAddr = _traceAddr;
 127     baseAddr1 = 0x100000;
 128     baseAddr2 = 0x400000;
 129     uncacheAddr = 0x800000;
 130
 131     // set up counters
 132     noResponseCycles = 0;
 133     numReads = 0;
 134     tickEvent.schedule(0);
 135
 136     id = TESTER_ALLOCATOR++;
 137 }
 138
 139 Port *
 140 MemTest::getPort(const std::string &if_name, int idx)
 141 {
 142     // ***** NOTE TO RON: I'm not sure what it should do if these get ports
 143     // are called on it.
 144     if (if_name == "dcache_port")
 145         return &cachePort;
 146     else if (if_name == "icache_port")
 147         return &cachePort;
 148     else
 149         panic("No Such Port\n");
 150 }
 151
 152 void
 153 MemTest::init()
 154 {
 155     // By the time init() is called, the ports should be hooked up.
 156     blockSize = cachePort.peerBlockSize();
 157     blockAddrMask = blockSize - 1;
 158     traceBlockAddr = blockAddr(traceBlockAddr);
 159
 160     //setup data storage with interesting values
 161     uint8_t *data1 = new uint8_t[size];
 162     uint8_t *data2 = new uint8_t[size];
 163     uint8_t *data3 = new uint8_t[size];
 164     memset(data1, 1, size);
 165     memset(data2, 2, size);
 166     memset(data3, 3, size);
 167
 168     // set up intial memory contents here
 169     // ***** NOTE FOR RON: I'm not sure how to setup initial memory
 170     // contents. - Kevin
 171 /*
 172     mainMem->prot_write(baseAddr1, data1, size);
 173     checkMem->prot_write(baseAddr1, data1, size);
 174     mainMem->prot_write(baseAddr2, data2, size);
 175     checkMem->prot_write(baseAddr2, data2, size);
 176     mainMem->prot_write(uncacheAddr, data3, size);
 177     checkMem->prot_write(uncacheAddr, data3, size);
 178 */
 179
 180     delete [] data1;
 181     delete [] data2;
 182     delete [] data3;
 183 }
 184
 185 static void
 186 printData(ostream &os, uint8_t *data, int nbytes)
 187 {
 188     os << hex << setfill('0');
 189     // assume little-endian: print bytes from highest address to lowest
 190     for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
 191         os << setw(2) << (unsigned)*dp;
 192     }
 193     os << dec;
 194 }
 195
 196 void
 197 MemTest::completeRequest(Packet *pkt)
 198 {
 199     MemTestSenderState *state =
 200         dynamic_cast<MemTestSenderState *>(pkt->senderState);
 201
 202     uint8_t *data = state->data;
 203     uint8_t *pkt_data = pkt->getPtr<uint8_t>();
 204     Request *req = pkt->req;
 205
 206     //Remove the address from the list of outstanding
 207     std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
 208     assert(removeAddr != outstandingAddrs.end());
 209     outstandingAddrs.erase(removeAddr);
 210
 211     switch (pkt->cmd) {
 212       case Packet::ReadReq:
 213
 214         if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
 215             cerr << name() << ": on read of 0x" << hex << req->getPaddr()
 216                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 217                  << "@ cycle " << dec << curTick
 218                  << ", cache returns 0x";
 219             printData(cerr, pkt_data, pkt->getSize());
 220             cerr << ", expected 0x";
 221             printData(cerr, data, pkt->getSize());
 222             cerr << endl;
 223             fatal("");
 224         }
 225
 226         numReads++;
 227         numReadsStat++;
 228
 229         if (numReads == nextProgressMessage) {
 230             ccprintf(cerr, "%s: completed %d read accesses @%d\n",
 231                      name(), numReads, curTick);
 232             nextProgressMessage += progressInterval;
 233         }
 234
 235         if (numReads >= maxLoads)
 236             exitSimLoop("Maximum number of loads reached!");
 237         break;
 238
 239       case Packet::WriteReq:
 240         numWritesStat++;
 241         break;
 242 /*
 243       case Copy:
 244         //Also remove dest from outstanding list
 245         removeAddr = outstandingAddrs.find(req->dest);
 246         assert(removeAddr != outstandingAddrs.end());
 247         outstandingAddrs.erase(removeAddr);
 248         numCopiesStat++;
 249         break;
 250 */
 251       default:
 252         panic("invalid command");
 253     }
 254
 255     if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 256         cerr << name() << ": completed "
 257              << (pkt->isWrite() ? "write" : "read")
 258              << " access of "
 259              << dec << pkt->getSize() << " bytes at address 0x"
 260              << hex << req->getPaddr()
 261              << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 262              << ", value = 0x";
 263         printData(cerr, pkt_data, pkt->getSize());
 264         cerr << " @ cycle " << dec << curTick;
 265
 266         cerr << endl;
 267     }
 268
 269     noResponseCycles = 0;
 270     delete state;
 271     delete [] data;
 272     delete pkt->req;
 273     delete pkt;
 274 }
 275
 276 void
 277 MemTest::regStats()
 278 {
 279     using namespace Stats;
 280
 281     numReadsStat
 282         .name(name() + ".num_reads")
 283         .desc("number of read accesses completed")
 284         ;
 285
 286     numWritesStat
 287         .name(name() + ".num_writes")
 288         .desc("number of write accesses completed")
 289         ;
 290
 291     numCopiesStat
 292         .name(name() + ".num_copies")
 293         .desc("number of copy accesses completed")
 294         ;
 295 }
 296
 297 void
 298 MemTest::tick()
 299 {
 300     if (!tickEvent.scheduled())
 301         tickEvent.schedule(curTick + cycles(1));
 302
 303     if (++noResponseCycles >= 500000) {
 304         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 305         fatal("");
 306     }
 307
 308     if (accessRetry) {
 309         return;
 310     }
 311
 312     //make new request
 313     unsigned cmd = random() % 100;
 314     unsigned offset = random() % size;
 315     unsigned base = random() % 2;
 316     uint64_t data = random();
 317     unsigned access_size = random() % 4;
 318     unsigned cacheable = random() % 100;
 319
 320     //If we aren't doing copies, use id as offset, and do a false sharing
 321     //mem tester
 322     // ***** NOTE FOR RON: We're not doing copies, but I'm not sure if this
 323     // code should be used.
 324 /*
 325     if (percentCopies == 0) {
 326         //We can eliminate the lower bits of the offset, and then use the id
 327         //to offset within the blks
 328         offset &= ~63; //Not the low order bits
 329         offset += id;
 330         access_size = 0;
 331     }
 332 */
 333
 334     Request *req = new Request();
 335     uint32_t flags = req->getFlags();
 336     Addr paddr;
 337
 338     if (cacheable < percentUncacheable) {
 339         flags |= UNCACHEABLE;
 340         paddr = uncacheAddr + offset;
 341     } else {
 342         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
 343     }
 344     // bool probe = (random() % 2 == 1) && !req->isUncacheable();
 345     bool probe = false;
 346
 347     paddr &= ~((1 << access_size) - 1);
 348     req->setPhys(paddr, 1 << access_size, flags);
 349
 350     uint8_t *result = new uint8_t[8];
 351
 352     if (cmd < percentReads) {
 353         // read
 354
 355         //For now we only allow one outstanding request per addreess per tester
 356         //This means we assume CPU does write forwarding to reads that alias something
 357         //in the cpu store buffer.
 358         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 359         else outstandingAddrs.insert(paddr);
 360
 361         // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
 362 //      checkMem->access(Read, req->getPaddr(), result, req->size);
 363         if (blockAddr(paddr) == traceBlockAddr) {
 364             cerr << name()
 365                  << ": initiating read "
 366                  << ((probe) ? "probe of " : "access of ")
 367                  << dec << req->getSize() << " bytes from addr 0x"
 368                  << hex << paddr
 369                  << " (0x" << hex << blockAddr(paddr) << ")"
 370                  << " at cycle "
 371                  << dec << curTick << endl;
 372         }
 373
 374         Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
 375         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
 376         MemTestSenderState *state = new MemTestSenderState(result);
 377         pkt->senderState = state;
 378
 379         if (probe) {
 380             // ***** NOTE FOR RON: Send functional access?  It used to
 381             // be a probeAndUpdate access. - Kevin
 382             cachePort.sendFunctional(pkt);
 383 //          completeRequest(pkt, result);
 384         } else {
 385 //          req->completionEvent = new MemCompleteEvent(req, result, this);
 386             if (!cachePort.sendTiming(pkt)) {
 387                 accessRetry = true;
 388                 retryPkt = pkt;
 389             }
 390         }
 391     } else {
 392         // write
 393
 394         //For now we only allow one outstanding request per addreess per tester
 395         //This means we assume CPU does write forwarding to reads that alias something
 396         //in the cpu store buffer.
 397         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
 398         else outstandingAddrs.insert(paddr);
 399
 400         // ***** NOTE FOR RON: Not sure how to access memory.
 401 //      checkMem->access(Write, req->paddr, req->data, req->size);
 402 /*
 403         if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 404             cerr << name() << ": initiating write "
 405                  << ((probe)?"probe of ":"access of ")
 406                  << dec << req->getSize() << " bytes (value = 0x";
 407             printData(cerr, data_pkt->getPtr(), req->getSize());
 408             cerr << ") to addr 0x"
 409                  << hex << req->getPaddr()
 410                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 411                  << " at cycle "
 412                  << dec << curTick << endl;
 413         }
 414 */
 415         Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 416         uint8_t *pkt_data = new uint8_t[req->getSize()];
 417         pkt->dataDynamicArray(pkt_data);
 418         memcpy(pkt_data, &data, req->getSize());
 419         MemTestSenderState *state = new MemTestSenderState(result);
 420         pkt->senderState = state;
 421
 422         if (probe) {
 423             // ***** NOTE FOR RON: Send functional access?  It used to
 424             // be a probe access. - Kevin
 425             cachePort.sendFunctional(pkt);
 426 //          completeRequest(req, NULL);
 427         } else {
 428 //          req->completionEvent = new MemCompleteEvent(req, NULL, this);
 429             if (!cachePort.sendTiming(pkt)) {
 430                 accessRetry = true;
 431                 retryPkt = pkt;
 432             }
 433         }
 434     }
 435 /*    else {
 436         // copy
 437         unsigned source_align = random() % 100;
 438         unsigned dest_align = random() % 100;
 439         unsigned offset2 = random() % size;
 440
 441         Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
 442         Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
 443         if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
 444         else outstandingAddrs.insert(source);
 445         if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
 446         else outstandingAddrs.insert(dest);
 447
 448         if (source_align >= percentSourceUnaligned) {
 449             source = blockAddr(source);
 450         }
 451         if (dest_align >= percentDestUnaligned) {
 452             dest = blockAddr(dest);
 453         }
 454         req->cmd = Copy;
 455         req->flags &= ~UNCACHEABLE;
 456         req->paddr = source;
 457         req->dest = dest;
 458         delete [] req->data;
 459         req->data = new uint8_t[blockSize];
 460         req->size = blockSize;
 461         if (source == traceBlockAddr || dest == traceBlockAddr) {
 462             cerr << name()
 463                  << ": initiating copy of "
 464                  << dec << req->size << " bytes from addr 0x"
 465                  << hex << source
 466                  << " (0x" << hex << blockAddr(source) << ")"
 467                  << " to addr 0x"
 468                  << hex << dest
 469                  << " (0x" << hex << blockAddr(dest) << ")"
 470                  << " at cycle "
 471                  << dec << curTick << endl;
 472         }*
 473         cacheInterface->access(req);
 474         uint8_t result[blockSize];
 475         checkMem->access(Read, source, &result, blockSize);
 476         checkMem->access(Write, dest, &result, blockSize);
 477     }
 478 */
 479 }
 480
 481 void
 482 MemTest::doRetry()
 483 {
 484     if (cachePort.sendTiming(retryPkt)) {
 485         accessRetry = false;
 486         retryPkt = NULL;
 487     }
 488 }
 489
 490 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 491
 492 //    SimObjectParam<BaseCache *> cache;
 493     SimObjectParam<PhysicalMemory *> main_mem;
 494     SimObjectParam<PhysicalMemory *> check_mem;
 495     Param<unsigned> memory_size;
 496     Param<unsigned> percent_reads;
 497 //    Param<unsigned> percent_copies;
 498     Param<unsigned> percent_uncacheable;
 499     Param<unsigned> progress_interval;
 500     Param<unsigned> percent_source_unaligned;
 501     Param<unsigned> percent_dest_unaligned;
 502     Param<Addr> trace_addr;
 503     Param<Counter> max_loads;
 504
 505 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 506
 507
 508 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 509
 510 //    INIT_PARAM(cache, "L1 cache"),
 511     INIT_PARAM(main_mem, "hierarchical memory"),
 512     INIT_PARAM(check_mem, "check memory"),
 513     INIT_PARAM(memory_size, "memory size"),
 514     INIT_PARAM(percent_reads, "target read percentage"),
 515 //    INIT_PARAM(percent_copies, "target copy percentage"),
 516     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
 517     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
 518     INIT_PARAM(percent_source_unaligned,
 519                "percent of copy source address that are unaligned"),
 520     INIT_PARAM(percent_dest_unaligned,
 521                "percent of copy dest address that are unaligned"),
 522     INIT_PARAM(trace_addr, "address to trace"),
 523     INIT_PARAM(max_loads, "terminate when we have reached this load count")
 524
 525 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 526
 527
 528 CREATE_SIM_OBJECT(MemTest)
 529 {
 530     return new MemTest(getInstanceName(), /*cache->getInterface(),*/ main_mem,
 531                        check_mem, memory_size, percent_reads, /*percent_copies,*/
 532                        percent_uncacheable, progress_interval,
 533                        percent_source_unaligned, percent_dest_unaligned,
 534                        trace_addr, max_loads);
 535 }
 536
 537 REGISTER_SIM_OBJECT("MemTest", MemTest)