src/cpu/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  */
  31
  32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  33
  34 #include <iomanip>
  35 #include <set>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/misc.hh"
  40 #include "base/statistics.hh"
  41 #include "cpu/memtest/memtest.hh"
  42 //#include "cpu/simple_thread.hh"
  43 //#include "mem/cache/base_cache.hh"
  44 #include "mem/mem_object.hh"
  45 #include "mem/port.hh"
  46 #include "mem/packet.hh"
  47 //#include "mem/physical.hh"
  48 #include "mem/request.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/sim_events.hh"
  51 #include "sim/stats.hh"
  52
  53 using namespace std;
  54
  55 int TESTER_ALLOCATOR=0;
  56
  57 bool
  58 MemTest::CpuPort::recvTiming(PacketPtr pkt)
  59 {
  60     memtest->completeRequest(pkt);
  61     return true;
  62 }
  63
  64 Tick
  65 MemTest::CpuPort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("MemTest doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 void
  72 MemTest::CpuPort::recvFunctional(PacketPtr pkt)
  73 {
  74     //Do nothing if we see one come through
  75 //    if (curTick != 0)//Supress warning durring initialization
  76 //        warn("Functional Writes not implemented in MemTester\n");
  77     //Need to find any response values that intersect and update
  78     return;
  79 }
  80
  81 void
  82 MemTest::CpuPort::recvStatusChange(Status status)
  83 {
  84     if (status == RangeChange) {
  85         if (!snoopRangeSent) {
  86             snoopRangeSent = true;
  87             sendStatusChange(Port::RangeChange);
  88         }
  89         return;
  90     }
  91
  92     panic("MemTest doesn't expect recvStatusChange callback!");
  93 }
  94
  95 void
  96 MemTest::CpuPort::recvRetry()
  97 {
  98     memtest->doRetry();
  99 }
 100
 101 void
 102 MemTest::sendPkt(PacketPtr pkt) {
 103     if (atomic) {
 104         cachePort.sendAtomic(pkt);
 105         pkt->makeAtomicResponse();
 106         completeRequest(pkt);
 107     }
 108     else if (!cachePort.sendTiming(pkt)) {
 109         accessRetry = true;
 110         retryPkt = pkt;
 111     }
 112
 113 }
 114
 115 MemTest::MemTest(const string &name,
 116 //               MemInterface *_cache_interface,
 117 //               PhysicalMemory *main_mem,
 118 //               PhysicalMemory *check_mem,
 119                  unsigned _memorySize,
 120                  unsigned _percentReads,
 121                  unsigned _percentFunctional,
 122                  unsigned _percentUncacheable,
 123                  unsigned _progressInterval,
 124                  unsigned _percentSourceUnaligned,
 125                  unsigned _percentDestUnaligned,
 126                  Addr _traceAddr,
 127                  Counter _max_loads,
 128                  bool _atomic)
 129     : MemObject(name),
 130       tickEvent(this),
 131       cachePort("test", this),
 132       funcPort("functional", this),
 133       retryPkt(NULL),
 134 //      mainMem(main_mem),
 135 //      checkMem(check_mem),
 136       size(_memorySize),
 137       percentReads(_percentReads),
 138       percentFunctional(_percentFunctional),
 139       percentUncacheable(_percentUncacheable),
 140       progressInterval(_progressInterval),
 141       nextProgressMessage(_progressInterval),
 142       percentSourceUnaligned(_percentSourceUnaligned),
 143       percentDestUnaligned(percentDestUnaligned),
 144       maxLoads(_max_loads),
 145       atomic(_atomic)
 146 {
 147     vector<string> cmd;
 148     cmd.push_back("/bin/ls");
 149     vector<string> null_vec;
 150     //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
 151     curTick = 0;
 152
 153     cachePort.snoopRangeSent = false;
 154     funcPort.snoopRangeSent = true;
 155
 156     // Needs to be masked off once we know the block size.
 157     traceBlockAddr = _traceAddr;
 158     baseAddr1 = 0x100000;
 159     baseAddr2 = 0x400000;
 160     uncacheAddr = 0x800000;
 161
 162     // set up counters
 163     noResponseCycles = 0;
 164     numReads = 0;
 165     tickEvent.schedule(0);
 166
 167     id = TESTER_ALLOCATOR++;
 168     if (TESTER_ALLOCATOR > 8)
 169         panic("False sharing memtester only allows up to 8 testers");
 170
 171     accessRetry = false;
 172 }
 173
 174 Port *
 175 MemTest::getPort(const std::string &if_name, int idx)
 176 {
 177     if (if_name == "functional")
 178         return &funcPort;
 179     else if (if_name == "test")
 180         return &cachePort;
 181     else
 182         panic("No Such Port\n");
 183 }
 184
 185 void
 186 MemTest::init()
 187 {
 188     // By the time init() is called, the ports should be hooked up.
 189     blockSize = cachePort.peerBlockSize();
 190     blockAddrMask = blockSize - 1;
 191     traceBlockAddr = blockAddr(traceBlockAddr);
 192
 193     // set up intial memory contents here
 194
 195     cachePort.memsetBlob(baseAddr1, 1, size);
 196     funcPort.memsetBlob(baseAddr1, 1, size);
 197     cachePort.memsetBlob(baseAddr2, 2, size);
 198     funcPort.memsetBlob(baseAddr2, 2, size);
 199     cachePort.memsetBlob(uncacheAddr, 3, size);
 200     funcPort.memsetBlob(uncacheAddr, 3, size);
 201 }
 202
 203 static void
 204 printData(ostream &os, uint8_t *data, int nbytes)
 205 {
 206     os << hex << setfill('0');
 207     // assume little-endian: print bytes from highest address to lowest
 208     for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
 209         os << setw(2) << (unsigned)*dp;
 210     }
 211     os << dec;
 212 }
 213
 214 void
 215 MemTest::completeRequest(PacketPtr pkt)
 216 {
 217     MemTestSenderState *state =
 218         dynamic_cast<MemTestSenderState *>(pkt->senderState);
 219
 220     uint8_t *data = state->data;
 221     uint8_t *pkt_data = pkt->getPtr<uint8_t>();
 222     Request *req = pkt->req;
 223
 224     //Remove the address from the list of outstanding
 225     std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
 226     assert(removeAddr != outstandingAddrs.end());
 227     outstandingAddrs.erase(removeAddr);
 228
 229     switch (pkt->cmd.toInt()) {
 230       case MemCmd::ReadResp:
 231
 232         if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
 233             cerr << name() << ": on read of 0x" << hex << req->getPaddr()
 234                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 235                  << "@ cycle " << dec << curTick
 236                  << ", cache returns 0x";
 237             printData(cerr, pkt_data, pkt->getSize());
 238             cerr << ", expected 0x";
 239             printData(cerr, data, pkt->getSize());
 240             cerr << endl;
 241             fatal("");
 242         }
 243
 244         numReads++;
 245         numReadsStat++;
 246
 247         if (numReads == nextProgressMessage) {
 248             ccprintf(cerr, "%s: completed %d read accesses @%d\n",
 249                      name(), numReads, curTick);
 250             nextProgressMessage += progressInterval;
 251         }
 252
 253         if (numReads >= maxLoads)
 254             exitSimLoop("Maximum number of loads reached!");
 255         break;
 256
 257       case MemCmd::WriteResp:
 258         numWritesStat++;
 259         break;
 260 /*
 261       case Copy:
 262         //Also remove dest from outstanding list
 263         removeAddr = outstandingAddrs.find(req->dest);
 264         assert(removeAddr != outstandingAddrs.end());
 265         outstandingAddrs.erase(removeAddr);
 266         numCopiesStat++;
 267         break;
 268 */
 269       default:
 270         panic("invalid command");
 271     }
 272
 273     if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 274         cerr << name() << ": completed "
 275              << (pkt->isWrite() ? "write" : "read")
 276              << " access of "
 277              << dec << pkt->getSize() << " bytes at address 0x"
 278              << hex << req->getPaddr()
 279              << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 280              << ", value = 0x";
 281         printData(cerr, pkt_data, pkt->getSize());
 282         cerr << " @ cycle " << dec << curTick;
 283
 284         cerr << endl;
 285     }
 286
 287     noResponseCycles = 0;
 288     delete state;
 289     delete [] data;
 290     delete pkt->req;
 291     delete pkt;
 292 }
 293
 294 void
 295 MemTest::regStats()
 296 {
 297     using namespace Stats;
 298
 299     numReadsStat
 300         .name(name() + ".num_reads")
 301         .desc("number of read accesses completed")
 302         ;
 303
 304     numWritesStat
 305         .name(name() + ".num_writes")
 306         .desc("number of write accesses completed")
 307         ;
 308
 309     numCopiesStat
 310         .name(name() + ".num_copies")
 311         .desc("number of copy accesses completed")
 312         ;
 313 }
 314
 315 void
 316 MemTest::tick()
 317 {
 318     if (!tickEvent.scheduled())
 319         tickEvent.schedule(curTick + cycles(1));
 320
 321     if (++noResponseCycles >= 500000) {
 322         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 323         fatal("");
 324     }
 325
 326     if (accessRetry) {
 327         return;
 328     }
 329
 330     //make new request
 331     unsigned cmd = random() % 100;
 332     unsigned offset = random() % size;
 333     unsigned base = random() % 2;
 334     uint64_t data = random();
 335     unsigned access_size = random() % 4;
 336     unsigned cacheable = random() % 100;
 337
 338     //If we aren't doing copies, use id as offset, and do a false sharing
 339     //mem tester
 340     //We can eliminate the lower bits of the offset, and then use the id
 341     //to offset within the blks
 342     offset &= ~63; //Not the low order bits
 343     offset += id;
 344     access_size = 0;
 345
 346     Request *req = new Request();
 347     uint32_t flags = 0;
 348     Addr paddr;
 349
 350     if (cacheable < percentUncacheable) {
 351         flags |= UNCACHEABLE;
 352         paddr = uncacheAddr + offset;
 353     } else {
 354         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
 355     }
 356     bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
 357     //bool probe = false;
 358
 359     paddr &= ~((1 << access_size) - 1);
 360     req->setPhys(paddr, 1 << access_size, flags);
 361     req->setThreadContext(id,0);
 362
 363     uint8_t *result = new uint8_t[8];
 364
 365     if (cmd < percentReads) {
 366         // read
 367
 368         //For now we only allow one outstanding request per addreess per tester
 369         //This means we assume CPU does write forwarding to reads that alias something
 370         //in the cpu store buffer.
 371         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
 372             delete [] result;
 373             delete req;
 374             return;
 375         }
 376         else outstandingAddrs.insert(paddr);
 377
 378         // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
 379         funcPort.readBlob(req->getPaddr(), result, req->getSize());
 380
 381         if (blockAddr(paddr) == traceBlockAddr) {
 382             cerr << name()
 383                  << ": initiating read "
 384                  << ((probe) ? "probe of " : "access of ")
 385                  << dec << req->getSize() << " bytes from addr 0x"
 386                  << hex << paddr
 387                  << " (0x" << hex << blockAddr(paddr) << ")"
 388                  << " at cycle "
 389                  << dec << curTick << endl;
 390         }
 391
 392         PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
 393         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
 394         MemTestSenderState *state = new MemTestSenderState(result);
 395         pkt->senderState = state;
 396
 397         if (probe) {
 398             cachePort.sendFunctional(pkt);
 399             pkt->makeAtomicResponse();
 400             completeRequest(pkt);
 401         } else {
 402 //          req->completionEvent = new MemCompleteEvent(req, result, this);
 403             sendPkt(pkt);
 404         }
 405     } else {
 406         // write
 407
 408         //For now we only allow one outstanding request per addreess per tester
 409         //This means we assume CPU does write forwarding to reads that alias something
 410         //in the cpu store buffer.
 411         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
 412             delete [] result;
 413             delete req;
 414             return;
 415         }
 416
 417         else outstandingAddrs.insert(paddr);
 418
 419 /*
 420         if (blockAddr(req->getPaddr()) == traceBlockAddr) {
 421             cerr << name() << ": initiating write "
 422                  << ((probe)?"probe of ":"access of ")
 423                  << dec << req->getSize() << " bytes (value = 0x";
 424             printData(cerr, data_pkt->getPtr(), req->getSize());
 425             cerr << ") to addr 0x"
 426                  << hex << req->getPaddr()
 427                  << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
 428                  << " at cycle "
 429                  << dec << curTick << endl;
 430         }
 431 */
 432         PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
 433         uint8_t *pkt_data = new uint8_t[req->getSize()];
 434         pkt->dataDynamicArray(pkt_data);
 435         memcpy(pkt_data, &data, req->getSize());
 436         MemTestSenderState *state = new MemTestSenderState(result);
 437         pkt->senderState = state;
 438
 439         funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
 440
 441         if (probe) {
 442             cachePort.sendFunctional(pkt);
 443             pkt->makeAtomicResponse();
 444             completeRequest(pkt);
 445         } else {
 446 //          req->completionEvent = new MemCompleteEvent(req, NULL, this);
 447             sendPkt(pkt);
 448         }
 449     }
 450 /*    else {
 451         // copy
 452         unsigned source_align = random() % 100;
 453         unsigned dest_align = random() % 100;
 454         unsigned offset2 = random() % size;
 455
 456         Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
 457         Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
 458         if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
 459         else outstandingAddrs.insert(source);
 460         if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
 461         else outstandingAddrs.insert(dest);
 462
 463         if (source_align >= percentSourceUnaligned) {
 464             source = blockAddr(source);
 465         }
 466         if (dest_align >= percentDestUnaligned) {
 467             dest = blockAddr(dest);
 468         }
 469         req->cmd = Copy;
 470         req->flags &= ~UNCACHEABLE;
 471         req->paddr = source;
 472         req->dest = dest;
 473         delete [] req->data;
 474         req->data = new uint8_t[blockSize];
 475         req->size = blockSize;
 476         if (source == traceBlockAddr || dest == traceBlockAddr) {
 477             cerr << name()
 478                  << ": initiating copy of "
 479                  << dec << req->size << " bytes from addr 0x"
 480                  << hex << source
 481                  << " (0x" << hex << blockAddr(source) << ")"
 482                  << " to addr 0x"
 483                  << hex << dest
 484                  << " (0x" << hex << blockAddr(dest) << ")"
 485                  << " at cycle "
 486                  << dec << curTick << endl;
 487         }*
 488         cacheInterface->access(req);
 489         uint8_t result[blockSize];
 490         checkMem->access(Read, source, &result, blockSize);
 491         checkMem->access(Write, dest, &result, blockSize);
 492     }
 493 */
 494 }
 495
 496 void
 497 MemTest::doRetry()
 498 {
 499     if (cachePort.sendTiming(retryPkt)) {
 500         accessRetry = false;
 501         retryPkt = NULL;
 502     }
 503 }
 504
 505 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 506
 507 //    SimObjectParam<BaseCache *> cache;
 508 //    SimObjectParam<PhysicalMemory *> main_mem;
 509 //    SimObjectParam<PhysicalMemory *> check_mem;
 510     Param<unsigned> memory_size;
 511     Param<unsigned> percent_reads;
 512     Param<unsigned> percent_functional;
 513     Param<unsigned> percent_uncacheable;
 514     Param<unsigned> progress_interval;
 515     Param<unsigned> percent_source_unaligned;
 516     Param<unsigned> percent_dest_unaligned;
 517     Param<Addr> trace_addr;
 518     Param<Counter> max_loads;
 519     Param<bool> atomic;
 520
 521 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 522
 523
 524 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 525
 526 //    INIT_PARAM(cache, "L1 cache"),
 527 //    INIT_PARAM(main_mem, "hierarchical memory"),
 528 //    INIT_PARAM(check_mem, "check memory"),
 529     INIT_PARAM(memory_size, "memory size"),
 530     INIT_PARAM(percent_reads, "target read percentage"),
 531     INIT_PARAM(percent_functional, "percentage of access that are functional"),
 532     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
 533     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
 534     INIT_PARAM(percent_source_unaligned,
 535                "percent of copy source address that are unaligned"),
 536     INIT_PARAM(percent_dest_unaligned,
 537                "percent of copy dest address that are unaligned"),
 538     INIT_PARAM(trace_addr, "address to trace"),
 539                               INIT_PARAM(max_loads, "terminate when we have reached this load count"),
 540     INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
 541
 542 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 543
 544
 545 CREATE_SIM_OBJECT(MemTest)
 546 {
 547     return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
 548                        /*check_mem,*/ memory_size, percent_reads, percent_functional,
 549                        percent_uncacheable, progress_interval,
 550                        percent_source_unaligned, percent_dest_unaligned,
 551                        trace_addr, max_loads, atomic);
 552 }
 553
 554 REGISTER_SIM_OBJECT("MemTest", MemTest)