Merge ktlim@zizzer:/bk/newmem
[gem5.git] / src / cpu / memtest / memtest.hh
1 /*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32 #ifndef __CPU_MEMTEST_MEMTEST_HH__
33 #define __CPU_MEMTEST_MEMTEST_HH__
34
35 #include <set>
36
37 #include "base/statistics.hh"
38 //#include "mem/functional/functional.hh"
39 //#include "mem/mem_interface.hh"
40 #include "sim/eventq.hh"
41 #include "sim/sim_exit.hh"
42 #include "sim/sim_object.hh"
43 #include "sim/stats.hh"
44
45 class PhysicalMemory;
46 class ThreadContext;
47 class MemTest : public MemObject
48 {
49 public:
50
51 MemTest(const std::string &name,
52 // MemInterface *_cache_interface,
53 PhysicalMemory *main_mem,
54 PhysicalMemory *check_mem,
55 unsigned _memorySize,
56 unsigned _percentReads,
57 // unsigned _percentCopies,
58 unsigned _percentUncacheable,
59 unsigned _progressInterval,
60 unsigned _percentSourceUnaligned,
61 unsigned _percentDestUnaligned,
62 Addr _traceAddr,
63 Counter _max_loads);
64
65 virtual void init();
66
67 // register statistics
68 virtual void regStats();
69
70 inline Tick cycles(int numCycles) const { return numCycles; }
71
72 // main simulation loop (one cycle)
73 void tick();
74
75 virtual Port *getPort(const std::string &if_name, int idx = -1);
76
77 protected:
78 class TickEvent : public Event
79 {
80 private:
81 MemTest *cpu;
82 public:
83 TickEvent(MemTest *c)
84 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
85 void process() {cpu->tick();}
86 virtual const char *description() { return "tick event"; }
87 };
88
89 TickEvent tickEvent;
90 class CpuPort : public Port
91 {
92
93 MemTest *memtest;
94
95 public:
96
97 CpuPort(const std::string &_name, MemTest *_memtest)
98 : Port(_name), memtest(_memtest)
99 { }
100
101 protected:
102
103 virtual bool recvTiming(Packet *pkt);
104
105 virtual Tick recvAtomic(Packet *pkt);
106
107 virtual void recvFunctional(Packet *pkt);
108
109 virtual void recvStatusChange(Status status);
110
111 virtual void recvRetry();
112
113 virtual void getDeviceAddressRanges(AddrRangeList &resp,
114 AddrRangeList &snoop)
115 { resp.clear(); snoop.clear(); }
116 };
117
118 CpuPort cachePort;
119
120 class MemTestSenderState : public Packet::SenderState
121 {
122 public:
123 /** Constructor. */
124 MemTestSenderState(uint8_t *_data)
125 : data(_data)
126 { }
127
128 // Hold onto data pointer
129 uint8_t *data;
130 };
131
132 // Request *dataReq;
133 Packet *retryPkt;
134 // MemInterface *cacheInterface;
135 PhysicalMemory *mainMem;
136 PhysicalMemory *checkMem;
137 SimpleThread *thread;
138
139 bool accessRetry;
140
141 unsigned size; // size of testing memory region
142
143 unsigned percentReads; // target percentage of read accesses
144 // unsigned percentCopies; // target percentage of copy accesses
145 unsigned percentUncacheable;
146
147 int id;
148
149 std::set<unsigned> outstandingAddrs;
150
151 unsigned blockSize;
152
153 Addr blockAddrMask;
154
155 Addr blockAddr(Addr addr)
156 {
157 return (addr & ~blockAddrMask);
158 }
159
160 Addr traceBlockAddr;
161
162 Addr baseAddr1; // fix this to option
163 Addr baseAddr2; // fix this to option
164 Addr uncacheAddr;
165
166 unsigned progressInterval; // frequency of progress reports
167 Tick nextProgressMessage; // access # for next progress report
168
169 unsigned percentSourceUnaligned;
170 unsigned percentDestUnaligned;
171
172 Tick noResponseCycles;
173
174 uint64_t numReads;
175 uint64_t maxLoads;
176 Stats::Scalar<> numReadsStat;
177 Stats::Scalar<> numWritesStat;
178 Stats::Scalar<> numCopiesStat;
179
180 // called by MemCompleteEvent::process()
181 void completeRequest(Packet *pkt);
182
183 void doRetry();
184
185 friend class MemCompleteEvent;
186 };
187
188 #endif // __CPU_MEMTEST_MEMTEST_HH__
189
190
191