src/cpu/minor/MinorCPU.py

   1 # Copyright (c) 2012-2014, 2017-2018 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2007 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
  16 # Redistribution and use in source and binary forms, with or without
  17 # modification, are permitted provided that the following conditions are
  18 # met: redistributions of source code must retain the above copyright
  19 # notice, this list of conditions and the following disclaimer;
  20 # redistributions in binary form must reproduce the above copyright
  21 # notice, this list of conditions and the following disclaimer in the
  22 # documentation and/or other materials provided with the distribution;
  23 # neither the name of the copyright holders nor the names of its
  24 # contributors may be used to endorse or promote products derived from
  25 # this software without specific prior written permission.
  26 #
  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38
  39 from __future__ import print_function
  40
  41 from m5.defines import buildEnv
  42 from m5.params import *
  43 from m5.proxy import *
  44 from m5.SimObject import SimObject
  45 from m5.objects.BaseCPU import BaseCPU
  46 from m5.objects.DummyChecker import DummyChecker
  47 from m5.objects.BranchPredictor import *
  48 from m5.objects.TimingExpr import TimingExpr
  49
  50 from m5.objects.FuncUnit import OpClass
  51
  52 class MinorOpClass(SimObject):
  53     """Boxing of OpClass to get around build problems and provide a hook for
  54     future additions to OpClass checks"""
  55
  56     type = 'MinorOpClass'
  57     cxx_header = "cpu/minor/func_unit.hh"
  58
  59     opClass = Param.OpClass("op class to match")
  60
  61 class MinorOpClassSet(SimObject):
  62     """A set of matchable op classes"""
  63
  64     type = 'MinorOpClassSet'
  65     cxx_header = "cpu/minor/func_unit.hh"
  66
  67     opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
  68         "  An empty list means any class")
  69
  70 class MinorFUTiming(SimObject):
  71     type = 'MinorFUTiming'
  72     cxx_header = "cpu/minor/func_unit.hh"
  73
  74     mask = Param.UInt64(0, "mask for testing ExtMachInst")
  75     match = Param.UInt64(0, "match value for testing ExtMachInst:"
  76         " (ext_mach_inst & mask) == match")
  77     suppress = Param.Bool(False, "if true, this inst. is not executed by"
  78         " this FU")
  79     extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
  80         " this inst.")
  81     extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
  82         " run-time evaluated expression")
  83     extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
  84         " retire time for this insts dest registers once it leaves the"
  85         " functional unit.  For mem refs, if this is 0, the result's time"
  86         " is marked as unpredictable and no forwarding can take place.")
  87     srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
  88         " after inst. issue that each src reg can be available for this"
  89         " inst. to issue")
  90     opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
  91         "op classes to be considered for this decode.  An empty set means any"
  92         " class")
  93     description = Param.String('', "description string of the decoding/inst."
  94         " class")
  95
  96 def minorMakeOpClassSet(op_classes):
  97     """Make a MinorOpClassSet from a list of OpClass enum value strings"""
  98     def boxOpClass(op_class):
  99         return MinorOpClass(opClass=op_class)
 100
 101     return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ])
 102
 103 class MinorFU(SimObject):
 104     type = 'MinorFU'
 105     cxx_header = "cpu/minor/func_unit.hh"
 106
 107     opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
 108         " allowed on this functional unit")
 109     opLat = Param.Cycles(1, "latency in cycles")
 110     issueLat = Param.Cycles(1, "cycles until another instruction can be"
 111         " issued")
 112     timings = VectorParam.MinorFUTiming([], "extra decoding rules")
 113
 114     cantForwardFromFUIndices = VectorParam.Unsigned([],
 115         "list of FU indices from which this FU can't receive and early"
 116         " (forwarded) result")
 117
 118 class MinorFUPool(SimObject):
 119     type = 'MinorFUPool'
 120     cxx_header = "cpu/minor/func_unit.hh"
 121
 122     funcUnits = VectorParam.MinorFU("functional units")
 123
 124 class MinorDefaultIntFU(MinorFU):
 125     opClasses = minorMakeOpClassSet(['IntAlu'])
 126     timings = [MinorFUTiming(description="Int",
 127         srcRegsRelativeLats=[2])]
 128     opLat = 3
 129
 130 class MinorDefaultIntMulFU(MinorFU):
 131     opClasses = minorMakeOpClassSet(['IntMult'])
 132     timings = [MinorFUTiming(description='Mul',
 133         srcRegsRelativeLats=[0])]
 134     opLat = 3
 135
 136 class MinorDefaultIntDivFU(MinorFU):
 137     opClasses = minorMakeOpClassSet(['IntDiv'])
 138     issueLat = 9
 139     opLat = 9
 140
 141 class MinorDefaultFloatSimdFU(MinorFU):
 142     opClasses = minorMakeOpClassSet([
 143         'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
 144         'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
 145         'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
 146         'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
 147         'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
 148         'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
 149         'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu',
 150         'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
 151         'SimdAes', 'SimdAesMix',
 152         'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash',
 153         'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3'])
 154
 155     timings = [MinorFUTiming(description='FloatSimd',
 156         srcRegsRelativeLats=[2])]
 157     opLat = 6
 158
 159 class MinorDefaultPredFU(MinorFU):
 160     opClasses = minorMakeOpClassSet(['SimdPredAlu'])
 161     timings = [MinorFUTiming(description="Pred",
 162         srcRegsRelativeLats=[2])]
 163     opLat = 3
 164
 165 class MinorDefaultMemFU(MinorFU):
 166     opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
 167                                      'FloatMemWrite'])
 168     timings = [MinorFUTiming(description='Mem',
 169         srcRegsRelativeLats=[1], extraAssumedLat=2)]
 170     opLat = 1
 171
 172 class MinorDefaultMiscFU(MinorFU):
 173     opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
 174     opLat = 1
 175
 176 class MinorDefaultFUPool(MinorFUPool):
 177     funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
 178         MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
 179         MinorDefaultFloatSimdFU(), MinorDefaultPredFU(),
 180         MinorDefaultMemFU(), MinorDefaultMiscFU()]
 181
 182 class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
 183
 184 class MinorCPU(BaseCPU):
 185     type = 'MinorCPU'
 186     cxx_header = "cpu/minor/cpu.hh"
 187
 188     @classmethod
 189     def memory_mode(cls):
 190         return 'timing'
 191
 192     @classmethod
 193     def require_caches(cls):
 194         return True
 195
 196     @classmethod
 197     def support_take_over(cls):
 198         return True
 199
 200     threadPolicy = Param.ThreadPolicy('RoundRobin',
 201             "Thread scheduling policy")
 202     fetch1FetchLimit = Param.Unsigned(1,
 203         "Number of line fetches allowable in flight at once")
 204     fetch1LineSnapWidth = Param.Unsigned(0,
 205         "Fetch1 'line' fetch snap size in bytes"
 206         " (0 means use system cache line size)")
 207     fetch1LineWidth = Param.Unsigned(0,
 208         "Fetch1 maximum fetch size in bytes (0 means use system cache"
 209         " line size)")
 210     fetch1ToFetch2ForwardDelay = Param.Cycles(1,
 211         "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
 212     fetch1ToFetch2BackwardDelay = Param.Cycles(1,
 213         "Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
 214         " signalling (0 means in the same cycle, 1 mean the next cycle)")
 215
 216     fetch2InputBufferSize = Param.Unsigned(2,
 217         "Size of input buffer to Fetch2 in cycles-worth of insts.")
 218     fetch2ToDecodeForwardDelay = Param.Cycles(1,
 219         "Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
 220     fetch2CycleInput = Param.Bool(True,
 221         "Allow Fetch2 to cross input lines to generate full output each"
 222         " cycle")
 223
 224     decodeInputBufferSize = Param.Unsigned(3,
 225         "Size of input buffer to Decode in cycles-worth of insts.")
 226     decodeToExecuteForwardDelay = Param.Cycles(1,
 227         "Forward cycle delay from Decode to Execute (1 means next cycle)")
 228     decodeInputWidth = Param.Unsigned(2,
 229         "Width (in instructions) of input to Decode (and implicitly"
 230         " Decode's own width)")
 231     decodeCycleInput = Param.Bool(True,
 232         "Allow Decode to pack instructions from more than one input cycle"
 233         " to fill its output each cycle")
 234
 235     executeInputWidth = Param.Unsigned(2,
 236         "Width (in instructions) of input to Execute")
 237     executeCycleInput = Param.Bool(True,
 238         "Allow Execute to use instructions from more than one input cycle"
 239         " each cycle")
 240     executeIssueLimit = Param.Unsigned(2,
 241         "Number of issuable instructions in Execute each cycle")
 242     executeMemoryIssueLimit = Param.Unsigned(1,
 243         "Number of issuable memory instructions in Execute each cycle")
 244     executeCommitLimit = Param.Unsigned(2,
 245         "Number of committable instructions in Execute each cycle")
 246     executeMemoryCommitLimit = Param.Unsigned(1,
 247         "Number of committable memory references in Execute each cycle")
 248     executeInputBufferSize = Param.Unsigned(7,
 249         "Size of input buffer to Execute in cycles-worth of insts.")
 250     executeMemoryWidth = Param.Unsigned(0,
 251         "Width (and snap) in bytes of the data memory interface. (0 mean use"
 252         " the system cacheLineSize)")
 253     executeMaxAccessesInMemory = Param.Unsigned(2,
 254         "Maximum number of concurrent accesses allowed to the memory system"
 255         " from the dcache port")
 256     executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
 257         "Maximum number of stores that the store buffer can issue per cycle")
 258     executeLSQRequestsQueueSize = Param.Unsigned(1,
 259         "Size of LSQ requests queue (address translation queue)")
 260     executeLSQTransfersQueueSize = Param.Unsigned(2,
 261         "Size of LSQ transfers queue (memory transaction queue)")
 262     executeLSQStoreBufferSize = Param.Unsigned(5,
 263         "Size of LSQ store buffer")
 264     executeBranchDelay = Param.Cycles(1,
 265         "Delay from Execute deciding to branch and Fetch1 reacting"
 266         " (1 means next cycle)")
 267
 268     executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
 269         "FUlines for this processor")
 270
 271     executeSetTraceTimeOnCommit = Param.Bool(True,
 272         "Set inst. trace times to be commit times")
 273     executeSetTraceTimeOnIssue = Param.Bool(False,
 274         "Set inst. trace times to be issue times")
 275
 276     executeAllowEarlyMemoryIssue = Param.Bool(True,
 277         "Allow mem refs to be issued to the LSQ before reaching the head of"
 278         " the in flight insts queue")
 279
 280     enableIdling = Param.Bool(True,
 281         "Enable cycle skipping when the processor is idle\n");
 282
 283     branchPred = Param.BranchPredictor(TournamentBP(
 284         numThreads = Parent.numThreads), "Branch Predictor")
 285
 286     def addCheckerCpu(self):
 287         print("Checker not yet supported by MinorCPU")
 288         exit(1)