2 * Copyright (c) 2012-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "arch/utility.hh"
41 #include "cpu/minor/cpu.hh"
42 #include "cpu/minor/dyn_inst.hh"
43 #include "cpu/minor/fetch1.hh"
44 #include "cpu/minor/pipeline.hh"
45 #include "debug/Drain.hh"
46 #include "debug/MinorCPU.hh"
47 #include "debug/Quiesce.hh"
49 MinorCPU::MinorCPU(MinorCPUParams
*params
) :
52 /* This is only written for one thread at the moment */
53 Minor::MinorThread
*thread
;
56 thread
= new Minor::MinorThread(this, 0, params
->system
, params
->itb
,
57 params
->dtb
, params
->isa
[0]);
60 thread
= new Minor::MinorThread(this, 0, params
->system
,
61 params
->workload
[0], params
->itb
, params
->dtb
, params
->isa
[0]);
64 threads
.push_back(thread
);
66 thread
->setStatus(ThreadContext::Halted
);
68 ThreadContext
*tc
= thread
->getTC();
70 if (params
->checker
) {
71 fatal("The Minor model doesn't support checking (yet)\n");
74 threadContexts
.push_back(tc
);
76 Minor::MinorDynInst::init();
78 pipeline
= new Minor::Pipeline(*this, *params
);
79 activityRecorder
= pipeline
->getActivityRecorder();
86 for (ThreadID thread_id
= 0; thread_id
< threads
.size(); thread_id
++) {
87 delete threads
[thread_id
];
96 if (!params()->switched_out
&&
97 system
->getMemoryMode() != Enums::timing
)
99 fatal("The Minor CPU requires the memory system to be in "
103 /* Initialise the ThreadContext's memory proxies */
104 for (ThreadID thread_id
= 0; thread_id
< threads
.size(); thread_id
++) {
105 ThreadContext
*tc
= getContext(thread_id
);
107 tc
->initMemProxies(tc
);
110 /* Initialise CPUs (== threads in the ISA) */
111 if (FullSystem
&& !params()->switched_out
) {
112 for (ThreadID thread_id
= 0; thread_id
< threads
.size(); thread_id
++)
114 ThreadContext
*tc
= getContext(thread_id
);
116 /* Initialize CPU, including PC */
117 TheISA::initCPU(tc
, cpuId());
122 /** Stats interface from SimObject (by way of BaseCPU) */
127 stats
.regStats(name(), *this);
128 pipeline
->regStats();
132 MinorCPU::serializeThread(CheckpointOut
&cp
, ThreadID thread_id
) const
134 threads
[thread_id
]->serialize(cp
);
138 MinorCPU::unserializeThread(CheckpointIn
&cp
, ThreadID thread_id
)
141 fatal("Trying to load more than one thread into a MinorCPU\n");
143 threads
[thread_id
]->unserialize(cp
);
147 MinorCPU::serialize(CheckpointOut
&cp
) const
149 pipeline
->serialize(cp
);
150 BaseCPU::serialize(cp
);
154 MinorCPU::unserialize(CheckpointIn
&cp
)
156 pipeline
->unserialize(cp
);
157 BaseCPU::unserialize(cp
);
161 MinorCPU::dbg_vtophys(Addr addr
)
163 /* Note that this gives you the translation for thread 0 */
164 panic("No implementation for vtophy\n");
170 MinorCPU::wakeup(ThreadID tid
)
172 DPRINTF(Drain
, "[tid:%d] MinorCPU wakeup\n", tid
);
174 if (threads
[tid
]->status() == ThreadContext::Suspended
)
175 threads
[tid
]->activate();
177 DPRINTF(Drain
,"Suspended Processor awoke\n");
183 DPRINTF(MinorCPU
, "MinorCPU startup\n");
187 for (auto i
= threads
.begin(); i
!= threads
.end(); i
++)
190 /* Workaround cases in SE mode where a thread is activated with an
191 * incorrect PC that is updated after the call to activate. This
192 * causes problems for Minor since it instantiates a virtual
193 * branch instruction when activateContext() is called which ends
194 * up pointing to an illegal address. */
195 if (threads
[0]->status() == ThreadContext::Active
)
203 DPRINTF(Drain
, "Minor CPU switched out, draining not needed.\n");
204 return DrainState::Drained
;
207 DPRINTF(Drain
, "MinorCPU drain\n");
209 /* Need to suspend all threads and wait for Execute to idle.
210 * Tell Fetch1 not to fetch */
211 if (pipeline
->drain()) {
212 DPRINTF(Drain
, "MinorCPU drained\n");
213 return DrainState::Drained
;
215 DPRINTF(Drain
, "MinorCPU not finished draining\n");
216 return DrainState::Draining
;
221 MinorCPU::signalDrainDone()
223 DPRINTF(Drain
, "MinorCPU drain done\n");
224 Drainable::signalDrainDone();
228 MinorCPU::drainResume()
230 /* When taking over from another cpu make sure lastStopped
231 * is reset since it might have not been defined previously
232 * and might lead to a stats corruption */
233 pipeline
->resetLastStopped();
236 DPRINTF(Drain
, "drainResume while switched out. Ignoring\n");
240 DPRINTF(Drain
, "MinorCPU drainResume\n");
242 if (!system
->isTimingMode()) {
243 fatal("The Minor CPU requires the memory system to be in "
247 for (ThreadID tid
= 0; tid
< numThreads
; tid
++)
249 pipeline
->drainResume();
253 MinorCPU::memWriteback()
255 DPRINTF(Drain
, "MinorCPU memWriteback\n");
259 MinorCPU::switchOut()
261 DPRINTF(MinorCPU
, "MinorCPU switchOut\n");
263 assert(!switchedOut());
264 BaseCPU::switchOut();
266 /* Check that the CPU is drained? */
267 activityRecorder
->reset();
271 MinorCPU::takeOverFrom(BaseCPU
*old_cpu
)
273 DPRINTF(MinorCPU
, "MinorCPU takeOverFrom\n");
275 BaseCPU::takeOverFrom(old_cpu
);
279 MinorCPU::activateContext(ThreadID thread_id
)
281 DPRINTF(MinorCPU
, "ActivateContext thread: %d", thread_id
);
283 /* Do some cycle accounting. lastStopped is reset to stop the
284 * wakeup call on the pipeline from adding the quiesce period
285 * to BaseCPU::numCycles */
286 stats
.quiesceCycles
+= pipeline
->cyclesSinceLastStopped();
287 pipeline
->resetLastStopped();
289 /* Wake up the thread, wakeup the pipeline tick */
290 threads
[thread_id
]->activate();
291 wakeupOnEvent(Minor::Pipeline::CPUStageId
);
292 pipeline
->wakeupFetch();
294 BaseCPU::activateContext(thread_id
);
298 MinorCPU::suspendContext(ThreadID thread_id
)
300 DPRINTF(MinorCPU
, "SuspendContext %d\n", thread_id
);
302 threads
[thread_id
]->suspend();
304 BaseCPU::suspendContext(thread_id
);
308 MinorCPU::wakeupOnEvent(unsigned int stage_id
)
310 DPRINTF(Quiesce
, "Event wakeup from stage %d\n", stage_id
);
312 /* Mark that some activity has taken place and start the pipeline */
313 activityRecorder
->activateStage(stage_id
);
318 MinorCPUParams::create()
321 if (!FullSystem
&& workload
.size() != 1)
322 panic("only one workload allowed");
323 return new MinorCPU(this);
326 MasterPort
&MinorCPU::getInstPort()
328 return pipeline
->getInstPort();
331 MasterPort
&MinorCPU::getDataPort()
333 return pipeline
->getDataPort();
337 MinorCPU::totalInsts() const
341 for (auto i
= threads
.begin(); i
!= threads
.end(); i
++)
342 ret
+= (*i
)->numInst
;
348 MinorCPU::totalOps() const
352 for (auto i
= threads
.begin(); i
!= threads
.end(); i
++)