src/cpu/minor/cpu.hh

   1 /*
   2  * Copyright (c) 2012-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andrew Bardsley
  38  */
  39
  40 /**
  41  * @file
  42  *
  43  *  Top level definition of the Minor in-order CPU model
  44  */
  45
  46 #ifndef __CPU_MINOR_CPU_HH__
  47 #define __CPU_MINOR_CPU_HH__
  48
  49 #include "cpu/minor/activity.hh"
  50 #include "cpu/minor/stats.hh"
  51 #include "cpu/base.hh"
  52 #include "cpu/simple_thread.hh"
  53 #include "params/MinorCPU.hh"
  54
  55 namespace Minor
  56 {
  57 /** Forward declared to break the cyclic inclusion dependencies between
  58  *  pipeline and cpu */
  59 class Pipeline;
  60
  61 /** Minor will use the SimpleThread state for now */
  62 typedef SimpleThread MinorThread;
  63 };
  64
  65 /**
  66  *  MinorCPU is an in-order CPU model with four fixed pipeline stages:
  67  *
  68  *  Fetch1 - fetches lines from memory
  69  *  Fetch2 - decomposes lines into macro-op instructions
  70  *  Decode - decomposes macro-ops into micro-ops
  71  *  Execute - executes those micro-ops
  72  *
  73  *  This pipeline is carried in the MinorCPU::pipeline object.
  74  *  The exec_context interface is not carried by MinorCPU but by
  75  *      Minor::ExecContext objects
  76  *  created by Minor::Execute.
  77  */
  78 class MinorCPU : public BaseCPU
  79 {
  80   protected:
  81     /** Event for delayed wakeup of a thread */
  82     class ThreadActivateEvent : public Event
  83     {
  84       public:
  85         MinorCPU &cpu;
  86         ThreadID thread_id;
  87
  88         ThreadActivateEvent(MinorCPU &cpu_, ThreadID thread_id_) :
  89             cpu(cpu_), thread_id(thread_id_)
  90         { }
  91
  92         void process();
  93     };
  94
  95     /** Events to wakeup each thread */
  96     std::vector<ThreadActivateEvent *> threadActivateEvents;
  97
  98     /** pipeline is a container for the clockable pipeline stage objects.
  99      *  Elements of pipeline call TheISA to implement the model. */
 100     Minor::Pipeline *pipeline;
 101
 102   public:
 103     /** Activity recording for pipeline.  This belongs to Pipeline but
 104      *  stages will access it through the CPU as the MinorCPU object
 105      *  actually mediates idling behaviour */
 106     Minor::MinorActivityRecorder *activityRecorder;
 107
 108     /** These are thread state-representing objects for this CPU.  If
 109      *  you need a ThreadContext for *any* reason, use
 110      *  threads[threadId]->getTC() */
 111     std::vector<Minor::MinorThread *> threads;
 112
 113   public:
 114     /** Provide a non-protected base class for Minor's Ports as derived
 115      *  classes are created by Fetch1 and Execute */
 116     class MinorCPUPort : public MasterPort
 117     {
 118       public:
 119         /** The enclosing cpu */
 120         MinorCPU &cpu;
 121
 122       public:
 123         MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
 124             : MasterPort(name_, &cpu_), cpu(cpu_)
 125         { }
 126
 127       protected:
 128         /** Snooping a coherence request, do nothing.  */
 129         virtual void recvTimingSnoopReq(PacketPtr pkt) { }
 130     };
 131
 132     /** The DrainManager passed into drain that needs be signalled when
 133      *  draining is complete */
 134     DrainManager *drainManager;
 135
 136   protected:
 137      /** Return a reference to the data port. */
 138     MasterPort &getDataPort();
 139
 140     /** Return a reference to the instruction port. */
 141     MasterPort &getInstPort();
 142
 143   public:
 144     MinorCPU(MinorCPUParams *params);
 145
 146     ~MinorCPU();
 147
 148   public:
 149     /** Starting, waking and initialisation */
 150     void init();
 151     void startup();
 152     void wakeup();
 153
 154     Addr dbg_vtophys(Addr addr);
 155
 156     /** Processor-specific statistics */
 157     Minor::MinorStats stats;
 158
 159     /** Stats interface from SimObject (by way of BaseCPU) */
 160     void regStats();
 161
 162     /** Simple inst count interface from BaseCPU */
 163     Counter totalInsts() const;
 164     Counter totalOps() const;
 165
 166     void serializeThread(std::ostream &os, ThreadID thread_id);
 167     void unserializeThread(Checkpoint *cp, const std::string &section,
 168         ThreadID thread_id);
 169
 170     /** Serialize pipeline data */
 171     void serialize(std::ostream &os);
 172     void unserialize(Checkpoint *cp, const std::string &section);
 173
 174     /** Drain interface */
 175     unsigned int drain(DrainManager *drain_manager);
 176     void drainResume();
 177     /** Signal from Pipeline that MinorCPU should signal the DrainManager
 178      *  that a drain is complete and set its drainState */
 179     void signalDrainDone();
 180     void memWriteback();
 181
 182     /** Switching interface from BaseCPU */
 183     void switchOut();
 184     void takeOverFrom(BaseCPU *old_cpu);
 185
 186     /** Thread activation interface from BaseCPU. */
 187     void activateContext(ThreadID thread_id, Cycles delay);
 188     void suspendContext(ThreadID thread_id);
 189
 190     /** Interface for stages to signal that they have become active after
 191      *  a callback or eventq event where the pipeline itself may have
 192      *  already been idled.  The stage argument should be from the
 193      *  enumeration Pipeline::StageId */
 194     void wakeupOnEvent(unsigned int stage_id);
 195 };
 196
 197 #endif /* __CPU_MINOR_CPU_HH__ */