src/cpu/minor/cpu.hh

   1 /*
   2  * Copyright (c) 2012-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /**
  39  * @file
  40  *
  41  *  Top level definition of the Minor in-order CPU model
  42  */
  43
  44 #ifndef __CPU_MINOR_CPU_HH__
  45 #define __CPU_MINOR_CPU_HH__
  46
  47 #include "cpu/minor/activity.hh"
  48 #include "cpu/minor/stats.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/simple_thread.hh"
  51 #include "enums/ThreadPolicy.hh"
  52 #include "params/MinorCPU.hh"
  53
  54 namespace Minor
  55 {
  56 /** Forward declared to break the cyclic inclusion dependencies between
  57  *  pipeline and cpu */
  58 class Pipeline;
  59
  60 /** Minor will use the SimpleThread state for now */
  61 typedef SimpleThread MinorThread;
  62 };
  63
  64 /**
  65  *  MinorCPU is an in-order CPU model with four fixed pipeline stages:
  66  *
  67  *  Fetch1 - fetches lines from memory
  68  *  Fetch2 - decomposes lines into macro-op instructions
  69  *  Decode - decomposes macro-ops into micro-ops
  70  *  Execute - executes those micro-ops
  71  *
  72  *  This pipeline is carried in the MinorCPU::pipeline object.
  73  *  The exec_context interface is not carried by MinorCPU but by
  74  *      Minor::ExecContext objects
  75  *  created by Minor::Execute.
  76  */
  77 class MinorCPU : public BaseCPU
  78 {
  79   protected:
  80     /** pipeline is a container for the clockable pipeline stage objects.
  81      *  Elements of pipeline call TheISA to implement the model. */
  82     Minor::Pipeline *pipeline;
  83
  84   public:
  85     /** Activity recording for pipeline.  This belongs to Pipeline but
  86      *  stages will access it through the CPU as the MinorCPU object
  87      *  actually mediates idling behaviour */
  88     Minor::MinorActivityRecorder *activityRecorder;
  89
  90     /** These are thread state-representing objects for this CPU.  If
  91      *  you need a ThreadContext for *any* reason, use
  92      *  threads[threadId]->getTC() */
  93     std::vector<Minor::MinorThread *> threads;
  94
  95   public:
  96     /** Provide a non-protected base class for Minor's Ports as derived
  97      *  classes are created by Fetch1 and Execute */
  98     class MinorCPUPort : public MasterPort
  99     {
 100       public:
 101         /** The enclosing cpu */
 102         MinorCPU &cpu;
 103
 104       public:
 105         MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
 106             : MasterPort(name_, &cpu_), cpu(cpu_)
 107         { }
 108
 109     };
 110
 111     /** Thread Scheduling Policy (RoundRobin, Random, etc) */
 112     Enums::ThreadPolicy threadPolicy;
 113   protected:
 114      /** Return a reference to the data port. */
 115     Port &getDataPort() override;
 116
 117     /** Return a reference to the instruction port. */
 118     Port &getInstPort() override;
 119
 120   public:
 121     MinorCPU(MinorCPUParams *params);
 122
 123     ~MinorCPU();
 124
 125   public:
 126     /** Starting, waking and initialisation */
 127     void init() override;
 128     void startup() override;
 129     void wakeup(ThreadID tid) override;
 130
 131     /** Processor-specific statistics */
 132     Minor::MinorStats stats;
 133
 134     /** Stats interface from SimObject (by way of BaseCPU) */
 135     void regStats() override;
 136
 137     /** Simple inst count interface from BaseCPU */
 138     Counter totalInsts() const override;
 139     Counter totalOps() const override;
 140
 141     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 142     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 143
 144     /** Serialize pipeline data */
 145     void serialize(CheckpointOut &cp) const override;
 146     void unserialize(CheckpointIn &cp) override;
 147
 148     /** Drain interface */
 149     DrainState drain() override;
 150     void drainResume() override;
 151     /** Signal from Pipeline that MinorCPU should signal that a drain
 152      *  is complete and set its drainState */
 153     void signalDrainDone();
 154     void memWriteback() override;
 155
 156     /** Switching interface from BaseCPU */
 157     void switchOut() override;
 158     void takeOverFrom(BaseCPU *old_cpu) override;
 159
 160     /** Thread activation interface from BaseCPU. */
 161     void activateContext(ThreadID thread_id) override;
 162     void suspendContext(ThreadID thread_id) override;
 163
 164     /** Thread scheduling utility functions */
 165     std::vector<ThreadID> roundRobinPriority(ThreadID priority)
 166     {
 167         std::vector<ThreadID> prio_list;
 168         for (ThreadID i = 1; i <= numThreads; i++) {
 169             prio_list.push_back((priority + i) % numThreads);
 170         }
 171         return prio_list;
 172     }
 173
 174     std::vector<ThreadID> randomPriority()
 175     {
 176         std::vector<ThreadID> prio_list;
 177         for (ThreadID i = 0; i < numThreads; i++) {
 178             prio_list.push_back(i);
 179         }
 180         std::random_shuffle(prio_list.begin(), prio_list.end());
 181         return prio_list;
 182     }
 183
 184     /** Interface for stages to signal that they have become active after
 185      *  a callback or eventq event where the pipeline itself may have
 186      *  already been idled.  The stage argument should be from the
 187      *  enumeration Pipeline::StageId */
 188     void wakeupOnEvent(unsigned int stage_id);
 189 };
 190
 191 #endif /* __CPU_MINOR_CPU_HH__ */