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41 * Authors: Steve Reinhardt
50 * ExecContext bears the exec_context interface for Minor.
53 #ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54 #define __CPU_MINOR_EXEC_CONTEXT_HH__
56 #include "cpu/exec_context.hh"
57 #include "cpu/minor/execute.hh"
58 #include "cpu/minor/pipeline.hh"
59 #include "cpu/base.hh"
60 #include "cpu/simple_thread.hh"
61 #include "mem/request.hh"
62 #include "debug/MinorExecute.hh"
67 /* Forward declaration of Execute */
70 /** ExecContext bears the exec_context interface for Minor. This nicely
71 * separates that interface from other classes such as Pipeline, MinorCPU
72 * and DynMinorInst and makes it easier to see what state is accessed by it.
74 class ExecContext : public ::ExecContext
79 /** ThreadState object, provides all the architectural state. */
82 /** The execute stage so we can peek at its contents. */
85 /** Instruction for the benefit of memory operations and for PC */
90 SimpleThread &thread_, Execute &execute_,
91 MinorDynInstPtr inst_) :
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
100 thread.setIntReg(TheISA::ZeroReg, 0);
101 #if THE_ISA == ALPHA_ISA
102 thread.setFloatReg(TheISA::ZeroReg, 0.0);
107 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL);
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
125 readIntRegOperand(const StaticInst *si, int idx) override
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
133 readFloatRegOperand(const StaticInst *si, int idx) override
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatReg(reg.index());
141 readFloatRegOperandBits(const StaticInst *si, int idx) override
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isFloatReg());
145 return thread.readFloatRegBits(reg.index());
148 const TheISA::VecRegContainer&
149 readVecRegOperand(const StaticInst *si, int idx) const override
151 const RegId& reg = si->srcRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.readVecReg(reg);
156 TheISA::VecRegContainer&
157 getWritableVecRegOperand(const StaticInst *si, int idx) override
159 const RegId& reg = si->destRegIdx(idx);
160 assert(reg.isVecReg());
161 return thread.getWritableVecReg(reg);
165 readVecElemOperand(const StaticInst *si, int idx) const override
167 const RegId& reg = si->srcRegIdx(idx);
168 assert(reg.isVecReg());
169 return thread.readVecElem(reg);
173 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isIntReg());
177 thread.setIntReg(reg.index(), val);
181 setFloatRegOperand(const StaticInst *si, int idx,
182 TheISA::FloatReg val) override
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isFloatReg());
186 thread.setFloatReg(reg.index(), val);
190 setFloatRegOperandBits(const StaticInst *si, int idx,
191 TheISA::FloatRegBits val) override
193 const RegId& reg = si->destRegIdx(idx);
194 assert(reg.isFloatReg());
195 thread.setFloatRegBits(reg.index(), val);
199 setVecRegOperand(const StaticInst *si, int idx,
200 const TheISA::VecRegContainer& val) override
202 const RegId& reg = si->destRegIdx(idx);
203 assert(reg.isVecReg());
204 thread.setVecReg(reg, val);
207 /** Vector Register Lane Interfaces. */
209 /** Reads source vector 8bit operand. */
211 readVec8BitLaneOperand(const StaticInst *si, int idx) const
214 const RegId& reg = si->srcRegIdx(idx);
215 assert(reg.isVecReg());
216 return thread.readVec8BitLaneReg(reg);
219 /** Reads source vector 16bit operand. */
221 readVec16BitLaneOperand(const StaticInst *si, int idx) const
224 const RegId& reg = si->srcRegIdx(idx);
225 assert(reg.isVecReg());
226 return thread.readVec16BitLaneReg(reg);
229 /** Reads source vector 32bit operand. */
231 readVec32BitLaneOperand(const StaticInst *si, int idx) const
234 const RegId& reg = si->srcRegIdx(idx);
235 assert(reg.isVecReg());
236 return thread.readVec32BitLaneReg(reg);
239 /** Reads source vector 64bit operand. */
241 readVec64BitLaneOperand(const StaticInst *si, int idx) const
244 const RegId& reg = si->srcRegIdx(idx);
245 assert(reg.isVecReg());
246 return thread.readVec64BitLaneReg(reg);
249 /** Write a lane of the destination vector operand. */
250 template <typename LD>
252 setVecLaneOperandT(const StaticInst *si, int idx,
255 const RegId& reg = si->destRegIdx(idx);
256 assert(reg.isVecReg());
257 return thread.setVecLane(reg, val);
260 setVecLaneOperand(const StaticInst *si, int idx,
261 const LaneData<LaneSize::Byte>& val) override
263 setVecLaneOperandT(si, idx, val);
266 setVecLaneOperand(const StaticInst *si, int idx,
267 const LaneData<LaneSize::TwoByte>& val) override
269 setVecLaneOperandT(si, idx, val);
272 setVecLaneOperand(const StaticInst *si, int idx,
273 const LaneData<LaneSize::FourByte>& val) override
275 setVecLaneOperandT(si, idx, val);
278 setVecLaneOperand(const StaticInst *si, int idx,
279 const LaneData<LaneSize::EightByte>& val) override
281 setVecLaneOperandT(si, idx, val);
286 setVecElemOperand(const StaticInst *si, int idx,
287 const TheISA::VecElem val) override
289 const RegId& reg = si->destRegIdx(idx);
290 assert(reg.isVecReg());
291 thread.setVecElem(reg, val);
295 readPredicate() override
297 return thread.readPredicate();
301 setPredicate(bool val) override
303 thread.setPredicate(val);
307 pcState() const override
309 return thread.pcState();
313 pcState(const TheISA::PCState &val) override
319 readMiscRegNoEffect(int misc_reg) const
321 return thread.readMiscRegNoEffect(misc_reg);
325 readMiscReg(int misc_reg) override
327 return thread.readMiscReg(misc_reg);
331 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
333 thread.setMiscReg(misc_reg, val);
337 readMiscRegOperand(const StaticInst *si, int idx) override
339 const RegId& reg = si->srcRegIdx(idx);
340 assert(reg.isMiscReg());
341 return thread.readMiscReg(reg.index());
345 setMiscRegOperand(const StaticInst *si, int idx,
346 const TheISA::MiscReg &val) override
348 const RegId& reg = si->destRegIdx(idx);
349 assert(reg.isMiscReg());
350 return thread.setMiscReg(reg.index(), val);
356 #if THE_ISA == ALPHA_ISA
357 return thread.hwrei();
364 simPalCheck(int palFunc) override
366 #if THE_ISA == ALPHA_ISA
367 return thread.simPalCheck(palFunc);
374 syscall(int64_t callnum, Fault *fault) override
377 panic("Syscall emulation isn't available in FS mode.\n");
379 thread.syscall(callnum, fault);
382 ThreadContext *tcBase() override { return thread.getTC(); }
384 /* @todo, should make stCondFailures persistent somewhere */
385 unsigned int readStCondFailures() const override { return 0; }
386 void setStCondFailures(unsigned int st_cond_failures) override {}
388 ContextID contextId() { return thread.contextId(); }
389 /* ISA-specific (or at least currently ISA singleton) functions */
391 /* X86: TLB twiddling */
393 demapPage(Addr vaddr, uint64_t asn) override
395 thread.getITBPtr()->demapPage(vaddr, asn);
396 thread.getDTBPtr()->demapPage(vaddr, asn);
400 readCCRegOperand(const StaticInst *si, int idx) override
402 const RegId& reg = si->srcRegIdx(idx);
403 assert(reg.isCCReg());
404 return thread.readCCReg(reg.index());
408 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
410 const RegId& reg = si->destRegIdx(idx);
411 assert(reg.isCCReg());
412 thread.setCCReg(reg.index(), val);
416 demapInstPage(Addr vaddr, uint64_t asn)
418 thread.getITBPtr()->demapPage(vaddr, asn);
422 demapDataPage(Addr vaddr, uint64_t asn)
424 thread.getDTBPtr()->demapPage(vaddr, asn);
427 /* ALPHA/POWER: Effective address storage */
428 void setEA(Addr ea) override
433 BaseCPU *getCpuPtr() { return &cpu; }
435 /* POWER: Effective address storage */
436 Addr getEA() const override
441 /* MIPS: other thread register reading/writing */
443 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
445 SimpleThread *other_thread = (tid == InvalidThreadID
446 ? &thread : cpu.threads[tid]);
448 switch (reg.classValue()) {
450 return other_thread->readIntReg(reg.index());
453 return other_thread->readFloatRegBits(reg.index());
456 return other_thread->readMiscReg(reg.index());
458 panic("Unexpected reg class! (%s)",
465 setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
466 ThreadID tid = InvalidThreadID)
468 SimpleThread *other_thread = (tid == InvalidThreadID
469 ? &thread : cpu.threads[tid]);
471 switch (reg.classValue()) {
473 return other_thread->setIntReg(reg.index(), val);
476 return other_thread->setFloatRegBits(reg.index(), val);
479 return other_thread->setMiscReg(reg.index(), val);
481 panic("Unexpected reg class! (%s)",
487 // monitor/mwait funtions
488 void armMonitor(Addr address) override
489 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
491 bool mwait(PacketPtr pkt) override
492 { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
494 void mwaitAtomic(ThreadContext *tc) override
495 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
497 AddressMonitor *getAddrMonitor() override
498 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
503 #endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */