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41 * Authors: Steve Reinhardt
50 * ExecContext bears the exec_context interface for Minor.
53 #ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54 #define __CPU_MINOR_EXEC_CONTEXT_HH__
56 #include "cpu/exec_context.hh"
57 #include "cpu/minor/execute.hh"
58 #include "cpu/minor/pipeline.hh"
59 #include "cpu/base.hh"
60 #include "cpu/simple_thread.hh"
61 #include "debug/MinorExecute.hh"
66 /* Forward declaration of Execute */
69 /** ExecContext bears the exec_context interface for Minor. This nicely
70 * separates that interface from other classes such as Pipeline, MinorCPU
71 * and DynMinorInst and makes it easier to see what state is accessed by it.
73 class ExecContext : public ::ExecContext
78 /** ThreadState object, provides all the architectural state. */
81 /** The execute stage so we can peek at its contents. */
84 /** Instruction for the benefit of memory operations and for PC */
89 SimpleThread &thread_, Execute &execute_,
90 MinorDynInstPtr inst_) :
96 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
99 thread.setIntReg(TheISA::ZeroReg, 0);
100 #if THE_ISA == ALPHA_ISA
101 thread.setFloatReg(TheISA::ZeroReg, 0.0);
106 initiateMemRead(Addr addr, unsigned int size, unsigned int flags)
108 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
109 size, addr, flags, NULL);
114 writeMem(uint8_t *data, unsigned int size, Addr addr,
115 unsigned int flags, uint64_t *res)
117 execute.getLSQ().pushRequest(inst, false /* store */, data,
118 size, addr, flags, res);
123 readIntRegOperand(const StaticInst *si, int idx)
125 return thread.readIntReg(si->srcRegIdx(idx));
129 readFloatRegOperand(const StaticInst *si, int idx)
131 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
132 return thread.readFloatReg(reg_idx);
136 readFloatRegOperandBits(const StaticInst *si, int idx)
138 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
139 return thread.readFloatRegBits(reg_idx);
143 setIntRegOperand(const StaticInst *si, int idx, IntReg val)
145 thread.setIntReg(si->destRegIdx(idx), val);
149 setFloatRegOperand(const StaticInst *si, int idx,
150 TheISA::FloatReg val)
152 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
153 thread.setFloatReg(reg_idx, val);
157 setFloatRegOperandBits(const StaticInst *si, int idx,
158 TheISA::FloatRegBits val)
160 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
161 thread.setFloatRegBits(reg_idx, val);
167 return thread.readPredicate();
171 setPredicate(bool val)
173 thread.setPredicate(val);
179 return thread.pcState();
183 pcState(const TheISA::PCState &val)
189 readMiscRegNoEffect(int misc_reg) const
191 return thread.readMiscRegNoEffect(misc_reg);
195 readMiscReg(int misc_reg)
197 return thread.readMiscReg(misc_reg);
201 setMiscReg(int misc_reg, const TheISA::MiscReg &val)
203 thread.setMiscReg(misc_reg, val);
207 readMiscRegOperand(const StaticInst *si, int idx)
209 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
210 return thread.readMiscReg(reg_idx);
214 setMiscRegOperand(const StaticInst *si, int idx,
215 const TheISA::MiscReg &val)
217 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
218 return thread.setMiscReg(reg_idx, val);
224 #if THE_ISA == ALPHA_ISA
225 return thread.hwrei();
232 simPalCheck(int palFunc)
234 #if THE_ISA == ALPHA_ISA
235 return thread.simPalCheck(palFunc);
242 syscall(int64_t callnum)
245 panic("Syscall emulation isn't available in FS mode.\n");
247 thread.syscall(callnum);
250 ThreadContext *tcBase() { return thread.getTC(); }
252 /* @todo, should make stCondFailures persistent somewhere */
253 unsigned int readStCondFailures() const { return 0; }
254 void setStCondFailures(unsigned int st_cond_failures) {}
256 ContextID contextId() { return thread.contextId(); }
257 /* ISA-specific (or at least currently ISA singleton) functions */
259 /* X86: TLB twiddling */
261 demapPage(Addr vaddr, uint64_t asn)
263 thread.getITBPtr()->demapPage(vaddr, asn);
264 thread.getDTBPtr()->demapPage(vaddr, asn);
268 readCCRegOperand(const StaticInst *si, int idx)
270 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
271 return thread.readCCReg(reg_idx);
275 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
277 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
278 thread.setCCReg(reg_idx, val);
282 demapInstPage(Addr vaddr, uint64_t asn)
284 thread.getITBPtr()->demapPage(vaddr, asn);
288 demapDataPage(Addr vaddr, uint64_t asn)
290 thread.getDTBPtr()->demapPage(vaddr, asn);
293 /* ALPHA/POWER: Effective address storage */
299 BaseCPU *getCpuPtr() { return &cpu; }
301 /* POWER: Effective address storage */
307 /* MIPS: other thread register reading/writing */
309 readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
311 SimpleThread *other_thread = (tid == InvalidThreadID
312 ? &thread : cpu.threads[tid]);
314 if (idx < TheISA::FP_Reg_Base) { /* Integer */
315 return other_thread->readIntReg(idx);
316 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
317 return other_thread->readFloatRegBits(idx
318 - TheISA::FP_Reg_Base);
320 return other_thread->readMiscReg(idx
321 - TheISA::Misc_Reg_Base);
326 setRegOtherThread(int idx, const TheISA::MiscReg &val,
327 ThreadID tid = InvalidThreadID)
329 SimpleThread *other_thread = (tid == InvalidThreadID
330 ? &thread : cpu.threads[tid]);
332 if (idx < TheISA::FP_Reg_Base) { /* Integer */
333 return other_thread->setIntReg(idx, val);
334 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
335 return other_thread->setFloatRegBits(idx
336 - TheISA::FP_Reg_Base, val);
338 return other_thread->setMiscReg(idx
339 - TheISA::Misc_Reg_Base, val);
344 // monitor/mwait funtions
345 void armMonitor(Addr address) { getCpuPtr()->armMonitor(0, address); }
346 bool mwait(PacketPtr pkt) { return getCpuPtr()->mwait(0, pkt); }
347 void mwaitAtomic(ThreadContext *tc)
348 { return getCpuPtr()->mwaitAtomic(0, tc, thread.dtb); }
349 AddressMonitor *getAddrMonitor()
350 { return getCpuPtr()->getCpuAddrMonitor(0); }
355 #endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */