2 * Copyright (c) 2013-2014,2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "cpu/minor/execute.hh"
42 #include "arch/locked_mem.hh"
43 #include "arch/registers.hh"
44 #include "arch/utility.hh"
45 #include "cpu/minor/cpu.hh"
46 #include "cpu/minor/exec_context.hh"
47 #include "cpu/minor/fetch1.hh"
48 #include "cpu/minor/lsq.hh"
49 #include "cpu/op_class.hh"
50 #include "debug/Activity.hh"
51 #include "debug/Branch.hh"
52 #include "debug/Drain.hh"
53 #include "debug/MinorExecute.hh"
54 #include "debug/MinorInterrupt.hh"
55 #include "debug/MinorMem.hh"
56 #include "debug/MinorTrace.hh"
57 #include "debug/PCEvent.hh"
62 Execute::Execute(const std::string
&name_
,
64 MinorCPUParams
¶ms
,
65 Latch
<ForwardInstData
>::Output inp_
,
66 Latch
<BranchData
>::Input out_
) :
71 issueLimit(params
.executeIssueLimit
),
72 memoryIssueLimit(params
.executeMemoryIssueLimit
),
73 commitLimit(params
.executeCommitLimit
),
74 memoryCommitLimit(params
.executeMemoryCommitLimit
),
75 processMoreThanOneInput(params
.executeCycleInput
),
76 fuDescriptions(*params
.executeFuncUnits
),
77 numFuncUnits(fuDescriptions
.funcUnits
.size()),
78 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
79 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
80 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
81 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
82 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
84 params
.executeMaxAccessesInMemory
,
85 params
.executeMemoryWidth
,
86 params
.executeLSQRequestsQueueSize
,
87 params
.executeLSQTransfersQueueSize
,
88 params
.executeLSQStoreBufferSize
,
89 params
.executeLSQMaxStoreBufferStoresPerCycle
),
90 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
95 if (commitLimit
< 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
100 if (issueLimit
< 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
105 if (memoryIssueLimit
< 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
110 if (memoryCommitLimit
> commitLimit
) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_
, memoryCommitLimit
, commitLimit
);
116 if (params
.executeInputBufferSize
< 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
118 params
.executeInputBufferSize
);
121 if (params
.executeInputBufferSize
< 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
123 params
.executeInputBufferSize
);
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
129 unsigned int total_slots
= 0;
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
133 std::ostringstream fu_name
;
134 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots
+= fu_description
->opLat
;
141 fu_name
<< name_
<< ".fu." << i
;
143 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
145 funcUnits
.push_back(fu
);
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
150 bool found_fu
= false;
151 unsigned int fu_index
= 0;
153 while (fu_index
< numFuncUnits
&& !found_fu
)
155 if (funcUnits
[fu_index
]->provides(
156 static_cast<OpClass
>(op_class
)))
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings
[op_class
]);
169 /* Per-thread structures */
170 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
171 std::string tid_str
= std::to_string(tid
);
174 inputBuffer
.push_back(
175 InputBuffer
<ForwardInstData
>(
176 name_
+ ".inputBuffer" + tid_str
, "insts",
177 params
.executeInputBufferSize
));
180 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
182 /* In-flight instruction records */
183 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
184 ReportTraitsAdaptor
<QueuedInst
> >(
185 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
187 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
188 ReportTraitsAdaptor
<QueuedInst
> >(
189 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
193 const ForwardInstData
*
194 Execute::getInput(ThreadID tid
)
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer
[tid
].empty()) {
198 const ForwardInstData
&head
= inputBuffer
[tid
].front();
200 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
207 Execute::popInput(ThreadID tid
)
209 if (!inputBuffer
[tid
].empty())
210 inputBuffer
[tid
].pop();
212 executeInfo
[tid
].inputIndex
= 0;
216 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
218 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
219 const TheISA::PCState
&pc_before
= inst
->pc
;
220 TheISA::PCState target
= thread
->pcState();
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
226 inst
->isLastOpInInst() &&
227 (inst
->staticInst
->isSerializeAfter() ||
228 inst
->staticInst
->isSquashAfter() ||
229 inst
->staticInst
->isIprAccess());
231 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
232 pc_before
, target
, (force_branch
? " (forcing)" : ""));
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch
= pc_before
!= target
||
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason
= BranchData::NoBranch
;
242 if (fault
== NoFault
)
244 TheISA::advancePC(target
, inst
->staticInst
);
245 thread
->pcState(target
);
247 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
251 if (inst
->predictedTaken
&& !force_branch
) {
252 /* Predicted to branch */
254 /* No branch was taken, change stream to get us back to the
255 * intended PC value */
256 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
257 " none happened inst: %s\n",
258 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
260 reason
= BranchData::BadlyPredictedBranch
;
261 } else if (inst
->predictedTarget
== target
) {
262 /* Branch prediction got the right target, kill the branch and
264 * Note that this information to the branch predictor might get
265 * overwritten by a "real" branch during this cycle */
266 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
268 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
270 reason
= BranchData::CorrectlyPredictedBranch
;
272 /* Branch prediction got the wrong target */
273 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
274 " but got the wrong target (actual: 0x%x) inst: %s\n",
275 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
276 target
.instAddr(), *inst
);
278 reason
= BranchData::BadlyPredictedBranchTarget
;
280 } else if (must_branch
) {
281 /* Unpredicted branch */
282 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
283 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
285 reason
= BranchData::UnpredictedBranch
;
287 /* No branch at all */
288 reason
= BranchData::NoBranch
;
291 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
295 Execute::updateBranchData(
297 BranchData::Reason reason
,
298 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
301 if (reason
!= BranchData::NoBranch
) {
302 /* Bump up the stream sequence number on a real branch*/
303 if (BranchData::isStreamChange(reason
))
304 executeInfo
[tid
].streamSeqNum
++;
306 /* Branches (even mis-predictions) don't change the predictionSeqNum,
307 * just the streamSeqNum */
308 branch
= BranchData(reason
, tid
,
309 executeInfo
[tid
].streamSeqNum
,
310 /* Maintaining predictionSeqNum if there's no inst is just a
311 * courtesy and looks better on minorview */
312 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
313 : inst
->id
.predictionSeqNum
),
316 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
321 Execute::handleMemResponse(MinorDynInstPtr inst
,
322 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
324 ThreadID thread_id
= inst
->id
.threadId
;
325 ThreadContext
*thread
= cpu
.getContext(thread_id
);
327 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
329 PacketPtr packet
= response
->packet
;
331 bool is_load
= inst
->staticInst
->isLoad();
332 bool is_store
= inst
->staticInst
->isStore();
333 bool is_atomic
= inst
->staticInst
->isAtomic();
334 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
336 /* If true, the trace's predicate value will be taken from the exec
337 * context predicate, otherwise, it will be set to false */
338 bool use_context_predicate
= true;
340 if (inst
->translationFault
!= NoFault
) {
341 /* Invoke memory faults. */
342 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
343 inst
->translationFault
->name());
345 if (inst
->staticInst
->isPrefetch()) {
346 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
347 inst
->translationFault
->name());
349 /* Don't assign to fault */
351 /* Take the fault raised during the TLB/memory access */
352 fault
= inst
->translationFault
;
354 fault
->invoke(thread
, inst
->staticInst
);
356 } else if (!packet
) {
357 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
359 use_context_predicate
= false;
360 if (!context
.readMemAccPredicate())
361 inst
->staticInst
->completeAcc(nullptr, &context
, inst
->traceData
);
362 } else if (packet
->isError()) {
363 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
366 fatal("Received error response packet for inst: %s\n", *inst
);
367 } else if (is_store
|| is_load
|| is_prefetch
|| is_atomic
) {
370 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
371 *inst
, packet
->getAddr(), packet
->getSize());
373 if (is_load
&& packet
->getSize() > 0) {
374 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
375 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
378 /* Complete the memory access instruction */
379 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
382 if (fault
!= NoFault
) {
383 /* Invoke fault created by instruction completion */
384 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
386 fault
->invoke(thread
, inst
->staticInst
);
388 /* Stores need to be pushed into the store buffer to finish
390 if (response
->needsToBeSentToStoreBuffer())
391 lsq
.sendStoreToStoreBuffer(response
);
394 fatal("There should only ever be reads, "
395 "writes or faults at this point\n");
398 lsq
.popResponse(response
);
400 if (inst
->traceData
) {
401 inst
->traceData
->setPredicate((use_context_predicate
?
402 context
.readPredicate() : false));
405 doInstCommitAccounting(inst
);
407 /* Generate output to account for branches */
408 tryToBranch(inst
, fault
, branch
);
412 Execute::isInterrupted(ThreadID thread_id
) const
414 return cpu
.checkInterrupts(cpu
.getContext(thread_id
));
418 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
420 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
421 cpu
.getContext(thread_id
)->pcState());
423 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt
424 (cpu
.getContext(thread_id
));
426 if (interrupt
!= NoFault
) {
427 /* The interrupt *must* set pcState */
428 cpu
.getInterruptController(thread_id
)->updateIntrInfo
429 (cpu
.getContext(thread_id
));
430 interrupt
->invoke(cpu
.getContext(thread_id
));
432 assert(!lsq
.accessesInFlight());
434 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
435 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
437 /* Assume that an interrupt *must* cause a branch. Assert this? */
439 updateBranchData(thread_id
, BranchData::Interrupt
,
440 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
444 return interrupt
!= NoFault
;
448 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
449 bool &passed_predicate
, Fault
&fault
)
453 /* Set to true if the mem op. is issued and sent to the mem system */
454 passed_predicate
= false;
456 if (!lsq
.canRequest()) {
457 /* Not acting on instruction yet as the memory
461 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
462 TheISA::PCState old_pc
= thread
->pcState();
464 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
467 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
469 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
473 if (init_fault
!= NoFault
) {
474 assert(inst
->translationFault
!= NoFault
);
475 // Translation faults are dealt with in handleMemResponse()
476 init_fault
= NoFault
;
478 // If we have a translation fault then it got suppressed by
480 inst
->translationFault
= NoFault
;
484 if (init_fault
!= NoFault
) {
485 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
486 " initiateAcc: %s\n", *inst
, init_fault
->name());
489 /* Only set this if the instruction passed its
491 if (!context
.readMemAccPredicate()) {
492 DPRINTF(MinorMem
, "No memory access for inst: %s\n", *inst
);
493 assert(context
.readPredicate());
495 passed_predicate
= context
.readPredicate();
497 /* Set predicate in tracing */
499 inst
->traceData
->setPredicate(passed_predicate
);
501 /* If the instruction didn't pass its predicate (and so will not
502 * progress from here) Try to branch to correct and branch
504 if (!passed_predicate
) {
505 /* Leave it up to commit to handle the fault */
506 lsq
.pushFailedRequest(inst
);
510 /* Restore thread PC */
511 thread
->pcState(old_pc
);
518 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
520 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
522 unsigned int ret
= index
+ 1;
524 if (ret
== cycle_size
)
530 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
532 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
537 ret
= cycle_size
- 1;
543 Execute::issue(ThreadID thread_id
)
545 const ForwardInstData
*insts_in
= getInput(thread_id
);
546 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
548 /* Early termination if we have no instructions */
552 /* Start from the first FU */
553 unsigned int fu_index
= 0;
555 /* Remains true while instructions are still being issued. If any
556 * instruction fails to issue, this is set to false and we exit issue.
557 * This strictly enforces in-order issue. For other issue behaviours,
558 * a more complicated test in the outer while loop below is needed. */
561 /* Number of insts issues this cycle to check for issueLimit */
562 unsigned num_insts_issued
= 0;
564 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
565 unsigned num_mem_insts_issued
= 0;
567 /* Number of instructions discarded this cycle in order to enforce a
568 * discardLimit. @todo, add that parameter? */
569 unsigned num_insts_discarded
= 0;
572 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
573 Fault fault
= inst
->fault
;
574 bool discarded
= false;
575 bool issued_mem_ref
= false;
577 if (inst
->isBubble()) {
580 } else if (cpu
.getContext(thread_id
)->status() ==
581 ThreadContext::Suspended
)
583 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
588 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
589 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
590 " state was unexpected, expected: %d\n",
591 *inst
, thread
.streamSeqNum
);
595 /* Try and issue an instruction into an FU, assume we didn't and
596 * fix that in the loop */
599 /* Try FU from 0 each instruction */
602 /* Try and issue a single instruction stepping through the
605 FUPipeline
*fu
= funcUnits
[fu_index
];
607 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
610 /* Does the examined fu have the OpClass-related capability
611 * needed to execute this instruction? Faults can always
612 * issue to any FU but probably should just 'live' in the
613 * inFlightInsts queue rather than having an FU. */
614 bool fu_is_capable
= (!inst
->isFault() ?
615 fu
->provides(inst
->staticInst
->opClass()) : true);
617 if (inst
->isNoCostInst()) {
618 /* Issue free insts. to a fake numbered FU */
619 fu_index
= noCostFUIndex
;
621 /* And start the countdown on activity to allow
622 * this instruction to get to the end of its FU */
623 cpu
.activityRecorder
->activity();
625 /* Mark the destinations for this instruction as
627 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
628 Cycles(0), cpu
.getContext(thread_id
), false);
630 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
631 inst
->fuIndex
= noCostFUIndex
;
632 inst
->extraCommitDelay
= Cycles(0);
633 inst
->extraCommitDelayExpr
= NULL
;
635 /* Push the instruction onto the inFlight queue so
636 * it can be committed in order */
637 QueuedInst
fu_inst(inst
);
638 thread
.inFlightInsts
->push(fu_inst
);
642 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
644 if (!fu_is_capable
) {
645 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
646 " capable\n", fu_index
);
648 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
649 " already busy\n", fu_index
);
651 } else if (fu
->stalled
) {
652 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
655 } else if (!fu
->canInsert()) {
656 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
657 " for another: %d cycles\n",
658 *inst
, fu
->cyclesBeforeInsert());
660 MinorFUTiming
*timing
= (!inst
->isFault() ?
661 fu
->findTiming(inst
->staticInst
) : NULL
);
663 const std::vector
<Cycles
> *src_latencies
=
664 (timing
? &(timing
->srcRegsRelativeLats
)
667 const std::vector
<bool> *cant_forward_from_fu_indices
=
668 &(fu
->cantForwardFromFUIndices
);
670 if (timing
&& timing
->suppress
) {
671 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
672 " decoding is suppressing it\n",
674 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
675 src_latencies
, cant_forward_from_fu_indices
,
676 cpu
.curCycle(), cpu
.getContext(thread_id
)))
678 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
681 /* Can insert the instruction into this FU */
682 DPRINTF(MinorExecute
, "Issuing inst: %s"
683 " into FU %d\n", *inst
,
686 Cycles extra_dest_retire_lat
= Cycles(0);
687 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
688 Cycles extra_assumed_lat
= Cycles(0);
690 /* Add the extraCommitDelay and extraAssumeLat to
691 * the FU pipeline timings */
693 extra_dest_retire_lat
=
694 timing
->extraCommitLat
;
695 extra_dest_retire_lat_expr
=
696 timing
->extraCommitLatExpr
;
698 timing
->extraAssumedLat
;
701 issued_mem_ref
= inst
->isMemRef();
703 QueuedInst
fu_inst(inst
);
705 /* Decorate the inst with FU details */
706 inst
->fuIndex
= fu_index
;
707 inst
->extraCommitDelay
= extra_dest_retire_lat
;
708 inst
->extraCommitDelayExpr
=
709 extra_dest_retire_lat_expr
;
711 if (issued_mem_ref
) {
712 /* Remember which instruction this memory op
713 * depends on so that initiateAcc can be called
715 if (allowEarlyMemIssue
) {
716 inst
->instToWaitFor
=
717 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
718 cpu
.getContext(thread_id
));
720 if (lsq
.getLastMemBarrier(thread_id
) >
723 DPRINTF(MinorExecute
, "A barrier will"
724 " cause a delay in mem ref issue of"
725 " inst: %s until after inst"
726 " %d(exec)\n", *inst
,
727 lsq
.getLastMemBarrier(thread_id
));
729 inst
->instToWaitFor
=
730 lsq
.getLastMemBarrier(thread_id
);
732 DPRINTF(MinorExecute
, "Memory ref inst:"
733 " %s must wait for inst %d(exec)"
735 *inst
, inst
->instToWaitFor
);
738 inst
->canEarlyIssue
= true;
740 /* Also queue this instruction in the memory ref
741 * queue to ensure in-order issue to the LSQ */
742 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
744 thread
.inFUMemInsts
->push(fu_inst
);
749 /* And start the countdown on activity to allow
750 * this instruction to get to the end of its FU */
751 cpu
.activityRecorder
->activity();
753 /* Mark the destinations for this instruction as
755 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
756 fu
->description
.opLat
+
757 extra_dest_retire_lat
+
759 cpu
.getContext(thread_id
),
760 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
762 /* Push the instruction onto the inFlight queue so
763 * it can be committed in order */
764 thread
.inFlightInsts
->push(fu_inst
);
771 } while (fu_index
!= numFuncUnits
&& !issued
);
774 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
778 /* Generate MinorTrace's MinorInst lines. Do this at commit
779 * to allow better instruction annotation? */
780 if (DTRACE(MinorTrace
) && !inst
->isBubble())
781 inst
->minorTraceInst(*this);
783 /* Mark up barriers in the LSQ */
784 if (!discarded
&& inst
->isInst() &&
785 inst
->staticInst
->isMemBarrier())
787 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
788 lsq
.issuedMemBarrierInst(inst
);
791 if (inst
->traceData
&& setTraceTimeOnIssue
) {
792 inst
->traceData
->setWhen(curTick());
796 num_mem_insts_issued
++;
799 num_insts_discarded
++;
800 } else if (!inst
->isBubble()) {
803 if (num_insts_issued
== issueLimit
)
804 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
808 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
812 /* Got to the end of a line */
813 if (thread
.inputIndex
== insts_in
->width()) {
815 /* Set insts_in to null to force us to leave the surrounding
819 if (processMoreThanOneInput
) {
820 DPRINTF(MinorExecute
, "Wrapping\n");
821 insts_in
= getInput(thread_id
);
824 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
825 /* We still have instructions */
826 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
827 issued
&& /* We've not yet failed to issue an instruction */
828 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
829 num_mem_insts_issued
!= memoryIssueLimit
);
831 return num_insts_issued
;
835 Execute::tryPCEvents(ThreadID thread_id
)
837 ThreadContext
*thread
= cpu
.getContext(thread_id
);
838 unsigned int num_pc_event_checks
= 0;
840 /* Handle PC events on instructions */
843 oldPC
= thread
->instAddr();
844 cpu
.threads
[thread_id
]->pcEventQueue
.service(oldPC
, thread
);
845 num_pc_event_checks
++;
846 } while (oldPC
!= thread
->instAddr());
848 if (num_pc_event_checks
> 1) {
849 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
853 return num_pc_event_checks
> 1;
857 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
859 assert(!inst
->isFault());
861 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
863 /* Increment the many and various inst and op counts in the
864 * thread and system */
865 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
869 cpu
.stats
.numInsts
++;
870 cpu
.system
->totalNumInsts
++;
872 /* Act on events related to instruction counts */
873 cpu
.comInstEventQueue
[inst
->id
.threadId
]->serviceEvents(thread
->numInst
);
878 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
879 [inst
->staticInst
->opClass()]++;
881 /* Set the CP SeqNum to the numOps commit number */
883 inst
->traceData
->setCPSeq(thread
->numOp
);
885 cpu
.probeInstCommit(inst
->staticInst
, inst
->pc
.instAddr());
889 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
890 BranchData
&branch
, Fault
&fault
, bool &committed
,
891 bool &completed_mem_issue
)
893 ThreadID thread_id
= inst
->id
.threadId
;
894 ThreadContext
*thread
= cpu
.getContext(thread_id
);
896 bool completed_inst
= true;
899 /* Is the thread for this instruction suspended? In that case, just
900 * stall as long as there are no pending interrupts */
901 if (thread
->status() == ThreadContext::Suspended
&&
902 !isInterrupted(thread_id
))
904 panic("We should never hit the case where we try to commit from a "
905 "suspended thread as the streamSeqNum should not match");
906 } else if (inst
->isFault()) {
907 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
909 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
910 inst
->fault
->name());
913 inst
->fault
->invoke(thread
, NULL
);
915 tryToBranch(inst
, fault
, branch
);
916 } else if (inst
->staticInst
->isMemRef()) {
917 /* Memory accesses are executed in two parts:
918 * executeMemRefInst -- calculates the EA and issues the access
919 * to memory. This is done here.
920 * handleMemResponse -- handles the response packet, done by
923 * While the memory access is in its FU, the EA is being
924 * calculated. At the end of the FU, when it is ready to
925 * 'commit' (in this function), the access is presented to the
926 * memory queues. When a response comes back from memory,
927 * Execute::commit will commit it.
929 bool predicate_passed
= false;
930 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
931 predicate_passed
, fault
);
933 if (completed_mem_inst
&& fault
!= NoFault
) {
934 if (early_memory_issue
) {
935 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
937 /* Don't execute the fault, just stall the instruction
938 * until it gets to the head of inFlightInsts */
939 inst
->canEarlyIssue
= false;
940 /* Not completed as we'll come here again to pick up
941 * the fault when we get to the end of the FU */
942 completed_inst
= false;
944 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
946 fault
->invoke(thread
, NULL
);
948 tryToBranch(inst
, fault
, branch
);
949 completed_inst
= true;
952 completed_inst
= completed_mem_inst
;
954 completed_mem_issue
= completed_inst
;
955 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
956 !lsq
.canPushIntoStoreBuffer())
958 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
959 " there isn't space in the store buffer\n", *inst
);
961 completed_inst
= false;
962 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
963 && !branch
.isBubble()){
964 /* This instruction can suspend, need to be able to communicate
965 * backwards, so no other branches may evaluate this cycle*/
966 completed_inst
= false;
968 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
970 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
972 fault
= inst
->staticInst
->execute(&context
,
975 /* Set the predicate for tracing and dump */
977 inst
->traceData
->setPredicate(context
.readPredicate());
981 if (fault
!= NoFault
) {
982 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
983 *inst
, fault
->name());
984 fault
->invoke(thread
, inst
->staticInst
);
987 doInstCommitAccounting(inst
);
988 tryToBranch(inst
, fault
, branch
);
991 if (completed_inst
) {
992 /* Keep a copy of this instruction's predictionSeqNum just in case
993 * we need to issue a branch without an instruction (such as an
995 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
997 /* Check to see if this instruction suspended the current thread. */
998 if (!inst
->isFault() &&
999 thread
->status() == ThreadContext::Suspended
&&
1000 branch
.isBubble() && /* It didn't branch too */
1001 !isInterrupted(thread_id
)) /* Don't suspend if we have
1004 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
1006 assert(resume_pc
.microPC() == 0);
1008 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
1009 " inst: %s\n", thread_id
, *inst
);
1011 cpu
.stats
.numFetchSuspends
++;
1013 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
1018 return completed_inst
;
1022 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1025 Fault fault
= NoFault
;
1026 Cycles now
= cpu
.curCycle();
1027 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1030 * Try and execute as many instructions from the end of FU pipelines as
1031 * possible. This *doesn't* include actually advancing the pipelines.
1033 * We do this by looping on the front of the inFlightInsts queue for as
1034 * long as we can find the desired instruction at the end of the
1035 * functional unit it was issued to without seeing a branch or a fault.
1036 * In this function, these terms are used:
1037 * complete -- The instruction has finished its passage through
1038 * its functional unit and its fate has been decided
1039 * (committed, discarded, issued to the memory system)
1040 * commit -- The instruction is complete(d), not discarded and has
1041 * its effects applied to the CPU state
1042 * discard(ed) -- The instruction is complete but not committed
1043 * as its streamSeqNum disagrees with the current
1044 * Execute::streamSeqNum
1046 * Commits are also possible from two other places:
1048 * 1) Responses returning from the LSQ
1049 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1050 * than their position in the inFlightInsts queue, but after all
1051 * their dependencies are resolved.
1054 /* Has an instruction been completed? Once this becomes false, we stop
1055 * trying to complete instructions. */
1056 bool completed_inst
= true;
1058 /* Number of insts committed this cycle to check against commitLimit */
1059 unsigned int num_insts_committed
= 0;
1061 /* Number of memory access instructions committed to check against
1063 unsigned int num_mem_refs_committed
= 0;
1065 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1066 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1067 *(ex_info
.inFlightInsts
->front().inst
),
1068 ex_info
.lastCommitWasEndOfMacroop
);
1071 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1072 !branch
.isStreamChange() && /* No real branch */
1073 fault
== NoFault
&& /* No faults */
1074 completed_inst
&& /* Still finding instructions to execute */
1075 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1078 if (only_commit_microops
) {
1079 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1081 *(ex_info
.inFlightInsts
->front().inst
));
1084 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1086 InstSeqNum head_exec_seq_num
=
1087 head_inflight_inst
->inst
->id
.execSeqNum
;
1089 /* The instruction we actually process if completed_inst
1090 * remains true to the end of the loop body.
1091 * Start by considering the the head of the in flight insts queue */
1092 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1094 bool committed_inst
= false;
1095 bool discard_inst
= false;
1096 bool completed_mem_ref
= false;
1097 bool issued_mem_ref
= false;
1098 bool early_memory_issue
= false;
1100 /* Must set this again to go around the loop */
1101 completed_inst
= false;
1103 /* If we're just completing a macroop before an interrupt or drain,
1104 * can we stil commit another microop (rather than a memory response)
1105 * without crosing into the next full instruction? */
1106 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1107 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1109 /* Can we find a mem response for this inst */
1110 LSQ::LSQRequestPtr mem_response
=
1111 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1113 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1116 /* Test for PC events after every instruction */
1117 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1118 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1120 /* Branch as there was a change in PC */
1121 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1122 MinorDynInst::bubble(), thread
->pcState(), branch
);
1123 } else if (mem_response
&&
1124 num_mem_refs_committed
< memoryCommitLimit
)
1126 /* Try to commit from the memory responses next */
1127 discard_inst
= inst
->id
.streamSeqNum
!=
1128 ex_info
.streamSeqNum
|| discard
;
1130 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1133 /* Complete or discard the response */
1135 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1136 " stream state was unexpected, expected: %d\n",
1137 *inst
, ex_info
.streamSeqNum
);
1139 lsq
.popResponse(mem_response
);
1141 handleMemResponse(inst
, mem_response
, branch
, fault
);
1142 committed_inst
= true;
1145 completed_mem_ref
= true;
1146 completed_inst
= true;
1147 } else if (can_commit_insts
) {
1148 /* If true, this instruction will, subject to timing tweaks,
1149 * be considered for completion. try_to_commit flattens
1150 * the `if' tree a bit and allows other tests for inst
1151 * commit to be inserted here. */
1152 bool try_to_commit
= false;
1154 /* Try and issue memory ops early if they:
1155 * - Can push a request into the LSQ
1156 * - Have reached the end of their FUs
1157 * - Have had all their dependencies satisfied
1158 * - Are from the right stream
1160 * For any other case, leave it to the normal instruction
1161 * issue below to handle them.
1163 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1164 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1166 const MinorDynInstPtr head_mem_ref_inst
=
1167 ex_info
.inFUMemInsts
->front().inst
;
1168 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1169 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1171 /* Use this, possibly out of order, inst as the one
1172 * to 'commit'/send to the LSQ */
1173 if (!fu_inst
->isBubble() &&
1175 fu_inst
->canEarlyIssue
&&
1176 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1177 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1179 DPRINTF(MinorExecute
, "Issuing mem ref early"
1180 " inst: %s instToWaitFor: %d\n",
1181 *(fu_inst
), fu_inst
->instToWaitFor
);
1184 try_to_commit
= true;
1185 early_memory_issue
= true;
1186 completed_inst
= true;
1190 /* Try and commit FU-less insts */
1191 if (!completed_inst
&& inst
->isNoCostInst()) {
1192 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1194 try_to_commit
= true;
1195 completed_inst
= true;
1198 /* Try to issue from the ends of FUs and the inFlightInsts
1200 if (!completed_inst
&& !inst
->inLSQ
) {
1201 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1203 /* Try to commit from a functional unit */
1204 /* Is the head inst of the expected inst's FU actually the
1206 QueuedInst
&fu_inst
=
1207 funcUnits
[inst
->fuIndex
]->front();
1208 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1210 if (fu_inst
.inst
->isBubble()) {
1211 /* No instruction ready */
1212 completed_inst
= false;
1213 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1214 /* Past instruction: we must have already executed it
1215 * in the same cycle and so the head inst isn't
1216 * actually at the end of its pipeline
1217 * Future instruction: handled above and only for
1218 * mem refs on their way to the LSQ */
1219 } else if (fu_inst
.inst
->id
== inst
->id
) {
1220 /* All instructions can be committed if they have the
1221 * right execSeqNum and there are no in-flight
1222 * mem insts before us */
1223 try_to_commit
= true;
1224 completed_inst
= true;
1228 if (try_to_commit
) {
1229 discard_inst
= inst
->id
.streamSeqNum
!=
1230 ex_info
.streamSeqNum
|| discard
;
1232 /* Is this instruction discardable as its streamSeqNum
1234 if (!discard_inst
) {
1235 /* Try to commit or discard a non-memory instruction.
1236 * Memory ops are actually 'committed' from this FUs
1237 * and 'issued' into the memory system so we need to
1238 * account for them later (commit_was_mem_issue gets
1240 if (inst
->extraCommitDelayExpr
) {
1241 DPRINTF(MinorExecute
, "Evaluating expression for"
1242 " extra commit delay inst: %s\n", *inst
);
1244 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1246 TimingExprEvalContext
context(inst
->staticInst
,
1249 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1252 DPRINTF(MinorExecute
, "Extra commit delay expr"
1253 " result: %d\n", extra_delay
);
1255 if (extra_delay
< 128) {
1256 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1258 DPRINTF(MinorExecute
, "Extra commit delay was"
1259 " very long: %d\n", extra_delay
);
1261 inst
->extraCommitDelayExpr
= NULL
;
1264 /* Move the extraCommitDelay from the instruction
1265 * into the minimumCommitCycle */
1266 if (inst
->extraCommitDelay
!= Cycles(0)) {
1267 inst
->minimumCommitCycle
= cpu
.curCycle() +
1268 inst
->extraCommitDelay
;
1269 inst
->extraCommitDelay
= Cycles(0);
1272 /* @todo Think about making lastMemBarrier be
1273 * MAX_UINT_64 to avoid using 0 as a marker value */
1274 if (!inst
->isFault() && inst
->isMemRef() &&
1275 lsq
.getLastMemBarrier(thread_id
) <
1276 inst
->id
.execSeqNum
&&
1277 lsq
.getLastMemBarrier(thread_id
) != 0)
1279 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1280 " as there are incomplete barriers in flight\n",
1282 completed_inst
= false;
1283 } else if (inst
->minimumCommitCycle
> now
) {
1284 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1285 " as it wants to be stalled for %d more cycles\n",
1286 *inst
, inst
->minimumCommitCycle
- now
);
1287 completed_inst
= false;
1289 completed_inst
= commitInst(inst
,
1290 early_memory_issue
, branch
, fault
,
1291 committed_inst
, issued_mem_ref
);
1294 /* Discard instruction */
1295 completed_inst
= true;
1298 if (completed_inst
) {
1299 /* Allow the pipeline to advance. If the FU head
1300 * instruction wasn't the inFlightInsts head
1301 * but had already been committed, it would have
1302 * unstalled the pipeline before here */
1303 if (inst
->fuIndex
!= noCostFUIndex
) {
1304 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1305 funcUnits
[inst
->fuIndex
]->stalled
= false;
1310 DPRINTF(MinorExecute
, "No instructions to commit\n");
1311 completed_inst
= false;
1314 /* All discardable instructions must also be 'completed' by now */
1315 assert(!(discard_inst
&& !completed_inst
));
1317 /* Instruction committed but was discarded due to streamSeqNum
1320 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1321 " state was unexpected, expected: %d\n",
1322 *inst
, ex_info
.streamSeqNum
);
1324 if (fault
== NoFault
)
1325 cpu
.stats
.numDiscardedOps
++;
1328 /* Mark the mem inst as being in the LSQ */
1329 if (issued_mem_ref
) {
1334 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1335 * as they've *definitely* exited the FUs */
1336 if (completed_inst
&& inst
->isMemRef()) {
1337 /* The MemRef could have been discarded from the FU or the memory
1338 * queue, so just check an FU instruction */
1339 if (!ex_info
.inFUMemInsts
->empty() &&
1340 ex_info
.inFUMemInsts
->front().inst
== inst
)
1342 ex_info
.inFUMemInsts
->pop();
1346 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1347 /* Note that this includes discarded insts */
1348 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1350 /* Got to the end of a full instruction? */
1351 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1352 inst
->isLastOpInInst();
1354 /* lastPredictionSeqNum is kept as a convenience to prevent its
1355 * value from changing too much on the minorview display */
1356 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1358 /* Finished with the inst, remove it from the inst queue and
1359 * clear its dependencies */
1360 ex_info
.inFlightInsts
->pop();
1362 /* Complete barriers in the LSQ/move to store buffer */
1363 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1364 DPRINTF(MinorMem
, "Completing memory barrier"
1365 " inst: %s committed: %d\n", *inst
, committed_inst
);
1366 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1369 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1372 /* Handle per-cycle instruction counting */
1373 if (committed_inst
) {
1374 bool is_no_cost_inst
= inst
->isNoCostInst();
1376 /* Don't show no cost instructions as having taken a commit
1378 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1379 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1381 if (!is_no_cost_inst
)
1382 num_insts_committed
++;
1384 if (num_insts_committed
== commitLimit
)
1385 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1387 /* Re-set the time of the instruction if that's required for
1389 if (inst
->traceData
) {
1390 if (setTraceTimeOnCommit
)
1391 inst
->traceData
->setWhen(curTick());
1392 inst
->traceData
->dump();
1395 if (completed_mem_ref
)
1396 num_mem_refs_committed
++;
1398 if (num_mem_refs_committed
== memoryCommitLimit
)
1399 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1405 Execute::isInbetweenInsts(ThreadID thread_id
) const
1407 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1408 !lsq
.accessesInFlight();
1414 if (!inp
.outputWire
->isBubble())
1415 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1417 BranchData
&branch
= *out
.inputWire
;
1419 unsigned int num_issued
= 0;
1421 /* Do all the cycle-wise activities for dcachePort here to potentially
1422 * free up input spaces in the LSQ's requests queue */
1425 /* Check interrupts first. Will halt commit if interrupt found */
1426 bool interrupted
= false;
1427 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1429 if (interrupt_tid
!= InvalidThreadID
) {
1430 /* Signalling an interrupt this cycle, not issuing/committing from
1431 * any other threads */
1432 } else if (!branch
.isBubble()) {
1433 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1434 * without overwriting them */
1435 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1436 " branch to complete\n");
1438 ThreadID commit_tid
= getCommittingThread();
1440 if (commit_tid
!= InvalidThreadID
) {
1441 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1443 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1445 /* commit can set stalled flags observable to issue and so *must* be
1447 if (commit_info
.drainState
!= NotDraining
) {
1448 if (commit_info
.drainState
== DrainCurrentInst
) {
1449 /* Commit only micro-ops, don't kill anything else */
1450 commit(commit_tid
, true, false, branch
);
1452 if (isInbetweenInsts(commit_tid
))
1453 setDrainState(commit_tid
, DrainHaltFetch
);
1455 /* Discard any generated branch */
1456 branch
= BranchData::bubble();
1457 } else if (commit_info
.drainState
== DrainAllInsts
) {
1458 /* Kill all instructions */
1459 while (getInput(commit_tid
))
1460 popInput(commit_tid
);
1461 commit(commit_tid
, false, true, branch
);
1464 /* Commit micro-ops only if interrupted. Otherwise, commit
1465 * anything you like */
1466 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1468 bool only_commit_microops
= interrupted
&&
1469 hasInterrupt(commit_tid
);
1470 commit(commit_tid
, only_commit_microops
, false, branch
);
1473 /* Halt fetch, but don't do it until we have the current instruction in
1475 if (commit_info
.drainState
== DrainHaltFetch
) {
1476 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1477 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1479 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1480 setDrainState(commit_tid
, DrainAllInsts
);
1483 ThreadID issue_tid
= getIssuingThread();
1484 /* This will issue merrily even when interrupted in the sure and
1485 * certain knowledge that the interrupt with change the stream */
1486 if (issue_tid
!= InvalidThreadID
) {
1487 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1489 num_issued
= issue(issue_tid
);
1494 /* Run logic to step functional units + decide if we are active on the next
1496 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1497 bool can_issue_next
= false;
1499 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1500 /* Find the next issuable instruction for each thread and see if it can
1502 if (getInput(tid
)) {
1503 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1504 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1505 if (inst
->isFault()) {
1506 can_issue_next
= true;
1507 } else if (!inst
->isBubble()) {
1508 next_issuable_insts
.push_back(inst
);
1513 bool becoming_stalled
= true;
1515 /* Advance the pipelines and note whether they still need to be
1517 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1518 FUPipeline
*fu
= funcUnits
[i
];
1521 /* If we need to tick again, the pipeline will have been left or set
1522 * to be unstalled */
1523 if (fu
->occupancy
!=0 && !fu
->stalled
)
1524 becoming_stalled
= false;
1526 /* Could we possibly issue the next instruction from any thread?
1527 * This is quite an expensive test and is only used to determine
1528 * if the CPU should remain active, only run it if we aren't sure
1529 * we are active next cycle yet */
1530 for (auto inst
: next_issuable_insts
) {
1531 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1532 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1533 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1534 cpu
.getContext(inst
->id
.threadId
))) {
1535 can_issue_next
= true;
1541 bool head_inst_might_commit
= false;
1543 /* Could the head in flight insts be committed */
1544 for (auto const &info
: executeInfo
) {
1545 if (!info
.inFlightInsts
->empty()) {
1546 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1548 if (head_inst
.inst
->isNoCostInst()) {
1549 head_inst_might_commit
= true;
1551 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1553 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1554 lsq
.findResponse(head_inst
.inst
))
1556 head_inst_might_commit
= true;
1563 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1564 (num_issued
!= 0 ? " (issued some insts)" : ""),
1565 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1566 (can_issue_next
? " (can issued next inst)" : ""),
1567 (head_inst_might_commit
? "(head inst might commit)" : ""),
1568 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1569 (interrupted
? " (interrupted)" : ""));
1572 num_issued
!= 0 || /* Issued some insts this cycle */
1573 !becoming_stalled
|| /* Some FU pipelines can still move */
1574 can_issue_next
|| /* Can still issue a new inst */
1575 head_inst_might_commit
|| /* Could possible commit the next inst */
1576 lsq
.needsToTick() || /* Must step the dcache port */
1577 interrupted
; /* There are pending interrupts */
1579 if (!need_to_tick
) {
1580 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1581 " advanceable FUs\n");
1584 /* Wake up if we need to tick again */
1586 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1588 /* Note activity of following buffer */
1589 if (!branch
.isBubble())
1590 cpu
.activityRecorder
->activity();
1592 /* Make sure the input (if any left) is pushed */
1593 if (!inp
.outputWire
->isBubble())
1594 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1598 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1600 ThreadID tid
= interruptPriority
;
1601 /* Evaluate interrupts in round-robin based upon service */
1603 /* Has an interrupt been signalled? This may not be acted on
1604 * straighaway so this is different from took_interrupt */
1605 bool thread_interrupted
= false;
1607 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1608 /* This is here because it seems that after drainResume the
1609 * interrupt controller isn't always set */
1610 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1612 interrupted
= interrupted
|| thread_interrupted
;
1614 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1616 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1617 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1618 /* Act on interrupts */
1619 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1620 if (takeInterrupt(tid
, branch
)) {
1621 interruptPriority
= tid
;
1625 tid
= (tid
+ 1) % cpu
.numThreads
;
1627 } while (tid
!= interruptPriority
);
1629 return InvalidThreadID
;
1633 Execute::hasInterrupt(ThreadID thread_id
)
1635 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1636 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1637 isInterrupted(thread_id
);
1644 Execute::minorTrace() const
1646 std::ostringstream insts
;
1647 std::ostringstream stalled
;
1649 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1651 inputBuffer
[0].minorTrace();
1652 scoreboard
[0].minorTrace();
1654 /* Report functional unit stalling in one string */
1656 while (i
< numFuncUnits
)
1658 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1660 if (i
!= numFuncUnits
)
1664 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1665 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1666 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1667 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1669 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1670 std::mem_fun(&FUPipeline::minorTrace
));
1672 executeInfo
[0].inFlightInsts
->minorTrace();
1673 executeInfo
[0].inFUMemInsts
->minorTrace();
1677 Execute::getCommittingThread()
1679 std::vector
<ThreadID
> priority_list
;
1681 switch (cpu
.threadPolicy
) {
1682 case Enums::SingleThreaded
:
1684 case Enums::RoundRobin
:
1685 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1688 priority_list
= cpu
.randomPriority();
1691 panic("Invalid thread policy");
1694 for (auto tid
: priority_list
) {
1695 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1696 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty();
1697 if (can_commit_insts
) {
1698 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1699 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1701 can_commit_insts
= can_commit_insts
&&
1702 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1705 bool can_transfer_mem_inst
= false;
1706 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1707 const MinorDynInstPtr head_mem_ref_inst
=
1708 ex_info
.inFUMemInsts
->front().inst
;
1709 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1710 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1711 can_transfer_mem_inst
=
1712 !fu_inst
->isBubble() &&
1713 fu_inst
->id
.threadId
== tid
&&
1715 fu_inst
->canEarlyIssue
&&
1716 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1719 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1720 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1721 inst
->fuIndex
!= noCostFUIndex
)
1723 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1724 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1725 fu_inst
.inst
->id
== inst
->id
;
1728 can_commit_insts
= can_commit_insts
&&
1729 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1734 if (can_commit_insts
) {
1735 commitPriority
= tid
;
1740 return InvalidThreadID
;
1744 Execute::getIssuingThread()
1746 std::vector
<ThreadID
> priority_list
;
1748 switch (cpu
.threadPolicy
) {
1749 case Enums::SingleThreaded
:
1751 case Enums::RoundRobin
:
1752 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1755 priority_list
= cpu
.randomPriority();
1758 panic("Invalid thread scheduling policy.");
1761 for (auto tid
: priority_list
) {
1762 if (getInput(tid
)) {
1763 issuePriority
= tid
;
1768 return InvalidThreadID
;
1772 Execute::drainResume()
1774 DPRINTF(Drain
, "MinorExecute drainResume\n");
1776 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1777 setDrainState(tid
, NotDraining
);
1780 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1783 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1787 case Execute::NotDraining
:
1788 os
<< "NotDraining";
1790 case Execute::DrainCurrentInst
:
1791 os
<< "DrainCurrentInst";
1793 case Execute::DrainHaltFetch
:
1794 os
<< "DrainHaltFetch";
1796 case Execute::DrainAllInsts
:
1797 os
<< "DrainAllInsts";
1800 os
<< "Drain-" << static_cast<int>(state
);
1808 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1810 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1811 executeInfo
[thread_id
].drainState
= state
;
1817 DPRINTF(Drain
, "MinorExecute drain\n");
1819 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1820 if (executeInfo
[tid
].drainState
== NotDraining
) {
1821 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1823 /* Go to DrainCurrentInst if we're between microops
1824 * or waiting on an unbufferable memory operation.
1825 * Otherwise we can go straight to DrainHaltFetch
1827 if (isInbetweenInsts(tid
))
1828 setDrainState(tid
, DrainHaltFetch
);
1830 setDrainState(tid
, DrainCurrentInst
);
1833 return (isDrained() ? 0 : 1);
1837 Execute::isDrained()
1839 if (!lsq
.isDrained())
1842 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1843 if (!inputBuffer
[tid
].empty() ||
1844 !executeInfo
[tid
].inFlightInsts
->empty()) {
1855 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1856 delete funcUnits
[i
];
1858 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1859 delete executeInfo
[tid
].inFlightInsts
;
1863 Execute::instIsRightStream(MinorDynInstPtr inst
)
1865 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1869 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1873 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1874 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1879 MinorCPU::MinorCPUPort
&
1880 Execute::getDcachePort()
1882 return lsq
.getDcachePort();