2 * Copyright (c) 2013-2014,2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "cpu/minor/execute.hh"
42 #include "arch/locked_mem.hh"
43 #include "arch/registers.hh"
44 #include "arch/utility.hh"
45 #include "cpu/minor/cpu.hh"
46 #include "cpu/minor/exec_context.hh"
47 #include "cpu/minor/fetch1.hh"
48 #include "cpu/minor/lsq.hh"
49 #include "cpu/op_class.hh"
50 #include "debug/Activity.hh"
51 #include "debug/Branch.hh"
52 #include "debug/Drain.hh"
53 #include "debug/MinorExecute.hh"
54 #include "debug/MinorInterrupt.hh"
55 #include "debug/MinorMem.hh"
56 #include "debug/MinorTrace.hh"
57 #include "debug/PCEvent.hh"
62 Execute::Execute(const std::string
&name_
,
64 MinorCPUParams
¶ms
,
65 Latch
<ForwardInstData
>::Output inp_
,
66 Latch
<BranchData
>::Input out_
) :
71 issueLimit(params
.executeIssueLimit
),
72 memoryIssueLimit(params
.executeMemoryIssueLimit
),
73 commitLimit(params
.executeCommitLimit
),
74 memoryCommitLimit(params
.executeMemoryCommitLimit
),
75 processMoreThanOneInput(params
.executeCycleInput
),
76 fuDescriptions(*params
.executeFuncUnits
),
77 numFuncUnits(fuDescriptions
.funcUnits
.size()),
78 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
79 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
80 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
81 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
82 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
84 params
.executeMaxAccessesInMemory
,
85 params
.executeMemoryWidth
,
86 params
.executeLSQRequestsQueueSize
,
87 params
.executeLSQTransfersQueueSize
,
88 params
.executeLSQStoreBufferSize
,
89 params
.executeLSQMaxStoreBufferStoresPerCycle
),
90 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
95 if (commitLimit
< 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
100 if (issueLimit
< 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
105 if (memoryIssueLimit
< 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
110 if (memoryCommitLimit
> commitLimit
) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_
, memoryCommitLimit
, commitLimit
);
116 if (params
.executeInputBufferSize
< 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
118 params
.executeInputBufferSize
);
121 if (params
.executeInputBufferSize
< 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
123 params
.executeInputBufferSize
);
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
129 unsigned int total_slots
= 0;
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
133 std::ostringstream fu_name
;
134 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots
+= fu_description
->opLat
;
141 fu_name
<< name_
<< ".fu." << i
;
143 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
145 funcUnits
.push_back(fu
);
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
150 bool found_fu
= false;
151 unsigned int fu_index
= 0;
153 while (fu_index
< numFuncUnits
&& !found_fu
)
155 if (funcUnits
[fu_index
]->provides(
156 static_cast<OpClass
>(op_class
)))
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings
[op_class
]);
169 /* Per-thread structures */
170 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
171 std::string tid_str
= std::to_string(tid
);
174 inputBuffer
.push_back(
175 InputBuffer
<ForwardInstData
>(
176 name_
+ ".inputBuffer" + tid_str
, "insts",
177 params
.executeInputBufferSize
));
180 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
182 /* In-flight instruction records */
183 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
184 ReportTraitsAdaptor
<QueuedInst
> >(
185 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
187 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
188 ReportTraitsAdaptor
<QueuedInst
> >(
189 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
193 const ForwardInstData
*
194 Execute::getInput(ThreadID tid
)
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer
[tid
].empty()) {
198 const ForwardInstData
&head
= inputBuffer
[tid
].front();
200 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
207 Execute::popInput(ThreadID tid
)
209 if (!inputBuffer
[tid
].empty())
210 inputBuffer
[tid
].pop();
212 executeInfo
[tid
].inputIndex
= 0;
216 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
218 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
219 const TheISA::PCState
&pc_before
= inst
->pc
;
220 TheISA::PCState target
= thread
->pcState();
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
226 inst
->isLastOpInInst() &&
227 (inst
->staticInst
->isSerializeAfter() ||
228 inst
->staticInst
->isSquashAfter() ||
229 inst
->staticInst
->isIprAccess());
231 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
232 pc_before
, target
, (force_branch
? " (forcing)" : ""));
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch
= pc_before
!= target
||
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason
= BranchData::NoBranch
;
242 if (fault
== NoFault
)
244 TheISA::advancePC(target
, inst
->staticInst
);
245 thread
->pcState(target
);
247 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
251 if (thread
->status() == ThreadContext::Suspended
) {
252 /* Thread got suspended */
253 DPRINTF(Branch
, "Thread got suspended: branch from 0x%x to 0x%x "
255 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
257 reason
= BranchData::SuspendThread
;
258 } else if (inst
->predictedTaken
&& !force_branch
) {
259 /* Predicted to branch */
261 /* No branch was taken, change stream to get us back to the
262 * intended PC value */
263 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
264 " none happened inst: %s\n",
265 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
267 reason
= BranchData::BadlyPredictedBranch
;
268 } else if (inst
->predictedTarget
== target
) {
269 /* Branch prediction got the right target, kill the branch and
271 * Note that this information to the branch predictor might get
272 * overwritten by a "real" branch during this cycle */
273 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
275 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
277 reason
= BranchData::CorrectlyPredictedBranch
;
279 /* Branch prediction got the wrong target */
280 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
281 " but got the wrong target (actual: 0x%x) inst: %s\n",
282 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
283 target
.instAddr(), *inst
);
285 reason
= BranchData::BadlyPredictedBranchTarget
;
287 } else if (must_branch
) {
288 /* Unpredicted branch */
289 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
290 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
292 reason
= BranchData::UnpredictedBranch
;
294 /* No branch at all */
295 reason
= BranchData::NoBranch
;
298 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
302 Execute::updateBranchData(
304 BranchData::Reason reason
,
305 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
308 if (reason
!= BranchData::NoBranch
) {
309 /* Bump up the stream sequence number on a real branch*/
310 if (BranchData::isStreamChange(reason
))
311 executeInfo
[tid
].streamSeqNum
++;
313 /* Branches (even mis-predictions) don't change the predictionSeqNum,
314 * just the streamSeqNum */
315 branch
= BranchData(reason
, tid
,
316 executeInfo
[tid
].streamSeqNum
,
317 /* Maintaining predictionSeqNum if there's no inst is just a
318 * courtesy and looks better on minorview */
319 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
320 : inst
->id
.predictionSeqNum
),
323 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
328 Execute::handleMemResponse(MinorDynInstPtr inst
,
329 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
331 ThreadID thread_id
= inst
->id
.threadId
;
332 ThreadContext
*thread
= cpu
.getContext(thread_id
);
334 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
336 PacketPtr packet
= response
->packet
;
338 bool is_load
= inst
->staticInst
->isLoad();
339 bool is_store
= inst
->staticInst
->isStore();
340 bool is_atomic
= inst
->staticInst
->isAtomic();
341 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
343 /* If true, the trace's predicate value will be taken from the exec
344 * context predicate, otherwise, it will be set to false */
345 bool use_context_predicate
= true;
347 if (response
->fault
!= NoFault
) {
348 /* Invoke memory faults. */
349 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
350 response
->fault
->name());
352 if (inst
->staticInst
->isPrefetch()) {
353 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
354 response
->fault
->name());
356 /* Don't assign to fault */
358 /* Take the fault raised during the TLB/memory access */
359 fault
= response
->fault
;
361 fault
->invoke(thread
, inst
->staticInst
);
363 } else if (!packet
) {
364 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
366 use_context_predicate
= false;
367 if (!context
.readMemAccPredicate())
368 inst
->staticInst
->completeAcc(nullptr, &context
, inst
->traceData
);
369 } else if (packet
->isError()) {
370 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
373 fatal("Received error response packet for inst: %s\n", *inst
);
374 } else if (is_store
|| is_load
|| is_prefetch
|| is_atomic
) {
377 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
378 *inst
, packet
->getAddr(), packet
->getSize());
380 if (is_load
&& packet
->getSize() > 0) {
381 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
382 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
385 /* Complete the memory access instruction */
386 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
389 if (fault
!= NoFault
) {
390 /* Invoke fault created by instruction completion */
391 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
393 fault
->invoke(thread
, inst
->staticInst
);
395 /* Stores need to be pushed into the store buffer to finish
397 if (response
->needsToBeSentToStoreBuffer())
398 lsq
.sendStoreToStoreBuffer(response
);
401 fatal("There should only ever be reads, "
402 "writes or faults at this point\n");
405 lsq
.popResponse(response
);
407 if (inst
->traceData
) {
408 inst
->traceData
->setPredicate((use_context_predicate
?
409 context
.readPredicate() : false));
412 doInstCommitAccounting(inst
);
414 /* Generate output to account for branches */
415 tryToBranch(inst
, fault
, branch
);
419 Execute::isInterrupted(ThreadID thread_id
) const
421 return cpu
.checkInterrupts(cpu
.getContext(thread_id
));
425 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
427 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
428 cpu
.getContext(thread_id
)->pcState());
430 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt
431 (cpu
.getContext(thread_id
));
433 if (interrupt
!= NoFault
) {
434 /* The interrupt *must* set pcState */
435 cpu
.getInterruptController(thread_id
)->updateIntrInfo
436 (cpu
.getContext(thread_id
));
437 interrupt
->invoke(cpu
.getContext(thread_id
));
439 assert(!lsq
.accessesInFlight());
441 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
442 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
444 /* Assume that an interrupt *must* cause a branch. Assert this? */
446 updateBranchData(thread_id
, BranchData::Interrupt
,
447 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
451 return interrupt
!= NoFault
;
455 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
456 bool &passed_predicate
, Fault
&fault
)
460 /* Set to true if the mem op. is issued and sent to the mem system */
461 passed_predicate
= false;
463 if (!lsq
.canRequest()) {
464 /* Not acting on instruction yet as the memory
468 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
469 TheISA::PCState old_pc
= thread
->pcState();
471 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
474 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
476 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
479 if (init_fault
!= NoFault
) {
480 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
481 " initiateAcc: %s\n", *inst
, init_fault
->name());
484 /* Only set this if the instruction passed its
486 if (!context
.readMemAccPredicate()) {
487 DPRINTF(MinorMem
, "No memory access for inst: %s\n", *inst
);
488 assert(context
.readPredicate());
490 passed_predicate
= context
.readPredicate();
492 /* Set predicate in tracing */
494 inst
->traceData
->setPredicate(passed_predicate
);
496 /* If the instruction didn't pass its predicate (and so will not
497 * progress from here) Try to branch to correct and branch
499 if (!passed_predicate
) {
500 /* Leave it up to commit to handle the fault */
501 lsq
.pushFailedRequest(inst
);
505 /* Restore thread PC */
506 thread
->pcState(old_pc
);
513 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
515 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
517 unsigned int ret
= index
+ 1;
519 if (ret
== cycle_size
)
525 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
527 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
532 ret
= cycle_size
- 1;
538 Execute::issue(ThreadID thread_id
)
540 const ForwardInstData
*insts_in
= getInput(thread_id
);
541 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
543 /* Early termination if we have no instructions */
547 /* Start from the first FU */
548 unsigned int fu_index
= 0;
550 /* Remains true while instructions are still being issued. If any
551 * instruction fails to issue, this is set to false and we exit issue.
552 * This strictly enforces in-order issue. For other issue behaviours,
553 * a more complicated test in the outer while loop below is needed. */
556 /* Number of insts issues this cycle to check for issueLimit */
557 unsigned num_insts_issued
= 0;
559 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
560 unsigned num_mem_insts_issued
= 0;
562 /* Number of instructions discarded this cycle in order to enforce a
563 * discardLimit. @todo, add that parameter? */
564 unsigned num_insts_discarded
= 0;
567 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
568 Fault fault
= inst
->fault
;
569 bool discarded
= false;
570 bool issued_mem_ref
= false;
572 if (inst
->isBubble()) {
575 } else if (cpu
.getContext(thread_id
)->status() ==
576 ThreadContext::Suspended
)
578 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
583 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
584 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
585 " state was unexpected, expected: %d\n",
586 *inst
, thread
.streamSeqNum
);
590 /* Try and issue an instruction into an FU, assume we didn't and
591 * fix that in the loop */
594 /* Try FU from 0 each instruction */
597 /* Try and issue a single instruction stepping through the
600 FUPipeline
*fu
= funcUnits
[fu_index
];
602 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
605 /* Does the examined fu have the OpClass-related capability
606 * needed to execute this instruction? Faults can always
607 * issue to any FU but probably should just 'live' in the
608 * inFlightInsts queue rather than having an FU. */
609 bool fu_is_capable
= (!inst
->isFault() ?
610 fu
->provides(inst
->staticInst
->opClass()) : true);
612 if (inst
->isNoCostInst()) {
613 /* Issue free insts. to a fake numbered FU */
614 fu_index
= noCostFUIndex
;
616 /* And start the countdown on activity to allow
617 * this instruction to get to the end of its FU */
618 cpu
.activityRecorder
->activity();
620 /* Mark the destinations for this instruction as
622 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
623 Cycles(0), cpu
.getContext(thread_id
), false);
625 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
626 inst
->fuIndex
= noCostFUIndex
;
627 inst
->extraCommitDelay
= Cycles(0);
628 inst
->extraCommitDelayExpr
= NULL
;
630 /* Push the instruction onto the inFlight queue so
631 * it can be committed in order */
632 QueuedInst
fu_inst(inst
);
633 thread
.inFlightInsts
->push(fu_inst
);
637 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
639 if (!fu_is_capable
) {
640 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
641 " capable\n", fu_index
);
643 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
644 " already busy\n", fu_index
);
646 } else if (fu
->stalled
) {
647 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
650 } else if (!fu
->canInsert()) {
651 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
652 " for another: %d cycles\n",
653 *inst
, fu
->cyclesBeforeInsert());
655 MinorFUTiming
*timing
= (!inst
->isFault() ?
656 fu
->findTiming(inst
->staticInst
) : NULL
);
658 const std::vector
<Cycles
> *src_latencies
=
659 (timing
? &(timing
->srcRegsRelativeLats
)
662 const std::vector
<bool> *cant_forward_from_fu_indices
=
663 &(fu
->cantForwardFromFUIndices
);
665 if (timing
&& timing
->suppress
) {
666 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
667 " decoding is suppressing it\n",
669 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
670 src_latencies
, cant_forward_from_fu_indices
,
671 cpu
.curCycle(), cpu
.getContext(thread_id
)))
673 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
676 /* Can insert the instruction into this FU */
677 DPRINTF(MinorExecute
, "Issuing inst: %s"
678 " into FU %d\n", *inst
,
681 Cycles extra_dest_retire_lat
= Cycles(0);
682 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
683 Cycles extra_assumed_lat
= Cycles(0);
685 /* Add the extraCommitDelay and extraAssumeLat to
686 * the FU pipeline timings */
688 extra_dest_retire_lat
=
689 timing
->extraCommitLat
;
690 extra_dest_retire_lat_expr
=
691 timing
->extraCommitLatExpr
;
693 timing
->extraAssumedLat
;
696 issued_mem_ref
= inst
->isMemRef();
698 QueuedInst
fu_inst(inst
);
700 /* Decorate the inst with FU details */
701 inst
->fuIndex
= fu_index
;
702 inst
->extraCommitDelay
= extra_dest_retire_lat
;
703 inst
->extraCommitDelayExpr
=
704 extra_dest_retire_lat_expr
;
706 if (issued_mem_ref
) {
707 /* Remember which instruction this memory op
708 * depends on so that initiateAcc can be called
710 if (allowEarlyMemIssue
) {
711 inst
->instToWaitFor
=
712 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
713 cpu
.getContext(thread_id
));
715 if (lsq
.getLastMemBarrier(thread_id
) >
718 DPRINTF(MinorExecute
, "A barrier will"
719 " cause a delay in mem ref issue of"
720 " inst: %s until after inst"
721 " %d(exec)\n", *inst
,
722 lsq
.getLastMemBarrier(thread_id
));
724 inst
->instToWaitFor
=
725 lsq
.getLastMemBarrier(thread_id
);
727 DPRINTF(MinorExecute
, "Memory ref inst:"
728 " %s must wait for inst %d(exec)"
730 *inst
, inst
->instToWaitFor
);
733 inst
->canEarlyIssue
= true;
735 /* Also queue this instruction in the memory ref
736 * queue to ensure in-order issue to the LSQ */
737 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
739 thread
.inFUMemInsts
->push(fu_inst
);
744 /* And start the countdown on activity to allow
745 * this instruction to get to the end of its FU */
746 cpu
.activityRecorder
->activity();
748 /* Mark the destinations for this instruction as
750 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
751 fu
->description
.opLat
+
752 extra_dest_retire_lat
+
754 cpu
.getContext(thread_id
),
755 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
757 /* Push the instruction onto the inFlight queue so
758 * it can be committed in order */
759 thread
.inFlightInsts
->push(fu_inst
);
766 } while (fu_index
!= numFuncUnits
&& !issued
);
769 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
773 /* Generate MinorTrace's MinorInst lines. Do this at commit
774 * to allow better instruction annotation? */
775 if (DTRACE(MinorTrace
) && !inst
->isBubble())
776 inst
->minorTraceInst(*this);
778 /* Mark up barriers in the LSQ */
779 if (!discarded
&& inst
->isInst() &&
780 inst
->staticInst
->isMemBarrier())
782 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
783 lsq
.issuedMemBarrierInst(inst
);
786 if (inst
->traceData
&& setTraceTimeOnIssue
) {
787 inst
->traceData
->setWhen(curTick());
791 num_mem_insts_issued
++;
794 num_insts_discarded
++;
795 } else if (!inst
->isBubble()) {
798 if (num_insts_issued
== issueLimit
)
799 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
803 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
807 /* Got to the end of a line */
808 if (thread
.inputIndex
== insts_in
->width()) {
810 /* Set insts_in to null to force us to leave the surrounding
814 if (processMoreThanOneInput
) {
815 DPRINTF(MinorExecute
, "Wrapping\n");
816 insts_in
= getInput(thread_id
);
819 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
820 /* We still have instructions */
821 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
822 issued
&& /* We've not yet failed to issue an instruction */
823 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
824 num_mem_insts_issued
!= memoryIssueLimit
);
826 return num_insts_issued
;
830 Execute::tryPCEvents(ThreadID thread_id
)
832 ThreadContext
*thread
= cpu
.getContext(thread_id
);
833 unsigned int num_pc_event_checks
= 0;
835 /* Handle PC events on instructions */
838 oldPC
= thread
->instAddr();
839 cpu
.system
->pcEventQueue
.service(thread
);
840 num_pc_event_checks
++;
841 } while (oldPC
!= thread
->instAddr());
843 if (num_pc_event_checks
> 1) {
844 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
848 return num_pc_event_checks
> 1;
852 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
854 assert(!inst
->isFault());
856 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
858 /* Increment the many and various inst and op counts in the
859 * thread and system */
860 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
864 cpu
.stats
.numInsts
++;
865 cpu
.system
->totalNumInsts
++;
867 /* Act on events related to instruction counts */
868 cpu
.comInstEventQueue
[inst
->id
.threadId
]->serviceEvents(thread
->numInst
);
869 cpu
.system
->instEventQueue
.serviceEvents(cpu
.system
->totalNumInsts
);
874 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
875 [inst
->staticInst
->opClass()]++;
877 /* Set the CP SeqNum to the numOps commit number */
879 inst
->traceData
->setCPSeq(thread
->numOp
);
881 cpu
.probeInstCommit(inst
->staticInst
, inst
->pc
.instAddr());
885 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
886 BranchData
&branch
, Fault
&fault
, bool &committed
,
887 bool &completed_mem_issue
)
889 ThreadID thread_id
= inst
->id
.threadId
;
890 ThreadContext
*thread
= cpu
.getContext(thread_id
);
892 bool completed_inst
= true;
895 /* Is the thread for this instruction suspended? In that case, just
896 * stall as long as there are no pending interrupts */
897 if (thread
->status() == ThreadContext::Suspended
&&
898 !isInterrupted(thread_id
))
900 panic("We should never hit the case where we try to commit from a "
901 "suspended thread as the streamSeqNum should not match");
902 } else if (inst
->isFault()) {
903 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
905 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
906 inst
->fault
->name());
909 inst
->fault
->invoke(thread
, NULL
);
911 tryToBranch(inst
, fault
, branch
);
912 } else if (inst
->staticInst
->isMemRef()) {
913 /* Memory accesses are executed in two parts:
914 * executeMemRefInst -- calculates the EA and issues the access
915 * to memory. This is done here.
916 * handleMemResponse -- handles the response packet, done by
919 * While the memory access is in its FU, the EA is being
920 * calculated. At the end of the FU, when it is ready to
921 * 'commit' (in this function), the access is presented to the
922 * memory queues. When a response comes back from memory,
923 * Execute::commit will commit it.
925 bool predicate_passed
= false;
926 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
927 predicate_passed
, fault
);
929 if (completed_mem_inst
&& fault
!= NoFault
) {
930 if (early_memory_issue
) {
931 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
933 /* Don't execute the fault, just stall the instruction
934 * until it gets to the head of inFlightInsts */
935 inst
->canEarlyIssue
= false;
936 /* Not completed as we'll come here again to pick up
937 * the fault when we get to the end of the FU */
938 completed_inst
= false;
940 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
942 fault
->invoke(thread
, NULL
);
944 tryToBranch(inst
, fault
, branch
);
945 completed_inst
= true;
948 completed_inst
= completed_mem_inst
;
950 completed_mem_issue
= completed_inst
;
951 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
952 !lsq
.canPushIntoStoreBuffer())
954 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
955 " there isn't space in the store buffer\n", *inst
);
957 completed_inst
= false;
958 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
959 && !branch
.isBubble()){
960 /* This instruction can suspend, need to be able to communicate
961 * backwards, so no other branches may evaluate this cycle*/
962 completed_inst
= false;
964 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
966 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
968 fault
= inst
->staticInst
->execute(&context
,
971 /* Set the predicate for tracing and dump */
973 inst
->traceData
->setPredicate(context
.readPredicate());
977 if (fault
!= NoFault
) {
978 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
979 *inst
, fault
->name());
980 fault
->invoke(thread
, inst
->staticInst
);
983 doInstCommitAccounting(inst
);
984 tryToBranch(inst
, fault
, branch
);
987 if (completed_inst
) {
988 /* Keep a copy of this instruction's predictionSeqNum just in case
989 * we need to issue a branch without an instruction (such as an
991 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
993 /* Check to see if this instruction suspended the current thread. */
994 if (!inst
->isFault() &&
995 thread
->status() == ThreadContext::Suspended
&&
996 branch
.isBubble() && /* It didn't branch too */
997 !isInterrupted(thread_id
)) /* Don't suspend if we have
1000 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
1002 assert(resume_pc
.microPC() == 0);
1004 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
1005 " inst: %s\n", thread_id
, *inst
);
1007 cpu
.stats
.numFetchSuspends
++;
1009 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
1014 return completed_inst
;
1018 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1021 Fault fault
= NoFault
;
1022 Cycles now
= cpu
.curCycle();
1023 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1026 * Try and execute as many instructions from the end of FU pipelines as
1027 * possible. This *doesn't* include actually advancing the pipelines.
1029 * We do this by looping on the front of the inFlightInsts queue for as
1030 * long as we can find the desired instruction at the end of the
1031 * functional unit it was issued to without seeing a branch or a fault.
1032 * In this function, these terms are used:
1033 * complete -- The instruction has finished its passage through
1034 * its functional unit and its fate has been decided
1035 * (committed, discarded, issued to the memory system)
1036 * commit -- The instruction is complete(d), not discarded and has
1037 * its effects applied to the CPU state
1038 * discard(ed) -- The instruction is complete but not committed
1039 * as its streamSeqNum disagrees with the current
1040 * Execute::streamSeqNum
1042 * Commits are also possible from two other places:
1044 * 1) Responses returning from the LSQ
1045 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1046 * than their position in the inFlightInsts queue, but after all
1047 * their dependencies are resolved.
1050 /* Has an instruction been completed? Once this becomes false, we stop
1051 * trying to complete instructions. */
1052 bool completed_inst
= true;
1054 /* Number of insts committed this cycle to check against commitLimit */
1055 unsigned int num_insts_committed
= 0;
1057 /* Number of memory access instructions committed to check against
1059 unsigned int num_mem_refs_committed
= 0;
1061 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1062 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1063 *(ex_info
.inFlightInsts
->front().inst
),
1064 ex_info
.lastCommitWasEndOfMacroop
);
1067 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1068 !branch
.isStreamChange() && /* No real branch */
1069 fault
== NoFault
&& /* No faults */
1070 completed_inst
&& /* Still finding instructions to execute */
1071 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1074 if (only_commit_microops
) {
1075 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1077 *(ex_info
.inFlightInsts
->front().inst
));
1080 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1082 InstSeqNum head_exec_seq_num
=
1083 head_inflight_inst
->inst
->id
.execSeqNum
;
1085 /* The instruction we actually process if completed_inst
1086 * remains true to the end of the loop body.
1087 * Start by considering the the head of the in flight insts queue */
1088 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1090 bool committed_inst
= false;
1091 bool discard_inst
= false;
1092 bool completed_mem_ref
= false;
1093 bool issued_mem_ref
= false;
1094 bool early_memory_issue
= false;
1096 /* Must set this again to go around the loop */
1097 completed_inst
= false;
1099 /* If we're just completing a macroop before an interrupt or drain,
1100 * can we stil commit another microop (rather than a memory response)
1101 * without crosing into the next full instruction? */
1102 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1103 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1105 /* Can we find a mem response for this inst */
1106 LSQ::LSQRequestPtr mem_response
=
1107 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1109 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1112 /* Test for PC events after every instruction */
1113 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1114 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1116 /* Branch as there was a change in PC */
1117 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1118 MinorDynInst::bubble(), thread
->pcState(), branch
);
1119 } else if (mem_response
&&
1120 num_mem_refs_committed
< memoryCommitLimit
)
1122 /* Try to commit from the memory responses next */
1123 discard_inst
= inst
->id
.streamSeqNum
!=
1124 ex_info
.streamSeqNum
|| discard
;
1126 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1129 /* Complete or discard the response */
1131 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1132 " stream state was unexpected, expected: %d\n",
1133 *inst
, ex_info
.streamSeqNum
);
1135 lsq
.popResponse(mem_response
);
1137 handleMemResponse(inst
, mem_response
, branch
, fault
);
1138 committed_inst
= true;
1141 completed_mem_ref
= true;
1142 completed_inst
= true;
1143 } else if (can_commit_insts
) {
1144 /* If true, this instruction will, subject to timing tweaks,
1145 * be considered for completion. try_to_commit flattens
1146 * the `if' tree a bit and allows other tests for inst
1147 * commit to be inserted here. */
1148 bool try_to_commit
= false;
1150 /* Try and issue memory ops early if they:
1151 * - Can push a request into the LSQ
1152 * - Have reached the end of their FUs
1153 * - Have had all their dependencies satisfied
1154 * - Are from the right stream
1156 * For any other case, leave it to the normal instruction
1157 * issue below to handle them.
1159 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1160 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1162 const MinorDynInstPtr head_mem_ref_inst
=
1163 ex_info
.inFUMemInsts
->front().inst
;
1164 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1165 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1167 /* Use this, possibly out of order, inst as the one
1168 * to 'commit'/send to the LSQ */
1169 if (!fu_inst
->isBubble() &&
1171 fu_inst
->canEarlyIssue
&&
1172 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1173 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1175 DPRINTF(MinorExecute
, "Issuing mem ref early"
1176 " inst: %s instToWaitFor: %d\n",
1177 *(fu_inst
), fu_inst
->instToWaitFor
);
1180 try_to_commit
= true;
1181 early_memory_issue
= true;
1182 completed_inst
= true;
1186 /* Try and commit FU-less insts */
1187 if (!completed_inst
&& inst
->isNoCostInst()) {
1188 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1190 try_to_commit
= true;
1191 completed_inst
= true;
1194 /* Try to issue from the ends of FUs and the inFlightInsts
1196 if (!completed_inst
&& !inst
->inLSQ
) {
1197 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1199 /* Try to commit from a functional unit */
1200 /* Is the head inst of the expected inst's FU actually the
1202 QueuedInst
&fu_inst
=
1203 funcUnits
[inst
->fuIndex
]->front();
1204 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1206 if (fu_inst
.inst
->isBubble()) {
1207 /* No instruction ready */
1208 completed_inst
= false;
1209 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1210 /* Past instruction: we must have already executed it
1211 * in the same cycle and so the head inst isn't
1212 * actually at the end of its pipeline
1213 * Future instruction: handled above and only for
1214 * mem refs on their way to the LSQ */
1215 } else if (fu_inst
.inst
->id
== inst
->id
) {
1216 /* All instructions can be committed if they have the
1217 * right execSeqNum and there are no in-flight
1218 * mem insts before us */
1219 try_to_commit
= true;
1220 completed_inst
= true;
1224 if (try_to_commit
) {
1225 discard_inst
= inst
->id
.streamSeqNum
!=
1226 ex_info
.streamSeqNum
|| discard
;
1228 /* Is this instruction discardable as its streamSeqNum
1230 if (!discard_inst
) {
1231 /* Try to commit or discard a non-memory instruction.
1232 * Memory ops are actually 'committed' from this FUs
1233 * and 'issued' into the memory system so we need to
1234 * account for them later (commit_was_mem_issue gets
1236 if (inst
->extraCommitDelayExpr
) {
1237 DPRINTF(MinorExecute
, "Evaluating expression for"
1238 " extra commit delay inst: %s\n", *inst
);
1240 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1242 TimingExprEvalContext
context(inst
->staticInst
,
1245 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1248 DPRINTF(MinorExecute
, "Extra commit delay expr"
1249 " result: %d\n", extra_delay
);
1251 if (extra_delay
< 128) {
1252 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1254 DPRINTF(MinorExecute
, "Extra commit delay was"
1255 " very long: %d\n", extra_delay
);
1257 inst
->extraCommitDelayExpr
= NULL
;
1260 /* Move the extraCommitDelay from the instruction
1261 * into the minimumCommitCycle */
1262 if (inst
->extraCommitDelay
!= Cycles(0)) {
1263 inst
->minimumCommitCycle
= cpu
.curCycle() +
1264 inst
->extraCommitDelay
;
1265 inst
->extraCommitDelay
= Cycles(0);
1268 /* @todo Think about making lastMemBarrier be
1269 * MAX_UINT_64 to avoid using 0 as a marker value */
1270 if (!inst
->isFault() && inst
->isMemRef() &&
1271 lsq
.getLastMemBarrier(thread_id
) <
1272 inst
->id
.execSeqNum
&&
1273 lsq
.getLastMemBarrier(thread_id
) != 0)
1275 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1276 " as there are incomplete barriers in flight\n",
1278 completed_inst
= false;
1279 } else if (inst
->minimumCommitCycle
> now
) {
1280 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1281 " as it wants to be stalled for %d more cycles\n",
1282 *inst
, inst
->minimumCommitCycle
- now
);
1283 completed_inst
= false;
1285 completed_inst
= commitInst(inst
,
1286 early_memory_issue
, branch
, fault
,
1287 committed_inst
, issued_mem_ref
);
1290 /* Discard instruction */
1291 completed_inst
= true;
1294 if (completed_inst
) {
1295 /* Allow the pipeline to advance. If the FU head
1296 * instruction wasn't the inFlightInsts head
1297 * but had already been committed, it would have
1298 * unstalled the pipeline before here */
1299 if (inst
->fuIndex
!= noCostFUIndex
) {
1300 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1301 funcUnits
[inst
->fuIndex
]->stalled
= false;
1306 DPRINTF(MinorExecute
, "No instructions to commit\n");
1307 completed_inst
= false;
1310 /* All discardable instructions must also be 'completed' by now */
1311 assert(!(discard_inst
&& !completed_inst
));
1313 /* Instruction committed but was discarded due to streamSeqNum
1316 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1317 " state was unexpected, expected: %d\n",
1318 *inst
, ex_info
.streamSeqNum
);
1320 if (fault
== NoFault
)
1321 cpu
.stats
.numDiscardedOps
++;
1324 /* Mark the mem inst as being in the LSQ */
1325 if (issued_mem_ref
) {
1330 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1331 * as they've *definitely* exited the FUs */
1332 if (completed_inst
&& inst
->isMemRef()) {
1333 /* The MemRef could have been discarded from the FU or the memory
1334 * queue, so just check an FU instruction */
1335 if (!ex_info
.inFUMemInsts
->empty() &&
1336 ex_info
.inFUMemInsts
->front().inst
== inst
)
1338 ex_info
.inFUMemInsts
->pop();
1342 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1343 /* Note that this includes discarded insts */
1344 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1346 /* Got to the end of a full instruction? */
1347 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1348 inst
->isLastOpInInst();
1350 /* lastPredictionSeqNum is kept as a convenience to prevent its
1351 * value from changing too much on the minorview display */
1352 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1354 /* Finished with the inst, remove it from the inst queue and
1355 * clear its dependencies */
1356 ex_info
.inFlightInsts
->pop();
1358 /* Complete barriers in the LSQ/move to store buffer */
1359 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1360 DPRINTF(MinorMem
, "Completing memory barrier"
1361 " inst: %s committed: %d\n", *inst
, committed_inst
);
1362 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1365 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1368 /* Handle per-cycle instruction counting */
1369 if (committed_inst
) {
1370 bool is_no_cost_inst
= inst
->isNoCostInst();
1372 /* Don't show no cost instructions as having taken a commit
1374 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1375 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1377 if (!is_no_cost_inst
)
1378 num_insts_committed
++;
1380 if (num_insts_committed
== commitLimit
)
1381 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1383 /* Re-set the time of the instruction if that's required for
1385 if (inst
->traceData
) {
1386 if (setTraceTimeOnCommit
)
1387 inst
->traceData
->setWhen(curTick());
1388 inst
->traceData
->dump();
1391 if (completed_mem_ref
)
1392 num_mem_refs_committed
++;
1394 if (num_mem_refs_committed
== memoryCommitLimit
)
1395 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1401 Execute::isInbetweenInsts(ThreadID thread_id
) const
1403 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1404 !lsq
.accessesInFlight();
1410 if (!inp
.outputWire
->isBubble())
1411 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1413 BranchData
&branch
= *out
.inputWire
;
1415 unsigned int num_issued
= 0;
1417 /* Do all the cycle-wise activities for dcachePort here to potentially
1418 * free up input spaces in the LSQ's requests queue */
1421 /* Check interrupts first. Will halt commit if interrupt found */
1422 bool interrupted
= false;
1423 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1425 if (interrupt_tid
!= InvalidThreadID
) {
1426 /* Signalling an interrupt this cycle, not issuing/committing from
1427 * any other threads */
1428 } else if (!branch
.isBubble()) {
1429 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1430 * without overwriting them */
1431 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1432 " branch to complete\n");
1434 ThreadID commit_tid
= getCommittingThread();
1436 if (commit_tid
!= InvalidThreadID
) {
1437 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1439 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1441 /* commit can set stalled flags observable to issue and so *must* be
1443 if (commit_info
.drainState
!= NotDraining
) {
1444 if (commit_info
.drainState
== DrainCurrentInst
) {
1445 /* Commit only micro-ops, don't kill anything else */
1446 commit(commit_tid
, true, false, branch
);
1448 if (isInbetweenInsts(commit_tid
))
1449 setDrainState(commit_tid
, DrainHaltFetch
);
1451 /* Discard any generated branch */
1452 branch
= BranchData::bubble();
1453 } else if (commit_info
.drainState
== DrainAllInsts
) {
1454 /* Kill all instructions */
1455 while (getInput(commit_tid
))
1456 popInput(commit_tid
);
1457 commit(commit_tid
, false, true, branch
);
1460 /* Commit micro-ops only if interrupted. Otherwise, commit
1461 * anything you like */
1462 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1464 bool only_commit_microops
= interrupted
&&
1465 hasInterrupt(commit_tid
);
1466 commit(commit_tid
, only_commit_microops
, false, branch
);
1469 /* Halt fetch, but don't do it until we have the current instruction in
1471 if (commit_info
.drainState
== DrainHaltFetch
) {
1472 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1473 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1475 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1476 setDrainState(commit_tid
, DrainAllInsts
);
1479 ThreadID issue_tid
= getIssuingThread();
1480 /* This will issue merrily even when interrupted in the sure and
1481 * certain knowledge that the interrupt with change the stream */
1482 if (issue_tid
!= InvalidThreadID
) {
1483 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1485 num_issued
= issue(issue_tid
);
1490 /* Run logic to step functional units + decide if we are active on the next
1492 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1493 bool can_issue_next
= false;
1495 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1496 /* Find the next issuable instruction for each thread and see if it can
1498 if (getInput(tid
)) {
1499 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1500 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1501 if (inst
->isFault()) {
1502 can_issue_next
= true;
1503 } else if (!inst
->isBubble()) {
1504 next_issuable_insts
.push_back(inst
);
1509 bool becoming_stalled
= true;
1511 /* Advance the pipelines and note whether they still need to be
1513 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1514 FUPipeline
*fu
= funcUnits
[i
];
1517 /* If we need to tick again, the pipeline will have been left or set
1518 * to be unstalled */
1519 if (fu
->occupancy
!=0 && !fu
->stalled
)
1520 becoming_stalled
= false;
1522 /* Could we possibly issue the next instruction from any thread?
1523 * This is quite an expensive test and is only used to determine
1524 * if the CPU should remain active, only run it if we aren't sure
1525 * we are active next cycle yet */
1526 for (auto inst
: next_issuable_insts
) {
1527 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1528 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1529 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1530 cpu
.getContext(inst
->id
.threadId
))) {
1531 can_issue_next
= true;
1537 bool head_inst_might_commit
= false;
1539 /* Could the head in flight insts be committed */
1540 for (auto const &info
: executeInfo
) {
1541 if (!info
.inFlightInsts
->empty()) {
1542 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1544 if (head_inst
.inst
->isNoCostInst()) {
1545 head_inst_might_commit
= true;
1547 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1549 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1550 lsq
.findResponse(head_inst
.inst
))
1552 head_inst_might_commit
= true;
1559 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1560 (num_issued
!= 0 ? " (issued some insts)" : ""),
1561 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1562 (can_issue_next
? " (can issued next inst)" : ""),
1563 (head_inst_might_commit
? "(head inst might commit)" : ""),
1564 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1565 (interrupted
? " (interrupted)" : ""));
1568 num_issued
!= 0 || /* Issued some insts this cycle */
1569 !becoming_stalled
|| /* Some FU pipelines can still move */
1570 can_issue_next
|| /* Can still issue a new inst */
1571 head_inst_might_commit
|| /* Could possible commit the next inst */
1572 lsq
.needsToTick() || /* Must step the dcache port */
1573 interrupted
; /* There are pending interrupts */
1575 if (!need_to_tick
) {
1576 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1577 " advanceable FUs\n");
1580 /* Wake up if we need to tick again */
1582 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1584 /* Note activity of following buffer */
1585 if (!branch
.isBubble())
1586 cpu
.activityRecorder
->activity();
1588 /* Make sure the input (if any left) is pushed */
1589 if (!inp
.outputWire
->isBubble())
1590 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1594 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1596 ThreadID tid
= interruptPriority
;
1597 /* Evaluate interrupts in round-robin based upon service */
1599 /* Has an interrupt been signalled? This may not be acted on
1600 * straighaway so this is different from took_interrupt */
1601 bool thread_interrupted
= false;
1603 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1604 /* This is here because it seems that after drainResume the
1605 * interrupt controller isn't always set */
1606 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1608 interrupted
= interrupted
|| thread_interrupted
;
1610 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1612 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1613 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1614 /* Act on interrupts */
1615 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1616 if (takeInterrupt(tid
, branch
)) {
1617 interruptPriority
= tid
;
1621 tid
= (tid
+ 1) % cpu
.numThreads
;
1623 } while (tid
!= interruptPriority
);
1625 return InvalidThreadID
;
1629 Execute::hasInterrupt(ThreadID thread_id
)
1631 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1632 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1633 isInterrupted(thread_id
);
1640 Execute::minorTrace() const
1642 std::ostringstream insts
;
1643 std::ostringstream stalled
;
1645 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1647 inputBuffer
[0].minorTrace();
1648 scoreboard
[0].minorTrace();
1650 /* Report functional unit stalling in one string */
1652 while (i
< numFuncUnits
)
1654 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1656 if (i
!= numFuncUnits
)
1660 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1661 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1662 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1663 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1665 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1666 std::mem_fun(&FUPipeline::minorTrace
));
1668 executeInfo
[0].inFlightInsts
->minorTrace();
1669 executeInfo
[0].inFUMemInsts
->minorTrace();
1673 Execute::getCommittingThread()
1675 std::vector
<ThreadID
> priority_list
;
1677 switch (cpu
.threadPolicy
) {
1678 case Enums::SingleThreaded
:
1680 case Enums::RoundRobin
:
1681 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1684 priority_list
= cpu
.randomPriority();
1687 panic("Invalid thread policy");
1690 for (auto tid
: priority_list
) {
1691 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1693 bool is_thread_active
=
1694 cpu
.getContext(tid
)->status() == ThreadContext::Active
;
1695 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1698 if (can_commit_insts
) {
1699 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1700 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1702 can_commit_insts
= can_commit_insts
&&
1703 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1706 bool can_transfer_mem_inst
= false;
1707 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1708 const MinorDynInstPtr head_mem_ref_inst
=
1709 ex_info
.inFUMemInsts
->front().inst
;
1710 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1711 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1712 can_transfer_mem_inst
=
1713 !fu_inst
->isBubble() &&
1714 fu_inst
->id
.threadId
== tid
&&
1716 fu_inst
->canEarlyIssue
&&
1717 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1720 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1721 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1722 inst
->fuIndex
!= noCostFUIndex
)
1724 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1725 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1726 fu_inst
.inst
->id
== inst
->id
;
1729 can_commit_insts
= can_commit_insts
&&
1730 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1735 if (can_commit_insts
) {
1736 commitPriority
= tid
;
1741 return InvalidThreadID
;
1745 Execute::getIssuingThread()
1747 std::vector
<ThreadID
> priority_list
;
1749 switch (cpu
.threadPolicy
) {
1750 case Enums::SingleThreaded
:
1752 case Enums::RoundRobin
:
1753 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1756 priority_list
= cpu
.randomPriority();
1759 panic("Invalid thread scheduling policy.");
1762 for (auto tid
: priority_list
) {
1763 if (cpu
.getContext(tid
)->status() == ThreadContext::Active
&&
1765 issuePriority
= tid
;
1770 return InvalidThreadID
;
1774 Execute::drainResume()
1776 DPRINTF(Drain
, "MinorExecute drainResume\n");
1778 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1779 setDrainState(tid
, NotDraining
);
1782 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1785 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1789 case Execute::NotDraining
:
1790 os
<< "NotDraining";
1792 case Execute::DrainCurrentInst
:
1793 os
<< "DrainCurrentInst";
1795 case Execute::DrainHaltFetch
:
1796 os
<< "DrainHaltFetch";
1798 case Execute::DrainAllInsts
:
1799 os
<< "DrainAllInsts";
1802 os
<< "Drain-" << static_cast<int>(state
);
1810 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1812 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1813 executeInfo
[thread_id
].drainState
= state
;
1819 DPRINTF(Drain
, "MinorExecute drain\n");
1821 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1822 if (executeInfo
[tid
].drainState
== NotDraining
) {
1823 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1825 /* Go to DrainCurrentInst if we're between microops
1826 * or waiting on an unbufferable memory operation.
1827 * Otherwise we can go straight to DrainHaltFetch
1829 if (isInbetweenInsts(tid
))
1830 setDrainState(tid
, DrainHaltFetch
);
1832 setDrainState(tid
, DrainCurrentInst
);
1835 return (isDrained() ? 0 : 1);
1839 Execute::isDrained()
1841 if (!lsq
.isDrained())
1844 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1845 if (!inputBuffer
[tid
].empty() ||
1846 !executeInfo
[tid
].inFlightInsts
->empty()) {
1857 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1858 delete funcUnits
[i
];
1860 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1861 delete executeInfo
[tid
].inFlightInsts
;
1865 Execute::instIsRightStream(MinorDynInstPtr inst
)
1867 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1871 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1875 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1876 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1881 MinorCPU::MinorCPUPort
&
1882 Execute::getDcachePort()
1884 return lsq
.getDcachePort();