2 * Copyright (c) 2013-2014,2018-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "cpu/minor/execute.hh"
40 #include "arch/locked_mem.hh"
41 #include "arch/registers.hh"
42 #include "arch/utility.hh"
43 #include "cpu/minor/cpu.hh"
44 #include "cpu/minor/exec_context.hh"
45 #include "cpu/minor/fetch1.hh"
46 #include "cpu/minor/lsq.hh"
47 #include "cpu/op_class.hh"
48 #include "debug/Activity.hh"
49 #include "debug/Branch.hh"
50 #include "debug/Drain.hh"
51 #include "debug/MinorExecute.hh"
52 #include "debug/MinorInterrupt.hh"
53 #include "debug/MinorMem.hh"
54 #include "debug/MinorTrace.hh"
55 #include "debug/PCEvent.hh"
60 Execute::Execute(const std::string
&name_
,
62 MinorCPUParams
¶ms
,
63 Latch
<ForwardInstData
>::Output inp_
,
64 Latch
<BranchData
>::Input out_
) :
69 issueLimit(params
.executeIssueLimit
),
70 memoryIssueLimit(params
.executeMemoryIssueLimit
),
71 commitLimit(params
.executeCommitLimit
),
72 memoryCommitLimit(params
.executeMemoryCommitLimit
),
73 processMoreThanOneInput(params
.executeCycleInput
),
74 fuDescriptions(*params
.executeFuncUnits
),
75 numFuncUnits(fuDescriptions
.funcUnits
.size()),
76 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
77 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
78 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
79 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
80 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
82 params
.executeMaxAccessesInMemory
,
83 params
.executeMemoryWidth
,
84 params
.executeLSQRequestsQueueSize
,
85 params
.executeLSQTransfersQueueSize
,
86 params
.executeLSQStoreBufferSize
,
87 params
.executeLSQMaxStoreBufferStoresPerCycle
),
88 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
93 if (commitLimit
< 1) {
94 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
99 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
103 if (memoryIssueLimit
< 1) {
104 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
108 if (memoryCommitLimit
> commitLimit
) {
109 fatal("%s: executeMemoryCommitLimit (%d) must be <="
110 " executeCommitLimit (%d)\n",
111 name_
, memoryCommitLimit
, commitLimit
);
114 if (params
.executeInputBufferSize
< 1) {
115 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
116 params
.executeInputBufferSize
);
119 if (params
.executeInputBufferSize
< 1) {
120 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
121 params
.executeInputBufferSize
);
124 /* This should be large enough to count all the in-FU instructions
125 * which need to be accounted for in the inFlightInsts
127 unsigned int total_slots
= 0;
129 /* Make FUPipelines for each MinorFU */
130 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
131 std::ostringstream fu_name
;
132 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
134 /* Note the total number of instruction slots (for sizing
135 * the inFlightInst queue) and the maximum latency of any FU
136 * (for sizing the activity recorder) */
137 total_slots
+= fu_description
->opLat
;
139 fu_name
<< name_
<< ".fu." << i
;
141 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
143 funcUnits
.push_back(fu
);
146 /** Check that there is a functional unit for all operation classes */
147 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
148 bool found_fu
= false;
149 unsigned int fu_index
= 0;
151 while (fu_index
< numFuncUnits
&& !found_fu
)
153 if (funcUnits
[fu_index
]->provides(
154 static_cast<OpClass
>(op_class
)))
162 warn("No functional unit for OpClass %s\n",
163 Enums::OpClassStrings
[op_class
]);
167 /* Per-thread structures */
168 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
169 std::string tid_str
= std::to_string(tid
);
172 inputBuffer
.push_back(
173 InputBuffer
<ForwardInstData
>(
174 name_
+ ".inputBuffer" + tid_str
, "insts",
175 params
.executeInputBufferSize
));
178 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
180 /* In-flight instruction records */
181 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
182 ReportTraitsAdaptor
<QueuedInst
> >(
183 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
185 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
186 ReportTraitsAdaptor
<QueuedInst
> >(
187 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
191 const ForwardInstData
*
192 Execute::getInput(ThreadID tid
)
194 /* Get a line from the inputBuffer to work with */
195 if (!inputBuffer
[tid
].empty()) {
196 const ForwardInstData
&head
= inputBuffer
[tid
].front();
198 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
205 Execute::popInput(ThreadID tid
)
207 if (!inputBuffer
[tid
].empty())
208 inputBuffer
[tid
].pop();
210 executeInfo
[tid
].inputIndex
= 0;
214 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
216 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
217 const TheISA::PCState
&pc_before
= inst
->pc
;
218 TheISA::PCState target
= thread
->pcState();
220 /* Force a branch for SerializeAfter/SquashAfter instructions
221 * at the end of micro-op sequence when we're not suspended */
222 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
224 inst
->isLastOpInInst() &&
225 (inst
->staticInst
->isSerializeAfter() ||
226 inst
->staticInst
->isSquashAfter() ||
227 inst
->staticInst
->isIprAccess());
229 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
230 pc_before
, target
, (force_branch
? " (forcing)" : ""));
232 /* Will we change the PC to something other than the next instruction? */
233 bool must_branch
= pc_before
!= target
||
237 /* The reason for the branch data we're about to generate, set below */
238 BranchData::Reason reason
= BranchData::NoBranch
;
240 if (fault
== NoFault
)
242 TheISA::advancePC(target
, inst
->staticInst
);
243 thread
->pcState(target
);
245 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
249 if (inst
->predictedTaken
&& !force_branch
) {
250 /* Predicted to branch */
252 /* No branch was taken, change stream to get us back to the
253 * intended PC value */
254 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
255 " none happened inst: %s\n",
256 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
258 reason
= BranchData::BadlyPredictedBranch
;
259 } else if (inst
->predictedTarget
== target
) {
260 /* Branch prediction got the right target, kill the branch and
262 * Note that this information to the branch predictor might get
263 * overwritten by a "real" branch during this cycle */
264 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
266 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
268 reason
= BranchData::CorrectlyPredictedBranch
;
270 /* Branch prediction got the wrong target */
271 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
272 " but got the wrong target (actual: 0x%x) inst: %s\n",
273 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
274 target
.instAddr(), *inst
);
276 reason
= BranchData::BadlyPredictedBranchTarget
;
278 } else if (must_branch
) {
279 /* Unpredicted branch */
280 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
281 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
283 reason
= BranchData::UnpredictedBranch
;
285 /* No branch at all */
286 reason
= BranchData::NoBranch
;
289 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
293 Execute::updateBranchData(
295 BranchData::Reason reason
,
296 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
299 if (reason
!= BranchData::NoBranch
) {
300 /* Bump up the stream sequence number on a real branch*/
301 if (BranchData::isStreamChange(reason
))
302 executeInfo
[tid
].streamSeqNum
++;
304 /* Branches (even mis-predictions) don't change the predictionSeqNum,
305 * just the streamSeqNum */
306 branch
= BranchData(reason
, tid
,
307 executeInfo
[tid
].streamSeqNum
,
308 /* Maintaining predictionSeqNum if there's no inst is just a
309 * courtesy and looks better on minorview */
310 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
311 : inst
->id
.predictionSeqNum
),
314 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
319 Execute::handleMemResponse(MinorDynInstPtr inst
,
320 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
322 ThreadID thread_id
= inst
->id
.threadId
;
323 ThreadContext
*thread
= cpu
.getContext(thread_id
);
325 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
327 PacketPtr packet
= response
->packet
;
329 bool is_load
= inst
->staticInst
->isLoad();
330 bool is_store
= inst
->staticInst
->isStore();
331 bool is_atomic
= inst
->staticInst
->isAtomic();
332 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
334 /* If true, the trace's predicate value will be taken from the exec
335 * context predicate, otherwise, it will be set to false */
336 bool use_context_predicate
= true;
338 if (inst
->translationFault
!= NoFault
) {
339 /* Invoke memory faults. */
340 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
341 inst
->translationFault
->name());
343 if (inst
->staticInst
->isPrefetch()) {
344 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
345 inst
->translationFault
->name());
347 /* Don't assign to fault */
349 /* Take the fault raised during the TLB/memory access */
350 fault
= inst
->translationFault
;
352 fault
->invoke(thread
, inst
->staticInst
);
354 } else if (!packet
) {
355 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
357 use_context_predicate
= false;
358 if (!context
.readMemAccPredicate())
359 inst
->staticInst
->completeAcc(nullptr, &context
, inst
->traceData
);
360 } else if (packet
->isError()) {
361 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
364 fatal("Received error response packet for inst: %s\n", *inst
);
365 } else if (is_store
|| is_load
|| is_prefetch
|| is_atomic
) {
368 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
369 *inst
, packet
->getAddr(), packet
->getSize());
371 if (is_load
&& packet
->getSize() > 0) {
372 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
373 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
376 /* Complete the memory access instruction */
377 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
380 if (fault
!= NoFault
) {
381 /* Invoke fault created by instruction completion */
382 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
384 fault
->invoke(thread
, inst
->staticInst
);
386 /* Stores need to be pushed into the store buffer to finish
388 if (response
->needsToBeSentToStoreBuffer())
389 lsq
.sendStoreToStoreBuffer(response
);
392 fatal("There should only ever be reads, "
393 "writes or faults at this point\n");
396 lsq
.popResponse(response
);
398 if (inst
->traceData
) {
399 inst
->traceData
->setPredicate((use_context_predicate
?
400 context
.readPredicate() : false));
403 doInstCommitAccounting(inst
);
405 /* Generate output to account for branches */
406 tryToBranch(inst
, fault
, branch
);
410 Execute::isInterrupted(ThreadID thread_id
) const
412 return cpu
.checkInterrupts(thread_id
);
416 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
418 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
419 cpu
.getContext(thread_id
)->pcState());
421 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt();
423 if (interrupt
!= NoFault
) {
424 /* The interrupt *must* set pcState */
425 cpu
.getInterruptController(thread_id
)->updateIntrInfo();
426 interrupt
->invoke(cpu
.getContext(thread_id
));
428 assert(!lsq
.accessesInFlight());
430 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
431 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
433 /* Assume that an interrupt *must* cause a branch. Assert this? */
435 updateBranchData(thread_id
, BranchData::Interrupt
,
436 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
440 return interrupt
!= NoFault
;
444 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
445 bool &passed_predicate
, Fault
&fault
)
449 /* Set to true if the mem op. is issued and sent to the mem system */
450 passed_predicate
= false;
452 if (!lsq
.canRequest()) {
453 /* Not acting on instruction yet as the memory
457 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
458 TheISA::PCState old_pc
= thread
->pcState();
460 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
463 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
465 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
469 if (init_fault
!= NoFault
) {
470 assert(inst
->translationFault
!= NoFault
);
471 // Translation faults are dealt with in handleMemResponse()
472 init_fault
= NoFault
;
474 // If we have a translation fault then it got suppressed by
476 inst
->translationFault
= NoFault
;
480 if (init_fault
!= NoFault
) {
481 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
482 " initiateAcc: %s\n", *inst
, init_fault
->name());
485 /* Only set this if the instruction passed its
487 if (!context
.readMemAccPredicate()) {
488 DPRINTF(MinorMem
, "No memory access for inst: %s\n", *inst
);
489 assert(context
.readPredicate());
491 passed_predicate
= context
.readPredicate();
493 /* Set predicate in tracing */
495 inst
->traceData
->setPredicate(passed_predicate
);
497 /* If the instruction didn't pass its predicate
498 * or it is a predicated vector instruction and the
499 * associated predicate register is all-false (and so will not
500 * progress from here) Try to branch to correct and branch
503 /* Leave it up to commit to handle the fault */
504 lsq
.pushFailedRequest(inst
);
509 /* Restore thread PC */
510 thread
->pcState(old_pc
);
517 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
519 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
521 unsigned int ret
= index
+ 1;
523 if (ret
== cycle_size
)
529 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
531 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
536 ret
= cycle_size
- 1;
542 Execute::issue(ThreadID thread_id
)
544 const ForwardInstData
*insts_in
= getInput(thread_id
);
545 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
547 /* Early termination if we have no instructions */
551 /* Start from the first FU */
552 unsigned int fu_index
= 0;
554 /* Remains true while instructions are still being issued. If any
555 * instruction fails to issue, this is set to false and we exit issue.
556 * This strictly enforces in-order issue. For other issue behaviours,
557 * a more complicated test in the outer while loop below is needed. */
560 /* Number of insts issues this cycle to check for issueLimit */
561 unsigned num_insts_issued
= 0;
563 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
564 unsigned num_mem_insts_issued
= 0;
566 /* Number of instructions discarded this cycle in order to enforce a
567 * discardLimit. @todo, add that parameter? */
568 unsigned num_insts_discarded
= 0;
571 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
572 Fault fault
= inst
->fault
;
573 bool discarded
= false;
574 bool issued_mem_ref
= false;
576 if (inst
->isBubble()) {
579 } else if (cpu
.getContext(thread_id
)->status() ==
580 ThreadContext::Suspended
)
582 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
587 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
588 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
589 " state was unexpected, expected: %d\n",
590 *inst
, thread
.streamSeqNum
);
594 /* Try and issue an instruction into an FU, assume we didn't and
595 * fix that in the loop */
598 /* Try FU from 0 each instruction */
601 /* Try and issue a single instruction stepping through the
604 FUPipeline
*fu
= funcUnits
[fu_index
];
606 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
609 /* Does the examined fu have the OpClass-related capability
610 * needed to execute this instruction? Faults can always
611 * issue to any FU but probably should just 'live' in the
612 * inFlightInsts queue rather than having an FU. */
613 bool fu_is_capable
= (!inst
->isFault() ?
614 fu
->provides(inst
->staticInst
->opClass()) : true);
616 if (inst
->isNoCostInst()) {
617 /* Issue free insts. to a fake numbered FU */
618 fu_index
= noCostFUIndex
;
620 /* And start the countdown on activity to allow
621 * this instruction to get to the end of its FU */
622 cpu
.activityRecorder
->activity();
624 /* Mark the destinations for this instruction as
626 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
627 Cycles(0), cpu
.getContext(thread_id
), false);
629 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
630 inst
->fuIndex
= noCostFUIndex
;
631 inst
->extraCommitDelay
= Cycles(0);
632 inst
->extraCommitDelayExpr
= NULL
;
634 /* Push the instruction onto the inFlight queue so
635 * it can be committed in order */
636 QueuedInst
fu_inst(inst
);
637 thread
.inFlightInsts
->push(fu_inst
);
641 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
643 if (!fu_is_capable
) {
644 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
645 " capable\n", fu_index
);
647 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
648 " already busy\n", fu_index
);
650 } else if (fu
->stalled
) {
651 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
654 } else if (!fu
->canInsert()) {
655 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
656 " for another: %d cycles\n",
657 *inst
, fu
->cyclesBeforeInsert());
659 MinorFUTiming
*timing
= (!inst
->isFault() ?
660 fu
->findTiming(inst
->staticInst
) : NULL
);
662 const std::vector
<Cycles
> *src_latencies
=
663 (timing
? &(timing
->srcRegsRelativeLats
)
666 const std::vector
<bool> *cant_forward_from_fu_indices
=
667 &(fu
->cantForwardFromFUIndices
);
669 if (timing
&& timing
->suppress
) {
670 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
671 " decoding is suppressing it\n",
673 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
674 src_latencies
, cant_forward_from_fu_indices
,
675 cpu
.curCycle(), cpu
.getContext(thread_id
)))
677 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
680 /* Can insert the instruction into this FU */
681 DPRINTF(MinorExecute
, "Issuing inst: %s"
682 " into FU %d\n", *inst
,
685 Cycles extra_dest_retire_lat
= Cycles(0);
686 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
687 Cycles extra_assumed_lat
= Cycles(0);
689 /* Add the extraCommitDelay and extraAssumeLat to
690 * the FU pipeline timings */
692 extra_dest_retire_lat
=
693 timing
->extraCommitLat
;
694 extra_dest_retire_lat_expr
=
695 timing
->extraCommitLatExpr
;
697 timing
->extraAssumedLat
;
700 issued_mem_ref
= inst
->isMemRef();
702 QueuedInst
fu_inst(inst
);
704 /* Decorate the inst with FU details */
705 inst
->fuIndex
= fu_index
;
706 inst
->extraCommitDelay
= extra_dest_retire_lat
;
707 inst
->extraCommitDelayExpr
=
708 extra_dest_retire_lat_expr
;
710 if (issued_mem_ref
) {
711 /* Remember which instruction this memory op
712 * depends on so that initiateAcc can be called
714 if (allowEarlyMemIssue
) {
715 inst
->instToWaitFor
=
716 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
717 cpu
.getContext(thread_id
));
719 if (lsq
.getLastMemBarrier(thread_id
) >
722 DPRINTF(MinorExecute
, "A barrier will"
723 " cause a delay in mem ref issue of"
724 " inst: %s until after inst"
725 " %d(exec)\n", *inst
,
726 lsq
.getLastMemBarrier(thread_id
));
728 inst
->instToWaitFor
=
729 lsq
.getLastMemBarrier(thread_id
);
731 DPRINTF(MinorExecute
, "Memory ref inst:"
732 " %s must wait for inst %d(exec)"
734 *inst
, inst
->instToWaitFor
);
737 inst
->canEarlyIssue
= true;
739 /* Also queue this instruction in the memory ref
740 * queue to ensure in-order issue to the LSQ */
741 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
743 thread
.inFUMemInsts
->push(fu_inst
);
748 /* And start the countdown on activity to allow
749 * this instruction to get to the end of its FU */
750 cpu
.activityRecorder
->activity();
752 /* Mark the destinations for this instruction as
754 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
755 fu
->description
.opLat
+
756 extra_dest_retire_lat
+
758 cpu
.getContext(thread_id
),
759 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
761 /* Push the instruction onto the inFlight queue so
762 * it can be committed in order */
763 thread
.inFlightInsts
->push(fu_inst
);
770 } while (fu_index
!= numFuncUnits
&& !issued
);
773 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
777 /* Generate MinorTrace's MinorInst lines. Do this at commit
778 * to allow better instruction annotation? */
779 if (DTRACE(MinorTrace
) && !inst
->isBubble())
780 inst
->minorTraceInst(*this);
782 /* Mark up barriers in the LSQ */
783 if (!discarded
&& inst
->isInst() &&
784 inst
->staticInst
->isMemBarrier())
786 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
787 lsq
.issuedMemBarrierInst(inst
);
790 if (inst
->traceData
&& setTraceTimeOnIssue
) {
791 inst
->traceData
->setWhen(curTick());
795 num_mem_insts_issued
++;
798 num_insts_discarded
++;
799 } else if (!inst
->isBubble()) {
802 if (num_insts_issued
== issueLimit
)
803 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
807 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
811 /* Got to the end of a line */
812 if (thread
.inputIndex
== insts_in
->width()) {
814 /* Set insts_in to null to force us to leave the surrounding
818 if (processMoreThanOneInput
) {
819 DPRINTF(MinorExecute
, "Wrapping\n");
820 insts_in
= getInput(thread_id
);
823 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
824 /* We still have instructions */
825 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
826 issued
&& /* We've not yet failed to issue an instruction */
827 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
828 num_mem_insts_issued
!= memoryIssueLimit
);
830 return num_insts_issued
;
834 Execute::tryPCEvents(ThreadID thread_id
)
836 ThreadContext
*thread
= cpu
.getContext(thread_id
);
837 unsigned int num_pc_event_checks
= 0;
839 /* Handle PC events on instructions */
842 oldPC
= thread
->instAddr();
843 cpu
.threads
[thread_id
]->pcEventQueue
.service(oldPC
, thread
);
844 num_pc_event_checks
++;
845 } while (oldPC
!= thread
->instAddr());
847 if (num_pc_event_checks
> 1) {
848 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
852 return num_pc_event_checks
> 1;
856 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
858 assert(!inst
->isFault());
860 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
862 /* Increment the many and various inst and op counts in the
863 * thread and system */
864 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
868 cpu
.stats
.numInsts
++;
869 cpu
.system
->totalNumInsts
++;
871 /* Act on events related to instruction counts */
872 thread
->comInstEventQueue
.serviceEvents(thread
->numInst
);
877 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
878 [inst
->staticInst
->opClass()]++;
880 /* Set the CP SeqNum to the numOps commit number */
882 inst
->traceData
->setCPSeq(thread
->numOp
);
884 cpu
.probeInstCommit(inst
->staticInst
, inst
->pc
.instAddr());
888 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
889 BranchData
&branch
, Fault
&fault
, bool &committed
,
890 bool &completed_mem_issue
)
892 ThreadID thread_id
= inst
->id
.threadId
;
893 ThreadContext
*thread
= cpu
.getContext(thread_id
);
895 bool completed_inst
= true;
898 /* Is the thread for this instruction suspended? In that case, just
899 * stall as long as there are no pending interrupts */
900 if (thread
->status() == ThreadContext::Suspended
&&
901 !isInterrupted(thread_id
))
903 panic("We should never hit the case where we try to commit from a "
904 "suspended thread as the streamSeqNum should not match");
905 } else if (inst
->isFault()) {
906 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
908 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
909 inst
->fault
->name());
912 inst
->fault
->invoke(thread
, NULL
);
914 tryToBranch(inst
, fault
, branch
);
915 } else if (inst
->staticInst
->isMemRef()) {
916 /* Memory accesses are executed in two parts:
917 * executeMemRefInst -- calculates the EA and issues the access
918 * to memory. This is done here.
919 * handleMemResponse -- handles the response packet, done by
922 * While the memory access is in its FU, the EA is being
923 * calculated. At the end of the FU, when it is ready to
924 * 'commit' (in this function), the access is presented to the
925 * memory queues. When a response comes back from memory,
926 * Execute::commit will commit it.
928 bool predicate_passed
= false;
929 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
930 predicate_passed
, fault
);
932 if (completed_mem_inst
&& fault
!= NoFault
) {
933 if (early_memory_issue
) {
934 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
936 /* Don't execute the fault, just stall the instruction
937 * until it gets to the head of inFlightInsts */
938 inst
->canEarlyIssue
= false;
939 /* Not completed as we'll come here again to pick up
940 * the fault when we get to the end of the FU */
941 completed_inst
= false;
943 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
945 fault
->invoke(thread
, NULL
);
947 tryToBranch(inst
, fault
, branch
);
948 completed_inst
= true;
951 completed_inst
= completed_mem_inst
;
953 completed_mem_issue
= completed_inst
;
954 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
955 !lsq
.canPushIntoStoreBuffer())
957 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
958 " there isn't space in the store buffer\n", *inst
);
960 completed_inst
= false;
961 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
962 && !branch
.isBubble()){
963 /* This instruction can suspend, need to be able to communicate
964 * backwards, so no other branches may evaluate this cycle*/
965 completed_inst
= false;
967 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
969 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
971 fault
= inst
->staticInst
->execute(&context
,
974 /* Set the predicate for tracing and dump */
976 inst
->traceData
->setPredicate(context
.readPredicate());
980 if (fault
!= NoFault
) {
981 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
982 *inst
, fault
->name());
983 fault
->invoke(thread
, inst
->staticInst
);
986 doInstCommitAccounting(inst
);
987 tryToBranch(inst
, fault
, branch
);
990 if (completed_inst
) {
991 /* Keep a copy of this instruction's predictionSeqNum just in case
992 * we need to issue a branch without an instruction (such as an
994 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
996 /* Check to see if this instruction suspended the current thread. */
997 if (!inst
->isFault() &&
998 thread
->status() == ThreadContext::Suspended
&&
999 branch
.isBubble() && /* It didn't branch too */
1000 !isInterrupted(thread_id
)) /* Don't suspend if we have
1003 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
1005 assert(resume_pc
.microPC() == 0);
1007 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
1008 " inst: %s\n", thread_id
, *inst
);
1010 cpu
.stats
.numFetchSuspends
++;
1012 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
1017 return completed_inst
;
1021 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1024 Fault fault
= NoFault
;
1025 Cycles now
= cpu
.curCycle();
1026 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1029 * Try and execute as many instructions from the end of FU pipelines as
1030 * possible. This *doesn't* include actually advancing the pipelines.
1032 * We do this by looping on the front of the inFlightInsts queue for as
1033 * long as we can find the desired instruction at the end of the
1034 * functional unit it was issued to without seeing a branch or a fault.
1035 * In this function, these terms are used:
1036 * complete -- The instruction has finished its passage through
1037 * its functional unit and its fate has been decided
1038 * (committed, discarded, issued to the memory system)
1039 * commit -- The instruction is complete(d), not discarded and has
1040 * its effects applied to the CPU state
1041 * discard(ed) -- The instruction is complete but not committed
1042 * as its streamSeqNum disagrees with the current
1043 * Execute::streamSeqNum
1045 * Commits are also possible from two other places:
1047 * 1) Responses returning from the LSQ
1048 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1049 * than their position in the inFlightInsts queue, but after all
1050 * their dependencies are resolved.
1053 /* Has an instruction been completed? Once this becomes false, we stop
1054 * trying to complete instructions. */
1055 bool completed_inst
= true;
1057 /* Number of insts committed this cycle to check against commitLimit */
1058 unsigned int num_insts_committed
= 0;
1060 /* Number of memory access instructions committed to check against
1062 unsigned int num_mem_refs_committed
= 0;
1064 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1065 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1066 *(ex_info
.inFlightInsts
->front().inst
),
1067 ex_info
.lastCommitWasEndOfMacroop
);
1070 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1071 !branch
.isStreamChange() && /* No real branch */
1072 fault
== NoFault
&& /* No faults */
1073 completed_inst
&& /* Still finding instructions to execute */
1074 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1077 if (only_commit_microops
) {
1078 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1080 *(ex_info
.inFlightInsts
->front().inst
));
1083 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1085 InstSeqNum head_exec_seq_num
=
1086 head_inflight_inst
->inst
->id
.execSeqNum
;
1088 /* The instruction we actually process if completed_inst
1089 * remains true to the end of the loop body.
1090 * Start by considering the the head of the in flight insts queue */
1091 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1093 bool committed_inst
= false;
1094 bool discard_inst
= false;
1095 bool completed_mem_ref
= false;
1096 bool issued_mem_ref
= false;
1097 bool early_memory_issue
= false;
1099 /* Must set this again to go around the loop */
1100 completed_inst
= false;
1102 /* If we're just completing a macroop before an interrupt or drain,
1103 * can we stil commit another microop (rather than a memory response)
1104 * without crosing into the next full instruction? */
1105 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1106 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1108 /* Can we find a mem response for this inst */
1109 LSQ::LSQRequestPtr mem_response
=
1110 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1112 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1115 /* Test for PC events after every instruction */
1116 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1117 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1119 /* Branch as there was a change in PC */
1120 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1121 MinorDynInst::bubble(), thread
->pcState(), branch
);
1122 } else if (mem_response
&&
1123 num_mem_refs_committed
< memoryCommitLimit
)
1125 /* Try to commit from the memory responses next */
1126 discard_inst
= inst
->id
.streamSeqNum
!=
1127 ex_info
.streamSeqNum
|| discard
;
1129 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1132 /* Complete or discard the response */
1134 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1135 " stream state was unexpected, expected: %d\n",
1136 *inst
, ex_info
.streamSeqNum
);
1138 lsq
.popResponse(mem_response
);
1140 handleMemResponse(inst
, mem_response
, branch
, fault
);
1141 committed_inst
= true;
1144 completed_mem_ref
= true;
1145 completed_inst
= true;
1146 } else if (can_commit_insts
) {
1147 /* If true, this instruction will, subject to timing tweaks,
1148 * be considered for completion. try_to_commit flattens
1149 * the `if' tree a bit and allows other tests for inst
1150 * commit to be inserted here. */
1151 bool try_to_commit
= false;
1153 /* Try and issue memory ops early if they:
1154 * - Can push a request into the LSQ
1155 * - Have reached the end of their FUs
1156 * - Have had all their dependencies satisfied
1157 * - Are from the right stream
1159 * For any other case, leave it to the normal instruction
1160 * issue below to handle them.
1162 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1163 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1165 const MinorDynInstPtr head_mem_ref_inst
=
1166 ex_info
.inFUMemInsts
->front().inst
;
1167 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1168 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1170 /* Use this, possibly out of order, inst as the one
1171 * to 'commit'/send to the LSQ */
1172 if (!fu_inst
->isBubble() &&
1174 fu_inst
->canEarlyIssue
&&
1175 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1176 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1178 DPRINTF(MinorExecute
, "Issuing mem ref early"
1179 " inst: %s instToWaitFor: %d\n",
1180 *(fu_inst
), fu_inst
->instToWaitFor
);
1183 try_to_commit
= true;
1184 early_memory_issue
= true;
1185 completed_inst
= true;
1189 /* Try and commit FU-less insts */
1190 if (!completed_inst
&& inst
->isNoCostInst()) {
1191 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1193 try_to_commit
= true;
1194 completed_inst
= true;
1197 /* Try to issue from the ends of FUs and the inFlightInsts
1199 if (!completed_inst
&& !inst
->inLSQ
) {
1200 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1202 /* Try to commit from a functional unit */
1203 /* Is the head inst of the expected inst's FU actually the
1205 QueuedInst
&fu_inst
=
1206 funcUnits
[inst
->fuIndex
]->front();
1207 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1209 if (fu_inst
.inst
->isBubble()) {
1210 /* No instruction ready */
1211 completed_inst
= false;
1212 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1213 /* Past instruction: we must have already executed it
1214 * in the same cycle and so the head inst isn't
1215 * actually at the end of its pipeline
1216 * Future instruction: handled above and only for
1217 * mem refs on their way to the LSQ */
1218 } else if (fu_inst
.inst
->id
== inst
->id
) {
1219 /* All instructions can be committed if they have the
1220 * right execSeqNum and there are no in-flight
1221 * mem insts before us */
1222 try_to_commit
= true;
1223 completed_inst
= true;
1227 if (try_to_commit
) {
1228 discard_inst
= inst
->id
.streamSeqNum
!=
1229 ex_info
.streamSeqNum
|| discard
;
1231 /* Is this instruction discardable as its streamSeqNum
1233 if (!discard_inst
) {
1234 /* Try to commit or discard a non-memory instruction.
1235 * Memory ops are actually 'committed' from this FUs
1236 * and 'issued' into the memory system so we need to
1237 * account for them later (commit_was_mem_issue gets
1239 if (inst
->extraCommitDelayExpr
) {
1240 DPRINTF(MinorExecute
, "Evaluating expression for"
1241 " extra commit delay inst: %s\n", *inst
);
1243 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1245 TimingExprEvalContext
context(inst
->staticInst
,
1248 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1251 DPRINTF(MinorExecute
, "Extra commit delay expr"
1252 " result: %d\n", extra_delay
);
1254 if (extra_delay
< 128) {
1255 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1257 DPRINTF(MinorExecute
, "Extra commit delay was"
1258 " very long: %d\n", extra_delay
);
1260 inst
->extraCommitDelayExpr
= NULL
;
1263 /* Move the extraCommitDelay from the instruction
1264 * into the minimumCommitCycle */
1265 if (inst
->extraCommitDelay
!= Cycles(0)) {
1266 inst
->minimumCommitCycle
= cpu
.curCycle() +
1267 inst
->extraCommitDelay
;
1268 inst
->extraCommitDelay
= Cycles(0);
1271 /* @todo Think about making lastMemBarrier be
1272 * MAX_UINT_64 to avoid using 0 as a marker value */
1273 if (!inst
->isFault() && inst
->isMemRef() &&
1274 lsq
.getLastMemBarrier(thread_id
) <
1275 inst
->id
.execSeqNum
&&
1276 lsq
.getLastMemBarrier(thread_id
) != 0)
1278 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1279 " as there are incomplete barriers in flight\n",
1281 completed_inst
= false;
1282 } else if (inst
->minimumCommitCycle
> now
) {
1283 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1284 " as it wants to be stalled for %d more cycles\n",
1285 *inst
, inst
->minimumCommitCycle
- now
);
1286 completed_inst
= false;
1288 completed_inst
= commitInst(inst
,
1289 early_memory_issue
, branch
, fault
,
1290 committed_inst
, issued_mem_ref
);
1293 /* Discard instruction */
1294 completed_inst
= true;
1297 if (completed_inst
) {
1298 /* Allow the pipeline to advance. If the FU head
1299 * instruction wasn't the inFlightInsts head
1300 * but had already been committed, it would have
1301 * unstalled the pipeline before here */
1302 if (inst
->fuIndex
!= noCostFUIndex
) {
1303 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1304 funcUnits
[inst
->fuIndex
]->stalled
= false;
1309 DPRINTF(MinorExecute
, "No instructions to commit\n");
1310 completed_inst
= false;
1313 /* All discardable instructions must also be 'completed' by now */
1314 assert(!(discard_inst
&& !completed_inst
));
1316 /* Instruction committed but was discarded due to streamSeqNum
1319 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1320 " state was unexpected, expected: %d\n",
1321 *inst
, ex_info
.streamSeqNum
);
1323 if (fault
== NoFault
)
1324 cpu
.stats
.numDiscardedOps
++;
1327 /* Mark the mem inst as being in the LSQ */
1328 if (issued_mem_ref
) {
1333 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1334 * as they've *definitely* exited the FUs */
1335 if (completed_inst
&& inst
->isMemRef()) {
1336 /* The MemRef could have been discarded from the FU or the memory
1337 * queue, so just check an FU instruction */
1338 if (!ex_info
.inFUMemInsts
->empty() &&
1339 ex_info
.inFUMemInsts
->front().inst
== inst
)
1341 ex_info
.inFUMemInsts
->pop();
1345 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1346 /* Note that this includes discarded insts */
1347 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1349 /* Got to the end of a full instruction? */
1350 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1351 inst
->isLastOpInInst();
1353 /* lastPredictionSeqNum is kept as a convenience to prevent its
1354 * value from changing too much on the minorview display */
1355 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1357 /* Finished with the inst, remove it from the inst queue and
1358 * clear its dependencies */
1359 ex_info
.inFlightInsts
->pop();
1361 /* Complete barriers in the LSQ/move to store buffer */
1362 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1363 DPRINTF(MinorMem
, "Completing memory barrier"
1364 " inst: %s committed: %d\n", *inst
, committed_inst
);
1365 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1368 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1371 /* Handle per-cycle instruction counting */
1372 if (committed_inst
) {
1373 bool is_no_cost_inst
= inst
->isNoCostInst();
1375 /* Don't show no cost instructions as having taken a commit
1377 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1378 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1380 if (!is_no_cost_inst
)
1381 num_insts_committed
++;
1383 if (num_insts_committed
== commitLimit
)
1384 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1386 /* Re-set the time of the instruction if that's required for
1388 if (inst
->traceData
) {
1389 if (setTraceTimeOnCommit
)
1390 inst
->traceData
->setWhen(curTick());
1391 inst
->traceData
->dump();
1394 if (completed_mem_ref
)
1395 num_mem_refs_committed
++;
1397 if (num_mem_refs_committed
== memoryCommitLimit
)
1398 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1404 Execute::isInbetweenInsts(ThreadID thread_id
) const
1406 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1407 !lsq
.accessesInFlight();
1413 if (!inp
.outputWire
->isBubble())
1414 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1416 BranchData
&branch
= *out
.inputWire
;
1418 unsigned int num_issued
= 0;
1420 /* Do all the cycle-wise activities for dcachePort here to potentially
1421 * free up input spaces in the LSQ's requests queue */
1424 /* Check interrupts first. Will halt commit if interrupt found */
1425 bool interrupted
= false;
1426 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1428 if (interrupt_tid
!= InvalidThreadID
) {
1429 /* Signalling an interrupt this cycle, not issuing/committing from
1430 * any other threads */
1431 } else if (!branch
.isBubble()) {
1432 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1433 * without overwriting them */
1434 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1435 " branch to complete\n");
1437 ThreadID commit_tid
= getCommittingThread();
1439 if (commit_tid
!= InvalidThreadID
) {
1440 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1442 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1444 /* commit can set stalled flags observable to issue and so *must* be
1446 if (commit_info
.drainState
!= NotDraining
) {
1447 if (commit_info
.drainState
== DrainCurrentInst
) {
1448 /* Commit only micro-ops, don't kill anything else */
1449 commit(commit_tid
, true, false, branch
);
1451 if (isInbetweenInsts(commit_tid
))
1452 setDrainState(commit_tid
, DrainHaltFetch
);
1454 /* Discard any generated branch */
1455 branch
= BranchData::bubble();
1456 } else if (commit_info
.drainState
== DrainAllInsts
) {
1457 /* Kill all instructions */
1458 while (getInput(commit_tid
))
1459 popInput(commit_tid
);
1460 commit(commit_tid
, false, true, branch
);
1463 /* Commit micro-ops only if interrupted. Otherwise, commit
1464 * anything you like */
1465 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1467 bool only_commit_microops
= interrupted
&&
1468 hasInterrupt(commit_tid
);
1469 commit(commit_tid
, only_commit_microops
, false, branch
);
1472 /* Halt fetch, but don't do it until we have the current instruction in
1474 if (commit_info
.drainState
== DrainHaltFetch
) {
1475 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1476 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1478 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1479 setDrainState(commit_tid
, DrainAllInsts
);
1482 ThreadID issue_tid
= getIssuingThread();
1483 /* This will issue merrily even when interrupted in the sure and
1484 * certain knowledge that the interrupt with change the stream */
1485 if (issue_tid
!= InvalidThreadID
) {
1486 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1488 num_issued
= issue(issue_tid
);
1493 /* Run logic to step functional units + decide if we are active on the next
1495 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1496 bool can_issue_next
= false;
1498 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1499 /* Find the next issuable instruction for each thread and see if it can
1501 if (getInput(tid
)) {
1502 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1503 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1504 if (inst
->isFault()) {
1505 can_issue_next
= true;
1506 } else if (!inst
->isBubble()) {
1507 next_issuable_insts
.push_back(inst
);
1512 bool becoming_stalled
= true;
1514 /* Advance the pipelines and note whether they still need to be
1516 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1517 FUPipeline
*fu
= funcUnits
[i
];
1520 /* If we need to tick again, the pipeline will have been left or set
1521 * to be unstalled */
1522 if (fu
->occupancy
!=0 && !fu
->stalled
)
1523 becoming_stalled
= false;
1525 /* Could we possibly issue the next instruction from any thread?
1526 * This is quite an expensive test and is only used to determine
1527 * if the CPU should remain active, only run it if we aren't sure
1528 * we are active next cycle yet */
1529 for (auto inst
: next_issuable_insts
) {
1530 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1531 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1532 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1533 cpu
.getContext(inst
->id
.threadId
))) {
1534 can_issue_next
= true;
1540 bool head_inst_might_commit
= false;
1542 /* Could the head in flight insts be committed */
1543 for (auto const &info
: executeInfo
) {
1544 if (!info
.inFlightInsts
->empty()) {
1545 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1547 if (head_inst
.inst
->isNoCostInst()) {
1548 head_inst_might_commit
= true;
1550 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1552 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1553 lsq
.findResponse(head_inst
.inst
))
1555 head_inst_might_commit
= true;
1562 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1563 (num_issued
!= 0 ? " (issued some insts)" : ""),
1564 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1565 (can_issue_next
? " (can issued next inst)" : ""),
1566 (head_inst_might_commit
? "(head inst might commit)" : ""),
1567 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1568 (interrupted
? " (interrupted)" : ""));
1571 num_issued
!= 0 || /* Issued some insts this cycle */
1572 !becoming_stalled
|| /* Some FU pipelines can still move */
1573 can_issue_next
|| /* Can still issue a new inst */
1574 head_inst_might_commit
|| /* Could possible commit the next inst */
1575 lsq
.needsToTick() || /* Must step the dcache port */
1576 interrupted
; /* There are pending interrupts */
1578 if (!need_to_tick
) {
1579 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1580 " advanceable FUs\n");
1583 /* Wake up if we need to tick again */
1585 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1587 /* Note activity of following buffer */
1588 if (!branch
.isBubble())
1589 cpu
.activityRecorder
->activity();
1591 /* Make sure the input (if any left) is pushed */
1592 if (!inp
.outputWire
->isBubble())
1593 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1597 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1599 ThreadID tid
= interruptPriority
;
1600 /* Evaluate interrupts in round-robin based upon service */
1602 /* Has an interrupt been signalled? This may not be acted on
1603 * straighaway so this is different from took_interrupt */
1604 bool thread_interrupted
= false;
1606 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1607 /* This is here because it seems that after drainResume the
1608 * interrupt controller isn't always set */
1609 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1611 interrupted
= interrupted
|| thread_interrupted
;
1613 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1615 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1616 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1617 /* Act on interrupts */
1618 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1619 if (takeInterrupt(tid
, branch
)) {
1620 interruptPriority
= tid
;
1624 tid
= (tid
+ 1) % cpu
.numThreads
;
1626 } while (tid
!= interruptPriority
);
1628 return InvalidThreadID
;
1632 Execute::hasInterrupt(ThreadID thread_id
)
1634 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1635 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1636 isInterrupted(thread_id
);
1643 Execute::minorTrace() const
1645 std::ostringstream insts
;
1646 std::ostringstream stalled
;
1648 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1650 inputBuffer
[0].minorTrace();
1651 scoreboard
[0].minorTrace();
1653 /* Report functional unit stalling in one string */
1655 while (i
< numFuncUnits
)
1657 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1659 if (i
!= numFuncUnits
)
1663 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1664 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1665 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1666 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1668 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1669 std::mem_fun(&FUPipeline::minorTrace
));
1671 executeInfo
[0].inFlightInsts
->minorTrace();
1672 executeInfo
[0].inFUMemInsts
->minorTrace();
1676 Execute::getCommittingThread()
1678 std::vector
<ThreadID
> priority_list
;
1680 switch (cpu
.threadPolicy
) {
1681 case Enums::SingleThreaded
:
1683 case Enums::RoundRobin
:
1684 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1687 priority_list
= cpu
.randomPriority();
1690 panic("Invalid thread policy");
1693 for (auto tid
: priority_list
) {
1694 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1695 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty();
1696 if (can_commit_insts
) {
1697 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1698 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1700 can_commit_insts
= can_commit_insts
&&
1701 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1704 bool can_transfer_mem_inst
= false;
1705 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1706 const MinorDynInstPtr head_mem_ref_inst
=
1707 ex_info
.inFUMemInsts
->front().inst
;
1708 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1709 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1710 can_transfer_mem_inst
=
1711 !fu_inst
->isBubble() &&
1712 fu_inst
->id
.threadId
== tid
&&
1714 fu_inst
->canEarlyIssue
&&
1715 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1718 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1719 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1720 inst
->fuIndex
!= noCostFUIndex
)
1722 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1723 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1724 fu_inst
.inst
->id
== inst
->id
;
1727 can_commit_insts
= can_commit_insts
&&
1728 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1733 if (can_commit_insts
) {
1734 commitPriority
= tid
;
1739 return InvalidThreadID
;
1743 Execute::getIssuingThread()
1745 std::vector
<ThreadID
> priority_list
;
1747 switch (cpu
.threadPolicy
) {
1748 case Enums::SingleThreaded
:
1750 case Enums::RoundRobin
:
1751 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1754 priority_list
= cpu
.randomPriority();
1757 panic("Invalid thread scheduling policy.");
1760 for (auto tid
: priority_list
) {
1761 if (getInput(tid
)) {
1762 issuePriority
= tid
;
1767 return InvalidThreadID
;
1771 Execute::drainResume()
1773 DPRINTF(Drain
, "MinorExecute drainResume\n");
1775 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1776 setDrainState(tid
, NotDraining
);
1779 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1782 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1786 case Execute::NotDraining
:
1787 os
<< "NotDraining";
1789 case Execute::DrainCurrentInst
:
1790 os
<< "DrainCurrentInst";
1792 case Execute::DrainHaltFetch
:
1793 os
<< "DrainHaltFetch";
1795 case Execute::DrainAllInsts
:
1796 os
<< "DrainAllInsts";
1799 os
<< "Drain-" << static_cast<int>(state
);
1807 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1809 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1810 executeInfo
[thread_id
].drainState
= state
;
1816 DPRINTF(Drain
, "MinorExecute drain\n");
1818 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1819 if (executeInfo
[tid
].drainState
== NotDraining
) {
1820 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1822 /* Go to DrainCurrentInst if we're between microops
1823 * or waiting on an unbufferable memory operation.
1824 * Otherwise we can go straight to DrainHaltFetch
1826 if (isInbetweenInsts(tid
))
1827 setDrainState(tid
, DrainHaltFetch
);
1829 setDrainState(tid
, DrainCurrentInst
);
1832 return (isDrained() ? 0 : 1);
1836 Execute::isDrained()
1838 if (!lsq
.isDrained())
1841 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1842 if (!inputBuffer
[tid
].empty() ||
1843 !executeInfo
[tid
].inFlightInsts
->empty()) {
1854 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1855 delete funcUnits
[i
];
1857 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1858 delete executeInfo
[tid
].inFlightInsts
;
1862 Execute::instIsRightStream(MinorDynInstPtr inst
)
1864 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1868 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1872 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1873 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1878 MinorCPU::MinorCPUPort
&
1879 Execute::getDcachePort()
1881 return lsq
.getDcachePort();