2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "arch/locked_mem.hh"
41 #include "arch/registers.hh"
42 #include "arch/utility.hh"
43 #include "cpu/minor/cpu.hh"
44 #include "cpu/minor/exec_context.hh"
45 #include "cpu/minor/execute.hh"
46 #include "cpu/minor/fetch1.hh"
47 #include "cpu/minor/lsq.hh"
48 #include "cpu/op_class.hh"
49 #include "debug/Activity.hh"
50 #include "debug/Branch.hh"
51 #include "debug/Drain.hh"
52 #include "debug/MinorExecute.hh"
53 #include "debug/MinorInterrupt.hh"
54 #include "debug/MinorMem.hh"
55 #include "debug/MinorTrace.hh"
56 #include "debug/PCEvent.hh"
61 Execute::Execute(const std::string
&name_
,
63 MinorCPUParams
¶ms
,
64 Latch
<ForwardInstData
>::Output inp_
,
65 Latch
<BranchData
>::Input out_
) :
70 issueLimit(params
.executeIssueLimit
),
71 memoryIssueLimit(params
.executeMemoryIssueLimit
),
72 commitLimit(params
.executeCommitLimit
),
73 memoryCommitLimit(params
.executeMemoryCommitLimit
),
74 processMoreThanOneInput(params
.executeCycleInput
),
75 fuDescriptions(*params
.executeFuncUnits
),
76 numFuncUnits(fuDescriptions
.funcUnits
.size()),
77 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
78 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
79 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
80 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
81 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
83 params
.executeMaxAccessesInMemory
,
84 params
.executeMemoryWidth
,
85 params
.executeLSQRequestsQueueSize
,
86 params
.executeLSQTransfersQueueSize
,
87 params
.executeLSQStoreBufferSize
,
88 params
.executeLSQMaxStoreBufferStoresPerCycle
),
89 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
94 if (commitLimit
< 1) {
95 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
100 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
104 if (memoryIssueLimit
< 1) {
105 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
109 if (memoryCommitLimit
> commitLimit
) {
110 fatal("%s: executeMemoryCommitLimit (%d) must be <="
111 " executeCommitLimit (%d)\n",
112 name_
, memoryCommitLimit
, commitLimit
);
115 if (params
.executeInputBufferSize
< 1) {
116 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
117 params
.executeInputBufferSize
);
120 if (params
.executeInputBufferSize
< 1) {
121 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
122 params
.executeInputBufferSize
);
125 /* This should be large enough to count all the in-FU instructions
126 * which need to be accounted for in the inFlightInsts
128 unsigned int total_slots
= 0;
130 /* Make FUPipelines for each MinorFU */
131 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
132 std::ostringstream fu_name
;
133 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
135 /* Note the total number of instruction slots (for sizing
136 * the inFlightInst queue) and the maximum latency of any FU
137 * (for sizing the activity recorder) */
138 total_slots
+= fu_description
->opLat
;
140 fu_name
<< name_
<< ".fu." << i
;
142 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
144 funcUnits
.push_back(fu
);
147 /** Check that there is a functional unit for all operation classes */
148 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
149 bool found_fu
= false;
150 unsigned int fu_index
= 0;
152 while (fu_index
< numFuncUnits
&& !found_fu
)
154 if (funcUnits
[fu_index
]->provides(
155 static_cast<OpClass
>(op_class
)))
163 warn("No functional unit for OpClass %s\n",
164 Enums::OpClassStrings
[op_class
]);
168 /* Per-thread structures */
169 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
170 std::string tid_str
= std::to_string(tid
);
173 inputBuffer
.push_back(
174 InputBuffer
<ForwardInstData
>(
175 name_
+ ".inputBuffer" + tid_str
, "insts",
176 params
.executeInputBufferSize
));
179 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
181 /* In-flight instruction records */
182 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
183 ReportTraitsAdaptor
<QueuedInst
> >(
184 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
186 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
187 ReportTraitsAdaptor
<QueuedInst
> >(
188 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
192 const ForwardInstData
*
193 Execute::getInput(ThreadID tid
)
195 /* Get a line from the inputBuffer to work with */
196 if (!inputBuffer
[tid
].empty()) {
197 const ForwardInstData
&head
= inputBuffer
[tid
].front();
199 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
206 Execute::popInput(ThreadID tid
)
208 if (!inputBuffer
[tid
].empty())
209 inputBuffer
[tid
].pop();
211 executeInfo
[tid
].inputIndex
= 0;
215 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
217 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
218 const TheISA::PCState
&pc_before
= inst
->pc
;
219 TheISA::PCState target
= thread
->pcState();
221 /* Force a branch for SerializeAfter instructions at the end of micro-op
222 * sequence when we're not suspended */
223 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
225 inst
->isLastOpInInst() &&
226 (inst
->staticInst
->isSerializeAfter() ||
227 inst
->staticInst
->isIprAccess());
229 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
230 pc_before
, target
, (force_branch
? " (forcing)" : ""));
232 /* Will we change the PC to something other than the next instruction? */
233 bool must_branch
= pc_before
!= target
||
237 /* The reason for the branch data we're about to generate, set below */
238 BranchData::Reason reason
= BranchData::NoBranch
;
240 if (fault
== NoFault
)
242 TheISA::advancePC(target
, inst
->staticInst
);
243 thread
->pcState(target
);
245 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
249 if (inst
->predictedTaken
&& !force_branch
) {
250 /* Predicted to branch */
252 /* No branch was taken, change stream to get us back to the
253 * intended PC value */
254 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
255 " none happened inst: %s\n",
256 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
258 reason
= BranchData::BadlyPredictedBranch
;
259 } else if (inst
->predictedTarget
== target
) {
260 /* Branch prediction got the right target, kill the branch and
262 * Note that this information to the branch predictor might get
263 * overwritten by a "real" branch during this cycle */
264 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
266 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
268 reason
= BranchData::CorrectlyPredictedBranch
;
270 /* Branch prediction got the wrong target */
271 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
272 " but got the wrong target (actual: 0x%x) inst: %s\n",
273 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
274 target
.instAddr(), *inst
);
276 reason
= BranchData::BadlyPredictedBranchTarget
;
278 } else if (must_branch
) {
279 /* Unpredicted branch */
280 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
281 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
283 reason
= BranchData::UnpredictedBranch
;
285 /* No branch at all */
286 reason
= BranchData::NoBranch
;
289 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
293 Execute::updateBranchData(
295 BranchData::Reason reason
,
296 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
299 if (reason
!= BranchData::NoBranch
) {
300 /* Bump up the stream sequence number on a real branch*/
301 if (BranchData::isStreamChange(reason
))
302 executeInfo
[tid
].streamSeqNum
++;
304 /* Branches (even mis-predictions) don't change the predictionSeqNum,
305 * just the streamSeqNum */
306 branch
= BranchData(reason
, tid
,
307 executeInfo
[tid
].streamSeqNum
,
308 /* Maintaining predictionSeqNum if there's no inst is just a
309 * courtesy and looks better on minorview */
310 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
311 : inst
->id
.predictionSeqNum
),
314 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
319 Execute::handleMemResponse(MinorDynInstPtr inst
,
320 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
322 ThreadID thread_id
= inst
->id
.threadId
;
323 ThreadContext
*thread
= cpu
.getContext(thread_id
);
325 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
327 PacketPtr packet
= response
->packet
;
329 bool is_load
= inst
->staticInst
->isLoad();
330 bool is_store
= inst
->staticInst
->isStore();
331 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
333 /* If true, the trace's predicate value will be taken from the exec
334 * context predicate, otherwise, it will be set to false */
335 bool use_context_predicate
= true;
337 if (response
->fault
!= NoFault
) {
338 /* Invoke memory faults. */
339 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
340 response
->fault
->name());
342 if (inst
->staticInst
->isPrefetch()) {
343 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
344 response
->fault
->name());
346 /* Don't assign to fault */
348 /* Take the fault raised during the TLB/memory access */
349 fault
= response
->fault
;
351 fault
->invoke(thread
, inst
->staticInst
);
353 } else if (!packet
) {
354 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
356 use_context_predicate
= false;
357 } else if (packet
->isError()) {
358 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
361 fatal("Received error response packet for inst: %s\n", *inst
);
362 } else if (is_store
|| is_load
|| is_prefetch
) {
365 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
366 *inst
, packet
->getAddr(), packet
->getSize());
368 if (is_load
&& packet
->getSize() > 0) {
369 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
370 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
373 /* Complete the memory access instruction */
374 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
377 if (fault
!= NoFault
) {
378 /* Invoke fault created by instruction completion */
379 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
381 fault
->invoke(thread
, inst
->staticInst
);
383 /* Stores need to be pushed into the store buffer to finish
385 if (response
->needsToBeSentToStoreBuffer())
386 lsq
.sendStoreToStoreBuffer(response
);
389 fatal("There should only ever be reads, "
390 "writes or faults at this point\n");
393 lsq
.popResponse(response
);
395 if (inst
->traceData
) {
396 inst
->traceData
->setPredicate((use_context_predicate
?
397 context
.readPredicate() : false));
400 doInstCommitAccounting(inst
);
402 /* Generate output to account for branches */
403 tryToBranch(inst
, fault
, branch
);
407 Execute::isInterrupted(ThreadID thread_id
) const
409 return cpu
.checkInterrupts(cpu
.getContext(thread_id
));
413 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
415 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
416 cpu
.getContext(thread_id
)->pcState());
418 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt
419 (cpu
.getContext(thread_id
));
421 if (interrupt
!= NoFault
) {
422 /* The interrupt *must* set pcState */
423 cpu
.getInterruptController(thread_id
)->updateIntrInfo
424 (cpu
.getContext(thread_id
));
425 interrupt
->invoke(cpu
.getContext(thread_id
));
427 assert(!lsq
.accessesInFlight());
429 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
430 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
432 /* Assume that an interrupt *must* cause a branch. Assert this? */
434 updateBranchData(thread_id
, BranchData::Interrupt
,
435 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
439 return interrupt
!= NoFault
;
443 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
444 bool &passed_predicate
, Fault
&fault
)
448 /* Set to true if the mem op. is issued and sent to the mem system */
449 passed_predicate
= false;
451 if (!lsq
.canRequest()) {
452 /* Not acting on instruction yet as the memory
456 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
457 TheISA::PCState old_pc
= thread
->pcState();
459 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
462 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
464 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
467 if (init_fault
!= NoFault
) {
468 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
469 " initiateAcc: %s\n", *inst
, init_fault
->name());
472 /* Only set this if the instruction passed its
474 passed_predicate
= context
.readPredicate();
476 /* Set predicate in tracing */
478 inst
->traceData
->setPredicate(passed_predicate
);
480 /* If the instruction didn't pass its predicate (and so will not
481 * progress from here) Try to branch to correct and branch
483 if (!passed_predicate
) {
484 /* Leave it up to commit to handle the fault */
485 lsq
.pushFailedRequest(inst
);
489 /* Restore thread PC */
490 thread
->pcState(old_pc
);
497 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
499 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
501 unsigned int ret
= index
+ 1;
503 if (ret
== cycle_size
)
509 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
511 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
516 ret
= cycle_size
- 1;
522 Execute::issue(ThreadID thread_id
)
524 const ForwardInstData
*insts_in
= getInput(thread_id
);
525 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
527 /* Early termination if we have no instructions */
531 /* Start from the first FU */
532 unsigned int fu_index
= 0;
534 /* Remains true while instructions are still being issued. If any
535 * instruction fails to issue, this is set to false and we exit issue.
536 * This strictly enforces in-order issue. For other issue behaviours,
537 * a more complicated test in the outer while loop below is needed. */
540 /* Number of insts issues this cycle to check for issueLimit */
541 unsigned num_insts_issued
= 0;
543 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
544 unsigned num_mem_insts_issued
= 0;
546 /* Number of instructions discarded this cycle in order to enforce a
547 * discardLimit. @todo, add that parameter? */
548 unsigned num_insts_discarded
= 0;
551 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
552 Fault fault
= inst
->fault
;
553 bool discarded
= false;
554 bool issued_mem_ref
= false;
556 if (inst
->isBubble()) {
559 } else if (cpu
.getContext(thread_id
)->status() ==
560 ThreadContext::Suspended
)
562 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
567 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
568 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
569 " state was unexpected, expected: %d\n",
570 *inst
, thread
.streamSeqNum
);
574 /* Try and issue an instruction into an FU, assume we didn't and
575 * fix that in the loop */
578 /* Try FU from 0 each instruction */
581 /* Try and issue a single instruction stepping through the
584 FUPipeline
*fu
= funcUnits
[fu_index
];
586 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
589 /* Does the examined fu have the OpClass-related capability
590 * needed to execute this instruction? Faults can always
591 * issue to any FU but probably should just 'live' in the
592 * inFlightInsts queue rather than having an FU. */
593 bool fu_is_capable
= (!inst
->isFault() ?
594 fu
->provides(inst
->staticInst
->opClass()) : true);
596 if (inst
->isNoCostInst()) {
597 /* Issue free insts. to a fake numbered FU */
598 fu_index
= noCostFUIndex
;
600 /* And start the countdown on activity to allow
601 * this instruction to get to the end of its FU */
602 cpu
.activityRecorder
->activity();
604 /* Mark the destinations for this instruction as
606 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
607 Cycles(0), cpu
.getContext(thread_id
), false);
609 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
610 inst
->fuIndex
= noCostFUIndex
;
611 inst
->extraCommitDelay
= Cycles(0);
612 inst
->extraCommitDelayExpr
= NULL
;
614 /* Push the instruction onto the inFlight queue so
615 * it can be committed in order */
616 QueuedInst
fu_inst(inst
);
617 thread
.inFlightInsts
->push(fu_inst
);
621 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
623 if (!fu_is_capable
) {
624 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
625 " capable\n", fu_index
);
627 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
628 " already busy\n", fu_index
);
630 } else if (fu
->stalled
) {
631 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
634 } else if (!fu
->canInsert()) {
635 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
636 " for another: %d cycles\n",
637 *inst
, fu
->cyclesBeforeInsert());
639 MinorFUTiming
*timing
= (!inst
->isFault() ?
640 fu
->findTiming(inst
->staticInst
) : NULL
);
642 const std::vector
<Cycles
> *src_latencies
=
643 (timing
? &(timing
->srcRegsRelativeLats
)
646 const std::vector
<bool> *cant_forward_from_fu_indices
=
647 &(fu
->cantForwardFromFUIndices
);
649 if (timing
&& timing
->suppress
) {
650 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
651 " decoding is suppressing it\n",
653 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
654 src_latencies
, cant_forward_from_fu_indices
,
655 cpu
.curCycle(), cpu
.getContext(thread_id
)))
657 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
660 /* Can insert the instruction into this FU */
661 DPRINTF(MinorExecute
, "Issuing inst: %s"
662 " into FU %d\n", *inst
,
665 Cycles extra_dest_retire_lat
= Cycles(0);
666 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
667 Cycles extra_assumed_lat
= Cycles(0);
669 /* Add the extraCommitDelay and extraAssumeLat to
670 * the FU pipeline timings */
672 extra_dest_retire_lat
=
673 timing
->extraCommitLat
;
674 extra_dest_retire_lat_expr
=
675 timing
->extraCommitLatExpr
;
677 timing
->extraAssumedLat
;
680 issued_mem_ref
= inst
->isMemRef();
682 QueuedInst
fu_inst(inst
);
684 /* Decorate the inst with FU details */
685 inst
->fuIndex
= fu_index
;
686 inst
->extraCommitDelay
= extra_dest_retire_lat
;
687 inst
->extraCommitDelayExpr
=
688 extra_dest_retire_lat_expr
;
690 if (issued_mem_ref
) {
691 /* Remember which instruction this memory op
692 * depends on so that initiateAcc can be called
694 if (allowEarlyMemIssue
) {
695 inst
->instToWaitFor
=
696 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
697 cpu
.getContext(thread_id
));
699 if (lsq
.getLastMemBarrier(thread_id
) >
702 DPRINTF(MinorExecute
, "A barrier will"
703 " cause a delay in mem ref issue of"
704 " inst: %s until after inst"
705 " %d(exec)\n", *inst
,
706 lsq
.getLastMemBarrier(thread_id
));
708 inst
->instToWaitFor
=
709 lsq
.getLastMemBarrier(thread_id
);
711 DPRINTF(MinorExecute
, "Memory ref inst:"
712 " %s must wait for inst %d(exec)"
714 *inst
, inst
->instToWaitFor
);
717 inst
->canEarlyIssue
= true;
719 /* Also queue this instruction in the memory ref
720 * queue to ensure in-order issue to the LSQ */
721 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
723 thread
.inFUMemInsts
->push(fu_inst
);
728 /* And start the countdown on activity to allow
729 * this instruction to get to the end of its FU */
730 cpu
.activityRecorder
->activity();
732 /* Mark the destinations for this instruction as
734 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
735 fu
->description
.opLat
+
736 extra_dest_retire_lat
+
738 cpu
.getContext(thread_id
),
739 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
741 /* Push the instruction onto the inFlight queue so
742 * it can be committed in order */
743 thread
.inFlightInsts
->push(fu_inst
);
750 } while (fu_index
!= numFuncUnits
&& !issued
);
753 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
757 /* Generate MinorTrace's MinorInst lines. Do this at commit
758 * to allow better instruction annotation? */
759 if (DTRACE(MinorTrace
) && !inst
->isBubble())
760 inst
->minorTraceInst(*this);
762 /* Mark up barriers in the LSQ */
763 if (!discarded
&& inst
->isInst() &&
764 inst
->staticInst
->isMemBarrier())
766 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
767 lsq
.issuedMemBarrierInst(inst
);
770 if (inst
->traceData
&& setTraceTimeOnIssue
) {
771 inst
->traceData
->setWhen(curTick());
775 num_mem_insts_issued
++;
778 num_insts_discarded
++;
779 } else if (!inst
->isBubble()) {
782 if (num_insts_issued
== issueLimit
)
783 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
787 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
791 /* Got to the end of a line */
792 if (thread
.inputIndex
== insts_in
->width()) {
794 /* Set insts_in to null to force us to leave the surrounding
798 if (processMoreThanOneInput
) {
799 DPRINTF(MinorExecute
, "Wrapping\n");
800 insts_in
= getInput(thread_id
);
803 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
804 /* We still have instructions */
805 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
806 issued
&& /* We've not yet failed to issue an instruction */
807 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
808 num_mem_insts_issued
!= memoryIssueLimit
);
810 return num_insts_issued
;
814 Execute::tryPCEvents(ThreadID thread_id
)
816 ThreadContext
*thread
= cpu
.getContext(thread_id
);
817 unsigned int num_pc_event_checks
= 0;
819 /* Handle PC events on instructions */
822 oldPC
= thread
->instAddr();
823 cpu
.system
->pcEventQueue
.service(thread
);
824 num_pc_event_checks
++;
825 } while (oldPC
!= thread
->instAddr());
827 if (num_pc_event_checks
> 1) {
828 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
832 return num_pc_event_checks
> 1;
836 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
838 assert(!inst
->isFault());
840 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
842 /* Increment the many and various inst and op counts in the
843 * thread and system */
844 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
848 cpu
.stats
.numInsts
++;
849 cpu
.system
->totalNumInsts
++;
851 /* Act on events related to instruction counts */
852 cpu
.comInstEventQueue
[inst
->id
.threadId
]->serviceEvents(thread
->numInst
);
853 cpu
.system
->instEventQueue
.serviceEvents(cpu
.system
->totalNumInsts
);
858 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
859 [inst
->staticInst
->opClass()]++;
861 /* Set the CP SeqNum to the numOps commit number */
863 inst
->traceData
->setCPSeq(thread
->numOp
);
865 cpu
.probeInstCommit(inst
->staticInst
);
869 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
870 BranchData
&branch
, Fault
&fault
, bool &committed
,
871 bool &completed_mem_issue
)
873 ThreadID thread_id
= inst
->id
.threadId
;
874 ThreadContext
*thread
= cpu
.getContext(thread_id
);
876 bool completed_inst
= true;
879 /* Is the thread for this instruction suspended? In that case, just
880 * stall as long as there are no pending interrupts */
881 if (thread
->status() == ThreadContext::Suspended
&&
882 !isInterrupted(thread_id
))
884 panic("We should never hit the case where we try to commit from a "
885 "suspended thread as the streamSeqNum should not match");
886 } else if (inst
->isFault()) {
887 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
889 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
890 inst
->fault
->name());
893 inst
->fault
->invoke(thread
, NULL
);
895 tryToBranch(inst
, fault
, branch
);
896 } else if (inst
->staticInst
->isMemRef()) {
897 /* Memory accesses are executed in two parts:
898 * executeMemRefInst -- calculates the EA and issues the access
899 * to memory. This is done here.
900 * handleMemResponse -- handles the response packet, done by
903 * While the memory access is in its FU, the EA is being
904 * calculated. At the end of the FU, when it is ready to
905 * 'commit' (in this function), the access is presented to the
906 * memory queues. When a response comes back from memory,
907 * Execute::commit will commit it.
909 bool predicate_passed
= false;
910 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
911 predicate_passed
, fault
);
913 if (completed_mem_inst
&& fault
!= NoFault
) {
914 if (early_memory_issue
) {
915 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
917 /* Don't execute the fault, just stall the instruction
918 * until it gets to the head of inFlightInsts */
919 inst
->canEarlyIssue
= false;
920 /* Not completed as we'll come here again to pick up
921 * the fault when we get to the end of the FU */
922 completed_inst
= false;
924 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
926 fault
->invoke(thread
, NULL
);
928 tryToBranch(inst
, fault
, branch
);
929 completed_inst
= true;
932 completed_inst
= completed_mem_inst
;
934 completed_mem_issue
= completed_inst
;
935 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
936 !lsq
.canPushIntoStoreBuffer())
938 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
939 " there isn't space in the store buffer\n", *inst
);
941 completed_inst
= false;
942 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
943 && !branch
.isBubble()){
944 /* This instruction can suspend, need to be able to communicate
945 * backwards, so no other branches may evaluate this cycle*/
946 completed_inst
= false;
948 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
950 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
952 fault
= inst
->staticInst
->execute(&context
,
955 /* Set the predicate for tracing and dump */
957 inst
->traceData
->setPredicate(context
.readPredicate());
961 if (fault
!= NoFault
) {
962 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
963 *inst
, fault
->name());
964 fault
->invoke(thread
, inst
->staticInst
);
967 doInstCommitAccounting(inst
);
968 tryToBranch(inst
, fault
, branch
);
971 if (completed_inst
) {
972 /* Keep a copy of this instruction's predictionSeqNum just in case
973 * we need to issue a branch without an instruction (such as an
975 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
977 /* Check to see if this instruction suspended the current thread. */
978 if (!inst
->isFault() &&
979 thread
->status() == ThreadContext::Suspended
&&
980 branch
.isBubble() && /* It didn't branch too */
981 !isInterrupted(thread_id
)) /* Don't suspend if we have
984 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
986 assert(resume_pc
.microPC() == 0);
988 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
989 " inst: %s\n", thread_id
, *inst
);
991 cpu
.stats
.numFetchSuspends
++;
993 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
998 return completed_inst
;
1002 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1005 Fault fault
= NoFault
;
1006 Cycles now
= cpu
.curCycle();
1007 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1010 * Try and execute as many instructions from the end of FU pipelines as
1011 * possible. This *doesn't* include actually advancing the pipelines.
1013 * We do this by looping on the front of the inFlightInsts queue for as
1014 * long as we can find the desired instruction at the end of the
1015 * functional unit it was issued to without seeing a branch or a fault.
1016 * In this function, these terms are used:
1017 * complete -- The instruction has finished its passage through
1018 * its functional unit and its fate has been decided
1019 * (committed, discarded, issued to the memory system)
1020 * commit -- The instruction is complete(d), not discarded and has
1021 * its effects applied to the CPU state
1022 * discard(ed) -- The instruction is complete but not committed
1023 * as its streamSeqNum disagrees with the current
1024 * Execute::streamSeqNum
1026 * Commits are also possible from two other places:
1028 * 1) Responses returning from the LSQ
1029 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1030 * than their position in the inFlightInsts queue, but after all
1031 * their dependencies are resolved.
1034 /* Has an instruction been completed? Once this becomes false, we stop
1035 * trying to complete instructions. */
1036 bool completed_inst
= true;
1038 /* Number of insts committed this cycle to check against commitLimit */
1039 unsigned int num_insts_committed
= 0;
1041 /* Number of memory access instructions committed to check against
1043 unsigned int num_mem_refs_committed
= 0;
1045 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1046 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1047 *(ex_info
.inFlightInsts
->front().inst
),
1048 ex_info
.lastCommitWasEndOfMacroop
);
1051 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1052 !branch
.isStreamChange() && /* No real branch */
1053 fault
== NoFault
&& /* No faults */
1054 completed_inst
&& /* Still finding instructions to execute */
1055 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1058 if (only_commit_microops
) {
1059 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1061 *(ex_info
.inFlightInsts
->front().inst
));
1064 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1066 InstSeqNum head_exec_seq_num
=
1067 head_inflight_inst
->inst
->id
.execSeqNum
;
1069 /* The instruction we actually process if completed_inst
1070 * remains true to the end of the loop body.
1071 * Start by considering the the head of the in flight insts queue */
1072 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1074 bool committed_inst
= false;
1075 bool discard_inst
= false;
1076 bool completed_mem_ref
= false;
1077 bool issued_mem_ref
= false;
1078 bool early_memory_issue
= false;
1080 /* Must set this again to go around the loop */
1081 completed_inst
= false;
1083 /* If we're just completing a macroop before an interrupt or drain,
1084 * can we stil commit another microop (rather than a memory response)
1085 * without crosing into the next full instruction? */
1086 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1087 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1089 /* Can we find a mem response for this inst */
1090 LSQ::LSQRequestPtr mem_response
=
1091 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1093 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1096 /* Test for PC events after every instruction */
1097 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1098 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1100 /* Branch as there was a change in PC */
1101 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1102 MinorDynInst::bubble(), thread
->pcState(), branch
);
1103 } else if (mem_response
&&
1104 num_mem_refs_committed
< memoryCommitLimit
)
1106 /* Try to commit from the memory responses next */
1107 discard_inst
= inst
->id
.streamSeqNum
!=
1108 ex_info
.streamSeqNum
|| discard
;
1110 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1113 /* Complete or discard the response */
1115 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1116 " stream state was unexpected, expected: %d\n",
1117 *inst
, ex_info
.streamSeqNum
);
1119 lsq
.popResponse(mem_response
);
1121 handleMemResponse(inst
, mem_response
, branch
, fault
);
1122 committed_inst
= true;
1125 completed_mem_ref
= true;
1126 completed_inst
= true;
1127 } else if (can_commit_insts
) {
1128 /* If true, this instruction will, subject to timing tweaks,
1129 * be considered for completion. try_to_commit flattens
1130 * the `if' tree a bit and allows other tests for inst
1131 * commit to be inserted here. */
1132 bool try_to_commit
= false;
1134 /* Try and issue memory ops early if they:
1135 * - Can push a request into the LSQ
1136 * - Have reached the end of their FUs
1137 * - Have had all their dependencies satisfied
1138 * - Are from the right stream
1140 * For any other case, leave it to the normal instruction
1141 * issue below to handle them.
1143 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1144 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1146 const MinorDynInstPtr head_mem_ref_inst
=
1147 ex_info
.inFUMemInsts
->front().inst
;
1148 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1149 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1151 /* Use this, possibly out of order, inst as the one
1152 * to 'commit'/send to the LSQ */
1153 if (!fu_inst
->isBubble() &&
1155 fu_inst
->canEarlyIssue
&&
1156 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1157 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1159 DPRINTF(MinorExecute
, "Issuing mem ref early"
1160 " inst: %s instToWaitFor: %d\n",
1161 *(fu_inst
), fu_inst
->instToWaitFor
);
1164 try_to_commit
= true;
1165 early_memory_issue
= true;
1166 completed_inst
= true;
1170 /* Try and commit FU-less insts */
1171 if (!completed_inst
&& inst
->isNoCostInst()) {
1172 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1174 try_to_commit
= true;
1175 completed_inst
= true;
1178 /* Try to issue from the ends of FUs and the inFlightInsts
1180 if (!completed_inst
&& !inst
->inLSQ
) {
1181 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1183 /* Try to commit from a functional unit */
1184 /* Is the head inst of the expected inst's FU actually the
1186 QueuedInst
&fu_inst
=
1187 funcUnits
[inst
->fuIndex
]->front();
1188 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1190 if (fu_inst
.inst
->isBubble()) {
1191 /* No instruction ready */
1192 completed_inst
= false;
1193 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1194 /* Past instruction: we must have already executed it
1195 * in the same cycle and so the head inst isn't
1196 * actually at the end of its pipeline
1197 * Future instruction: handled above and only for
1198 * mem refs on their way to the LSQ */
1199 } else if (fu_inst
.inst
->id
== inst
->id
) {
1200 /* All instructions can be committed if they have the
1201 * right execSeqNum and there are no in-flight
1202 * mem insts before us */
1203 try_to_commit
= true;
1204 completed_inst
= true;
1208 if (try_to_commit
) {
1209 discard_inst
= inst
->id
.streamSeqNum
!=
1210 ex_info
.streamSeqNum
|| discard
;
1212 /* Is this instruction discardable as its streamSeqNum
1214 if (!discard_inst
) {
1215 /* Try to commit or discard a non-memory instruction.
1216 * Memory ops are actually 'committed' from this FUs
1217 * and 'issued' into the memory system so we need to
1218 * account for them later (commit_was_mem_issue gets
1220 if (inst
->extraCommitDelayExpr
) {
1221 DPRINTF(MinorExecute
, "Evaluating expression for"
1222 " extra commit delay inst: %s\n", *inst
);
1224 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1226 TimingExprEvalContext
context(inst
->staticInst
,
1229 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1232 DPRINTF(MinorExecute
, "Extra commit delay expr"
1233 " result: %d\n", extra_delay
);
1235 if (extra_delay
< 128) {
1236 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1238 DPRINTF(MinorExecute
, "Extra commit delay was"
1239 " very long: %d\n", extra_delay
);
1241 inst
->extraCommitDelayExpr
= NULL
;
1244 /* Move the extraCommitDelay from the instruction
1245 * into the minimumCommitCycle */
1246 if (inst
->extraCommitDelay
!= Cycles(0)) {
1247 inst
->minimumCommitCycle
= cpu
.curCycle() +
1248 inst
->extraCommitDelay
;
1249 inst
->extraCommitDelay
= Cycles(0);
1252 /* @todo Think about making lastMemBarrier be
1253 * MAX_UINT_64 to avoid using 0 as a marker value */
1254 if (!inst
->isFault() && inst
->isMemRef() &&
1255 lsq
.getLastMemBarrier(thread_id
) <
1256 inst
->id
.execSeqNum
&&
1257 lsq
.getLastMemBarrier(thread_id
) != 0)
1259 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1260 " as there are incomplete barriers in flight\n",
1262 completed_inst
= false;
1263 } else if (inst
->minimumCommitCycle
> now
) {
1264 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1265 " as it wants to be stalled for %d more cycles\n",
1266 *inst
, inst
->minimumCommitCycle
- now
);
1267 completed_inst
= false;
1269 completed_inst
= commitInst(inst
,
1270 early_memory_issue
, branch
, fault
,
1271 committed_inst
, issued_mem_ref
);
1274 /* Discard instruction */
1275 completed_inst
= true;
1278 if (completed_inst
) {
1279 /* Allow the pipeline to advance. If the FU head
1280 * instruction wasn't the inFlightInsts head
1281 * but had already been committed, it would have
1282 * unstalled the pipeline before here */
1283 if (inst
->fuIndex
!= noCostFUIndex
) {
1284 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1285 funcUnits
[inst
->fuIndex
]->stalled
= false;
1290 DPRINTF(MinorExecute
, "No instructions to commit\n");
1291 completed_inst
= false;
1294 /* All discardable instructions must also be 'completed' by now */
1295 assert(!(discard_inst
&& !completed_inst
));
1297 /* Instruction committed but was discarded due to streamSeqNum
1300 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1301 " state was unexpected, expected: %d\n",
1302 *inst
, ex_info
.streamSeqNum
);
1304 if (fault
== NoFault
)
1305 cpu
.stats
.numDiscardedOps
++;
1308 /* Mark the mem inst as being in the LSQ */
1309 if (issued_mem_ref
) {
1314 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1315 * as they've *definitely* exited the FUs */
1316 if (completed_inst
&& inst
->isMemRef()) {
1317 /* The MemRef could have been discarded from the FU or the memory
1318 * queue, so just check an FU instruction */
1319 if (!ex_info
.inFUMemInsts
->empty() &&
1320 ex_info
.inFUMemInsts
->front().inst
== inst
)
1322 ex_info
.inFUMemInsts
->pop();
1326 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1327 /* Note that this includes discarded insts */
1328 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1330 /* Got to the end of a full instruction? */
1331 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1332 inst
->isLastOpInInst();
1334 /* lastPredictionSeqNum is kept as a convenience to prevent its
1335 * value from changing too much on the minorview display */
1336 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1338 /* Finished with the inst, remove it from the inst queue and
1339 * clear its dependencies */
1340 ex_info
.inFlightInsts
->pop();
1342 /* Complete barriers in the LSQ/move to store buffer */
1343 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1344 DPRINTF(MinorMem
, "Completing memory barrier"
1345 " inst: %s committed: %d\n", *inst
, committed_inst
);
1346 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1349 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1352 /* Handle per-cycle instruction counting */
1353 if (committed_inst
) {
1354 bool is_no_cost_inst
= inst
->isNoCostInst();
1356 /* Don't show no cost instructions as having taken a commit
1358 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1359 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1361 if (!is_no_cost_inst
)
1362 num_insts_committed
++;
1364 if (num_insts_committed
== commitLimit
)
1365 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1367 /* Re-set the time of the instruction if that's required for
1369 if (inst
->traceData
) {
1370 if (setTraceTimeOnCommit
)
1371 inst
->traceData
->setWhen(curTick());
1372 inst
->traceData
->dump();
1375 if (completed_mem_ref
)
1376 num_mem_refs_committed
++;
1378 if (num_mem_refs_committed
== memoryCommitLimit
)
1379 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1385 Execute::isInbetweenInsts(ThreadID thread_id
) const
1387 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1388 !lsq
.accessesInFlight();
1394 if (!inp
.outputWire
->isBubble())
1395 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1397 BranchData
&branch
= *out
.inputWire
;
1399 unsigned int num_issued
= 0;
1401 /* Do all the cycle-wise activities for dcachePort here to potentially
1402 * free up input spaces in the LSQ's requests queue */
1405 /* Check interrupts first. Will halt commit if interrupt found */
1406 bool interrupted
= false;
1407 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1409 if (interrupt_tid
!= InvalidThreadID
) {
1410 /* Signalling an interrupt this cycle, not issuing/committing from
1411 * any other threads */
1412 } else if (!branch
.isBubble()) {
1413 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1414 * without overwriting them */
1415 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1416 " branch to complete\n");
1418 ThreadID commit_tid
= getCommittingThread();
1420 if (commit_tid
!= InvalidThreadID
) {
1421 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1423 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1425 /* commit can set stalled flags observable to issue and so *must* be
1427 if (commit_info
.drainState
!= NotDraining
) {
1428 if (commit_info
.drainState
== DrainCurrentInst
) {
1429 /* Commit only micro-ops, don't kill anything else */
1430 commit(commit_tid
, true, false, branch
);
1432 if (isInbetweenInsts(commit_tid
))
1433 setDrainState(commit_tid
, DrainHaltFetch
);
1435 /* Discard any generated branch */
1436 branch
= BranchData::bubble();
1437 } else if (commit_info
.drainState
== DrainAllInsts
) {
1438 /* Kill all instructions */
1439 while (getInput(commit_tid
))
1440 popInput(commit_tid
);
1441 commit(commit_tid
, false, true, branch
);
1444 /* Commit micro-ops only if interrupted. Otherwise, commit
1445 * anything you like */
1446 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1448 bool only_commit_microops
= interrupted
&&
1449 hasInterrupt(commit_tid
);
1450 commit(commit_tid
, only_commit_microops
, false, branch
);
1453 /* Halt fetch, but don't do it until we have the current instruction in
1455 if (commit_info
.drainState
== DrainHaltFetch
) {
1456 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1457 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1459 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1460 setDrainState(commit_tid
, DrainAllInsts
);
1463 ThreadID issue_tid
= getIssuingThread();
1464 /* This will issue merrily even when interrupted in the sure and
1465 * certain knowledge that the interrupt with change the stream */
1466 if (issue_tid
!= InvalidThreadID
) {
1467 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1469 num_issued
= issue(issue_tid
);
1474 /* Run logic to step functional units + decide if we are active on the next
1476 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1477 bool can_issue_next
= false;
1479 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1480 /* Find the next issuable instruction for each thread and see if it can
1482 if (getInput(tid
)) {
1483 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1484 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1485 if (inst
->isFault()) {
1486 can_issue_next
= true;
1487 } else if (!inst
->isBubble()) {
1488 next_issuable_insts
.push_back(inst
);
1493 bool becoming_stalled
= true;
1495 /* Advance the pipelines and note whether they still need to be
1497 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1498 FUPipeline
*fu
= funcUnits
[i
];
1501 /* If we need to tick again, the pipeline will have been left or set
1502 * to be unstalled */
1503 if (fu
->occupancy
!=0 && !fu
->stalled
)
1504 becoming_stalled
= false;
1506 /* Could we possibly issue the next instruction from any thread?
1507 * This is quite an expensive test and is only used to determine
1508 * if the CPU should remain active, only run it if we aren't sure
1509 * we are active next cycle yet */
1510 for (auto inst
: next_issuable_insts
) {
1511 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1512 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1513 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1514 cpu
.getContext(inst
->id
.threadId
))) {
1515 can_issue_next
= true;
1521 bool head_inst_might_commit
= false;
1523 /* Could the head in flight insts be committed */
1524 for (auto const &info
: executeInfo
) {
1525 if (!info
.inFlightInsts
->empty()) {
1526 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1528 if (head_inst
.inst
->isNoCostInst()) {
1529 head_inst_might_commit
= true;
1531 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1533 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1534 lsq
.findResponse(head_inst
.inst
))
1536 head_inst_might_commit
= true;
1543 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1544 (num_issued
!= 0 ? " (issued some insts)" : ""),
1545 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1546 (can_issue_next
? " (can issued next inst)" : ""),
1547 (head_inst_might_commit
? "(head inst might commit)" : ""),
1548 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1549 (interrupted
? " (interrupted)" : ""));
1552 num_issued
!= 0 || /* Issued some insts this cycle */
1553 !becoming_stalled
|| /* Some FU pipelines can still move */
1554 can_issue_next
|| /* Can still issue a new inst */
1555 head_inst_might_commit
|| /* Could possible commit the next inst */
1556 lsq
.needsToTick() || /* Must step the dcache port */
1557 interrupted
; /* There are pending interrupts */
1559 if (!need_to_tick
) {
1560 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1561 " advanceable FUs\n");
1564 /* Wake up if we need to tick again */
1566 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1568 /* Note activity of following buffer */
1569 if (!branch
.isBubble())
1570 cpu
.activityRecorder
->activity();
1572 /* Make sure the input (if any left) is pushed */
1573 if (!inp
.outputWire
->isBubble())
1574 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1578 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1580 ThreadID tid
= interruptPriority
;
1581 /* Evaluate interrupts in round-robin based upon service */
1583 /* Has an interrupt been signalled? This may not be acted on
1584 * straighaway so this is different from took_interrupt */
1585 bool thread_interrupted
= false;
1587 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1588 /* This is here because it seems that after drainResume the
1589 * interrupt controller isn't always set */
1590 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1592 interrupted
= interrupted
|| thread_interrupted
;
1594 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1596 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1597 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1598 /* Act on interrupts */
1599 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1600 if (takeInterrupt(tid
, branch
)) {
1601 interruptPriority
= tid
;
1605 tid
= (tid
+ 1) % cpu
.numThreads
;
1607 } while (tid
!= interruptPriority
);
1609 return InvalidThreadID
;
1613 Execute::hasInterrupt(ThreadID thread_id
)
1615 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1616 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1617 isInterrupted(thread_id
);
1624 Execute::minorTrace() const
1626 std::ostringstream insts
;
1627 std::ostringstream stalled
;
1629 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1631 inputBuffer
[0].minorTrace();
1632 scoreboard
[0].minorTrace();
1634 /* Report functional unit stalling in one string */
1636 while (i
< numFuncUnits
)
1638 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1640 if (i
!= numFuncUnits
)
1644 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1645 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1646 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1647 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1649 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1650 std::mem_fun(&FUPipeline::minorTrace
));
1652 executeInfo
[0].inFlightInsts
->minorTrace();
1653 executeInfo
[0].inFUMemInsts
->minorTrace();
1657 Execute::getCommittingThread()
1659 std::vector
<ThreadID
> priority_list
;
1661 switch (cpu
.threadPolicy
) {
1662 case Enums::SingleThreaded
:
1664 case Enums::RoundRobin
:
1665 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1668 priority_list
= cpu
.randomPriority();
1671 panic("Invalid thread policy");
1674 for (auto tid
: priority_list
) {
1675 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1676 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty();
1677 if (can_commit_insts
) {
1678 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1679 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1681 can_commit_insts
= can_commit_insts
&&
1682 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1685 bool can_transfer_mem_inst
= false;
1686 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1687 const MinorDynInstPtr head_mem_ref_inst
=
1688 ex_info
.inFUMemInsts
->front().inst
;
1689 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1690 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1691 can_transfer_mem_inst
=
1692 !fu_inst
->isBubble() &&
1693 fu_inst
->id
.threadId
== tid
&&
1695 fu_inst
->canEarlyIssue
&&
1696 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1699 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1700 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1701 inst
->fuIndex
!= noCostFUIndex
)
1703 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1704 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1705 fu_inst
.inst
->id
== inst
->id
;
1708 can_commit_insts
= can_commit_insts
&&
1709 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1714 if (can_commit_insts
) {
1715 commitPriority
= tid
;
1720 return InvalidThreadID
;
1724 Execute::getIssuingThread()
1726 std::vector
<ThreadID
> priority_list
;
1728 switch (cpu
.threadPolicy
) {
1729 case Enums::SingleThreaded
:
1731 case Enums::RoundRobin
:
1732 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1735 priority_list
= cpu
.randomPriority();
1738 panic("Invalid thread scheduling policy.");
1741 for (auto tid
: priority_list
) {
1742 if (getInput(tid
)) {
1743 issuePriority
= tid
;
1748 return InvalidThreadID
;
1752 Execute::drainResume()
1754 DPRINTF(Drain
, "MinorExecute drainResume\n");
1756 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1757 setDrainState(tid
, NotDraining
);
1760 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1763 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1767 case Execute::NotDraining
:
1768 os
<< "NotDraining";
1770 case Execute::DrainCurrentInst
:
1771 os
<< "DrainCurrentInst";
1773 case Execute::DrainHaltFetch
:
1774 os
<< "DrainHaltFetch";
1776 case Execute::DrainAllInsts
:
1777 os
<< "DrainAllInsts";
1780 os
<< "Drain-" << static_cast<int>(state
);
1788 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1790 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1791 executeInfo
[thread_id
].drainState
= state
;
1797 DPRINTF(Drain
, "MinorExecute drain\n");
1799 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1800 if (executeInfo
[tid
].drainState
== NotDraining
) {
1801 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1803 /* Go to DrainCurrentInst if we're between microops
1804 * or waiting on an unbufferable memory operation.
1805 * Otherwise we can go straight to DrainHaltFetch
1807 if (isInbetweenInsts(tid
))
1808 setDrainState(tid
, DrainHaltFetch
);
1810 setDrainState(tid
, DrainCurrentInst
);
1813 return (isDrained() ? 0 : 1);
1817 Execute::isDrained()
1819 if (!lsq
.isDrained())
1822 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1823 if (!inputBuffer
[tid
].empty() ||
1824 !executeInfo
[tid
].inFlightInsts
->empty()) {
1835 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1836 delete funcUnits
[i
];
1838 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1839 delete executeInfo
[tid
].inFlightInsts
;
1843 Execute::instIsRightStream(MinorDynInstPtr inst
)
1845 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1849 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1853 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1854 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1859 MinorCPU::MinorCPUPort
&
1860 Execute::getDcachePort()
1862 return lsq
.getDcachePort();