2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "cpu/minor/execute.hh"
42 #include "arch/locked_mem.hh"
43 #include "arch/registers.hh"
44 #include "arch/utility.hh"
45 #include "cpu/minor/cpu.hh"
46 #include "cpu/minor/exec_context.hh"
47 #include "cpu/minor/fetch1.hh"
48 #include "cpu/minor/lsq.hh"
49 #include "cpu/op_class.hh"
50 #include "debug/Activity.hh"
51 #include "debug/Branch.hh"
52 #include "debug/Drain.hh"
53 #include "debug/MinorExecute.hh"
54 #include "debug/MinorInterrupt.hh"
55 #include "debug/MinorMem.hh"
56 #include "debug/MinorTrace.hh"
57 #include "debug/PCEvent.hh"
62 Execute::Execute(const std::string
&name_
,
64 MinorCPUParams
¶ms
,
65 Latch
<ForwardInstData
>::Output inp_
,
66 Latch
<BranchData
>::Input out_
) :
71 issueLimit(params
.executeIssueLimit
),
72 memoryIssueLimit(params
.executeMemoryIssueLimit
),
73 commitLimit(params
.executeCommitLimit
),
74 memoryCommitLimit(params
.executeMemoryCommitLimit
),
75 processMoreThanOneInput(params
.executeCycleInput
),
76 fuDescriptions(*params
.executeFuncUnits
),
77 numFuncUnits(fuDescriptions
.funcUnits
.size()),
78 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
79 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
80 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
81 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
82 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
84 params
.executeMaxAccessesInMemory
,
85 params
.executeMemoryWidth
,
86 params
.executeLSQRequestsQueueSize
,
87 params
.executeLSQTransfersQueueSize
,
88 params
.executeLSQStoreBufferSize
,
89 params
.executeLSQMaxStoreBufferStoresPerCycle
),
90 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
95 if (commitLimit
< 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
100 if (issueLimit
< 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
105 if (memoryIssueLimit
< 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
110 if (memoryCommitLimit
> commitLimit
) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_
, memoryCommitLimit
, commitLimit
);
116 if (params
.executeInputBufferSize
< 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
118 params
.executeInputBufferSize
);
121 if (params
.executeInputBufferSize
< 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
123 params
.executeInputBufferSize
);
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
129 unsigned int total_slots
= 0;
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
133 std::ostringstream fu_name
;
134 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots
+= fu_description
->opLat
;
141 fu_name
<< name_
<< ".fu." << i
;
143 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
145 funcUnits
.push_back(fu
);
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
150 bool found_fu
= false;
151 unsigned int fu_index
= 0;
153 while (fu_index
< numFuncUnits
&& !found_fu
)
155 if (funcUnits
[fu_index
]->provides(
156 static_cast<OpClass
>(op_class
)))
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings
[op_class
]);
169 /* Per-thread structures */
170 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
171 std::string tid_str
= std::to_string(tid
);
174 inputBuffer
.push_back(
175 InputBuffer
<ForwardInstData
>(
176 name_
+ ".inputBuffer" + tid_str
, "insts",
177 params
.executeInputBufferSize
));
180 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
182 /* In-flight instruction records */
183 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
184 ReportTraitsAdaptor
<QueuedInst
> >(
185 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
187 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
188 ReportTraitsAdaptor
<QueuedInst
> >(
189 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
193 const ForwardInstData
*
194 Execute::getInput(ThreadID tid
)
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer
[tid
].empty()) {
198 const ForwardInstData
&head
= inputBuffer
[tid
].front();
200 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
207 Execute::popInput(ThreadID tid
)
209 if (!inputBuffer
[tid
].empty())
210 inputBuffer
[tid
].pop();
212 executeInfo
[tid
].inputIndex
= 0;
216 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
218 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
219 const TheISA::PCState
&pc_before
= inst
->pc
;
220 TheISA::PCState target
= thread
->pcState();
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
226 inst
->isLastOpInInst() &&
227 (inst
->staticInst
->isSerializeAfter() ||
228 inst
->staticInst
->isSquashAfter() ||
229 inst
->staticInst
->isIprAccess());
231 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
232 pc_before
, target
, (force_branch
? " (forcing)" : ""));
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch
= pc_before
!= target
||
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason
= BranchData::NoBranch
;
242 if (fault
== NoFault
)
244 TheISA::advancePC(target
, inst
->staticInst
);
245 thread
->pcState(target
);
247 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
251 if (thread
->status() == ThreadContext::Suspended
) {
252 /* Thread got suspended */
253 DPRINTF(Branch
, "Thread got suspended: branch from 0x%x to 0x%x "
255 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
257 reason
= BranchData::SuspendThread
;
258 } else if (inst
->predictedTaken
&& !force_branch
) {
259 /* Predicted to branch */
261 /* No branch was taken, change stream to get us back to the
262 * intended PC value */
263 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
264 " none happened inst: %s\n",
265 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
267 reason
= BranchData::BadlyPredictedBranch
;
268 } else if (inst
->predictedTarget
== target
) {
269 /* Branch prediction got the right target, kill the branch and
271 * Note that this information to the branch predictor might get
272 * overwritten by a "real" branch during this cycle */
273 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
275 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
277 reason
= BranchData::CorrectlyPredictedBranch
;
279 /* Branch prediction got the wrong target */
280 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
281 " but got the wrong target (actual: 0x%x) inst: %s\n",
282 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
283 target
.instAddr(), *inst
);
285 reason
= BranchData::BadlyPredictedBranchTarget
;
287 } else if (must_branch
) {
288 /* Unpredicted branch */
289 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
290 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
292 reason
= BranchData::UnpredictedBranch
;
294 /* No branch at all */
295 reason
= BranchData::NoBranch
;
298 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
302 Execute::updateBranchData(
304 BranchData::Reason reason
,
305 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
308 if (reason
!= BranchData::NoBranch
) {
309 /* Bump up the stream sequence number on a real branch*/
310 if (BranchData::isStreamChange(reason
))
311 executeInfo
[tid
].streamSeqNum
++;
313 /* Branches (even mis-predictions) don't change the predictionSeqNum,
314 * just the streamSeqNum */
315 branch
= BranchData(reason
, tid
,
316 executeInfo
[tid
].streamSeqNum
,
317 /* Maintaining predictionSeqNum if there's no inst is just a
318 * courtesy and looks better on minorview */
319 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
320 : inst
->id
.predictionSeqNum
),
323 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
328 Execute::handleMemResponse(MinorDynInstPtr inst
,
329 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
331 ThreadID thread_id
= inst
->id
.threadId
;
332 ThreadContext
*thread
= cpu
.getContext(thread_id
);
334 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
336 PacketPtr packet
= response
->packet
;
338 bool is_load
= inst
->staticInst
->isLoad();
339 bool is_store
= inst
->staticInst
->isStore();
340 bool is_atomic
= inst
->staticInst
->isAtomic();
341 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
343 /* If true, the trace's predicate value will be taken from the exec
344 * context predicate, otherwise, it will be set to false */
345 bool use_context_predicate
= true;
347 if (response
->fault
!= NoFault
) {
348 /* Invoke memory faults. */
349 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
350 response
->fault
->name());
352 if (inst
->staticInst
->isPrefetch()) {
353 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
354 response
->fault
->name());
356 /* Don't assign to fault */
358 /* Take the fault raised during the TLB/memory access */
359 fault
= response
->fault
;
361 fault
->invoke(thread
, inst
->staticInst
);
363 } else if (!packet
) {
364 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
366 use_context_predicate
= false;
367 } else if (packet
->isError()) {
368 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
371 fatal("Received error response packet for inst: %s\n", *inst
);
372 } else if (is_store
|| is_load
|| is_prefetch
|| is_atomic
) {
375 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
376 *inst
, packet
->getAddr(), packet
->getSize());
378 if (is_load
&& packet
->getSize() > 0) {
379 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
380 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
383 /* Complete the memory access instruction */
384 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
387 if (fault
!= NoFault
) {
388 /* Invoke fault created by instruction completion */
389 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
391 fault
->invoke(thread
, inst
->staticInst
);
393 /* Stores need to be pushed into the store buffer to finish
395 if (response
->needsToBeSentToStoreBuffer())
396 lsq
.sendStoreToStoreBuffer(response
);
399 fatal("There should only ever be reads, "
400 "writes or faults at this point\n");
403 lsq
.popResponse(response
);
405 if (inst
->traceData
) {
406 inst
->traceData
->setPredicate((use_context_predicate
?
407 context
.readPredicate() : false));
410 doInstCommitAccounting(inst
);
412 /* Generate output to account for branches */
413 tryToBranch(inst
, fault
, branch
);
417 Execute::isInterrupted(ThreadID thread_id
) const
419 return cpu
.checkInterrupts(cpu
.getContext(thread_id
));
423 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
425 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
426 cpu
.getContext(thread_id
)->pcState());
428 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt
429 (cpu
.getContext(thread_id
));
431 if (interrupt
!= NoFault
) {
432 /* The interrupt *must* set pcState */
433 cpu
.getInterruptController(thread_id
)->updateIntrInfo
434 (cpu
.getContext(thread_id
));
435 interrupt
->invoke(cpu
.getContext(thread_id
));
437 assert(!lsq
.accessesInFlight());
439 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
440 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
442 /* Assume that an interrupt *must* cause a branch. Assert this? */
444 updateBranchData(thread_id
, BranchData::Interrupt
,
445 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
449 return interrupt
!= NoFault
;
453 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
454 bool &passed_predicate
, Fault
&fault
)
458 /* Set to true if the mem op. is issued and sent to the mem system */
459 passed_predicate
= false;
461 if (!lsq
.canRequest()) {
462 /* Not acting on instruction yet as the memory
466 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
467 TheISA::PCState old_pc
= thread
->pcState();
469 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
472 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
474 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
477 if (init_fault
!= NoFault
) {
478 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
479 " initiateAcc: %s\n", *inst
, init_fault
->name());
482 /* Only set this if the instruction passed its
484 passed_predicate
= context
.readPredicate();
486 /* Set predicate in tracing */
488 inst
->traceData
->setPredicate(passed_predicate
);
490 /* If the instruction didn't pass its predicate (and so will not
491 * progress from here) Try to branch to correct and branch
493 if (!passed_predicate
) {
494 /* Leave it up to commit to handle the fault */
495 lsq
.pushFailedRequest(inst
);
499 /* Restore thread PC */
500 thread
->pcState(old_pc
);
507 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
509 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
511 unsigned int ret
= index
+ 1;
513 if (ret
== cycle_size
)
519 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
521 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
526 ret
= cycle_size
- 1;
532 Execute::issue(ThreadID thread_id
)
534 const ForwardInstData
*insts_in
= getInput(thread_id
);
535 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
537 /* Early termination if we have no instructions */
541 /* Start from the first FU */
542 unsigned int fu_index
= 0;
544 /* Remains true while instructions are still being issued. If any
545 * instruction fails to issue, this is set to false and we exit issue.
546 * This strictly enforces in-order issue. For other issue behaviours,
547 * a more complicated test in the outer while loop below is needed. */
550 /* Number of insts issues this cycle to check for issueLimit */
551 unsigned num_insts_issued
= 0;
553 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
554 unsigned num_mem_insts_issued
= 0;
556 /* Number of instructions discarded this cycle in order to enforce a
557 * discardLimit. @todo, add that parameter? */
558 unsigned num_insts_discarded
= 0;
561 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
562 Fault fault
= inst
->fault
;
563 bool discarded
= false;
564 bool issued_mem_ref
= false;
566 if (inst
->isBubble()) {
569 } else if (cpu
.getContext(thread_id
)->status() ==
570 ThreadContext::Suspended
)
572 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
577 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
578 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
579 " state was unexpected, expected: %d\n",
580 *inst
, thread
.streamSeqNum
);
584 /* Try and issue an instruction into an FU, assume we didn't and
585 * fix that in the loop */
588 /* Try FU from 0 each instruction */
591 /* Try and issue a single instruction stepping through the
594 FUPipeline
*fu
= funcUnits
[fu_index
];
596 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
599 /* Does the examined fu have the OpClass-related capability
600 * needed to execute this instruction? Faults can always
601 * issue to any FU but probably should just 'live' in the
602 * inFlightInsts queue rather than having an FU. */
603 bool fu_is_capable
= (!inst
->isFault() ?
604 fu
->provides(inst
->staticInst
->opClass()) : true);
606 if (inst
->isNoCostInst()) {
607 /* Issue free insts. to a fake numbered FU */
608 fu_index
= noCostFUIndex
;
610 /* And start the countdown on activity to allow
611 * this instruction to get to the end of its FU */
612 cpu
.activityRecorder
->activity();
614 /* Mark the destinations for this instruction as
616 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
617 Cycles(0), cpu
.getContext(thread_id
), false);
619 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
620 inst
->fuIndex
= noCostFUIndex
;
621 inst
->extraCommitDelay
= Cycles(0);
622 inst
->extraCommitDelayExpr
= NULL
;
624 /* Push the instruction onto the inFlight queue so
625 * it can be committed in order */
626 QueuedInst
fu_inst(inst
);
627 thread
.inFlightInsts
->push(fu_inst
);
631 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
633 if (!fu_is_capable
) {
634 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
635 " capable\n", fu_index
);
637 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
638 " already busy\n", fu_index
);
640 } else if (fu
->stalled
) {
641 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
644 } else if (!fu
->canInsert()) {
645 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
646 " for another: %d cycles\n",
647 *inst
, fu
->cyclesBeforeInsert());
649 MinorFUTiming
*timing
= (!inst
->isFault() ?
650 fu
->findTiming(inst
->staticInst
) : NULL
);
652 const std::vector
<Cycles
> *src_latencies
=
653 (timing
? &(timing
->srcRegsRelativeLats
)
656 const std::vector
<bool> *cant_forward_from_fu_indices
=
657 &(fu
->cantForwardFromFUIndices
);
659 if (timing
&& timing
->suppress
) {
660 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
661 " decoding is suppressing it\n",
663 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
664 src_latencies
, cant_forward_from_fu_indices
,
665 cpu
.curCycle(), cpu
.getContext(thread_id
)))
667 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
670 /* Can insert the instruction into this FU */
671 DPRINTF(MinorExecute
, "Issuing inst: %s"
672 " into FU %d\n", *inst
,
675 Cycles extra_dest_retire_lat
= Cycles(0);
676 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
677 Cycles extra_assumed_lat
= Cycles(0);
679 /* Add the extraCommitDelay and extraAssumeLat to
680 * the FU pipeline timings */
682 extra_dest_retire_lat
=
683 timing
->extraCommitLat
;
684 extra_dest_retire_lat_expr
=
685 timing
->extraCommitLatExpr
;
687 timing
->extraAssumedLat
;
690 issued_mem_ref
= inst
->isMemRef();
692 QueuedInst
fu_inst(inst
);
694 /* Decorate the inst with FU details */
695 inst
->fuIndex
= fu_index
;
696 inst
->extraCommitDelay
= extra_dest_retire_lat
;
697 inst
->extraCommitDelayExpr
=
698 extra_dest_retire_lat_expr
;
700 if (issued_mem_ref
) {
701 /* Remember which instruction this memory op
702 * depends on so that initiateAcc can be called
704 if (allowEarlyMemIssue
) {
705 inst
->instToWaitFor
=
706 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
707 cpu
.getContext(thread_id
));
709 if (lsq
.getLastMemBarrier(thread_id
) >
712 DPRINTF(MinorExecute
, "A barrier will"
713 " cause a delay in mem ref issue of"
714 " inst: %s until after inst"
715 " %d(exec)\n", *inst
,
716 lsq
.getLastMemBarrier(thread_id
));
718 inst
->instToWaitFor
=
719 lsq
.getLastMemBarrier(thread_id
);
721 DPRINTF(MinorExecute
, "Memory ref inst:"
722 " %s must wait for inst %d(exec)"
724 *inst
, inst
->instToWaitFor
);
727 inst
->canEarlyIssue
= true;
729 /* Also queue this instruction in the memory ref
730 * queue to ensure in-order issue to the LSQ */
731 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
733 thread
.inFUMemInsts
->push(fu_inst
);
738 /* And start the countdown on activity to allow
739 * this instruction to get to the end of its FU */
740 cpu
.activityRecorder
->activity();
742 /* Mark the destinations for this instruction as
744 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
745 fu
->description
.opLat
+
746 extra_dest_retire_lat
+
748 cpu
.getContext(thread_id
),
749 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
751 /* Push the instruction onto the inFlight queue so
752 * it can be committed in order */
753 thread
.inFlightInsts
->push(fu_inst
);
760 } while (fu_index
!= numFuncUnits
&& !issued
);
763 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
767 /* Generate MinorTrace's MinorInst lines. Do this at commit
768 * to allow better instruction annotation? */
769 if (DTRACE(MinorTrace
) && !inst
->isBubble())
770 inst
->minorTraceInst(*this);
772 /* Mark up barriers in the LSQ */
773 if (!discarded
&& inst
->isInst() &&
774 inst
->staticInst
->isMemBarrier())
776 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
777 lsq
.issuedMemBarrierInst(inst
);
780 if (inst
->traceData
&& setTraceTimeOnIssue
) {
781 inst
->traceData
->setWhen(curTick());
785 num_mem_insts_issued
++;
788 num_insts_discarded
++;
789 } else if (!inst
->isBubble()) {
792 if (num_insts_issued
== issueLimit
)
793 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
797 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
801 /* Got to the end of a line */
802 if (thread
.inputIndex
== insts_in
->width()) {
804 /* Set insts_in to null to force us to leave the surrounding
808 if (processMoreThanOneInput
) {
809 DPRINTF(MinorExecute
, "Wrapping\n");
810 insts_in
= getInput(thread_id
);
813 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
814 /* We still have instructions */
815 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
816 issued
&& /* We've not yet failed to issue an instruction */
817 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
818 num_mem_insts_issued
!= memoryIssueLimit
);
820 return num_insts_issued
;
824 Execute::tryPCEvents(ThreadID thread_id
)
826 ThreadContext
*thread
= cpu
.getContext(thread_id
);
827 unsigned int num_pc_event_checks
= 0;
829 /* Handle PC events on instructions */
832 oldPC
= thread
->instAddr();
833 cpu
.system
->pcEventQueue
.service(thread
);
834 num_pc_event_checks
++;
835 } while (oldPC
!= thread
->instAddr());
837 if (num_pc_event_checks
> 1) {
838 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
842 return num_pc_event_checks
> 1;
846 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
848 assert(!inst
->isFault());
850 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
852 /* Increment the many and various inst and op counts in the
853 * thread and system */
854 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
858 cpu
.stats
.numInsts
++;
859 cpu
.system
->totalNumInsts
++;
861 /* Act on events related to instruction counts */
862 cpu
.comInstEventQueue
[inst
->id
.threadId
]->serviceEvents(thread
->numInst
);
863 cpu
.system
->instEventQueue
.serviceEvents(cpu
.system
->totalNumInsts
);
868 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
869 [inst
->staticInst
->opClass()]++;
871 /* Set the CP SeqNum to the numOps commit number */
873 inst
->traceData
->setCPSeq(thread
->numOp
);
875 cpu
.probeInstCommit(inst
->staticInst
, inst
->pc
.instAddr());
879 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
880 BranchData
&branch
, Fault
&fault
, bool &committed
,
881 bool &completed_mem_issue
)
883 ThreadID thread_id
= inst
->id
.threadId
;
884 ThreadContext
*thread
= cpu
.getContext(thread_id
);
886 bool completed_inst
= true;
889 /* Is the thread for this instruction suspended? In that case, just
890 * stall as long as there are no pending interrupts */
891 if (thread
->status() == ThreadContext::Suspended
&&
892 !isInterrupted(thread_id
))
894 panic("We should never hit the case where we try to commit from a "
895 "suspended thread as the streamSeqNum should not match");
896 } else if (inst
->isFault()) {
897 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
899 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
900 inst
->fault
->name());
903 inst
->fault
->invoke(thread
, NULL
);
905 tryToBranch(inst
, fault
, branch
);
906 } else if (inst
->staticInst
->isMemRef()) {
907 /* Memory accesses are executed in two parts:
908 * executeMemRefInst -- calculates the EA and issues the access
909 * to memory. This is done here.
910 * handleMemResponse -- handles the response packet, done by
913 * While the memory access is in its FU, the EA is being
914 * calculated. At the end of the FU, when it is ready to
915 * 'commit' (in this function), the access is presented to the
916 * memory queues. When a response comes back from memory,
917 * Execute::commit will commit it.
919 bool predicate_passed
= false;
920 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
921 predicate_passed
, fault
);
923 if (completed_mem_inst
&& fault
!= NoFault
) {
924 if (early_memory_issue
) {
925 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
927 /* Don't execute the fault, just stall the instruction
928 * until it gets to the head of inFlightInsts */
929 inst
->canEarlyIssue
= false;
930 /* Not completed as we'll come here again to pick up
931 * the fault when we get to the end of the FU */
932 completed_inst
= false;
934 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
936 fault
->invoke(thread
, NULL
);
938 tryToBranch(inst
, fault
, branch
);
939 completed_inst
= true;
942 completed_inst
= completed_mem_inst
;
944 completed_mem_issue
= completed_inst
;
945 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
946 !lsq
.canPushIntoStoreBuffer())
948 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
949 " there isn't space in the store buffer\n", *inst
);
951 completed_inst
= false;
952 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
953 && !branch
.isBubble()){
954 /* This instruction can suspend, need to be able to communicate
955 * backwards, so no other branches may evaluate this cycle*/
956 completed_inst
= false;
958 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
960 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
962 fault
= inst
->staticInst
->execute(&context
,
965 /* Set the predicate for tracing and dump */
967 inst
->traceData
->setPredicate(context
.readPredicate());
971 if (fault
!= NoFault
) {
972 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
973 *inst
, fault
->name());
974 fault
->invoke(thread
, inst
->staticInst
);
977 doInstCommitAccounting(inst
);
978 tryToBranch(inst
, fault
, branch
);
981 if (completed_inst
) {
982 /* Keep a copy of this instruction's predictionSeqNum just in case
983 * we need to issue a branch without an instruction (such as an
985 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
987 /* Check to see if this instruction suspended the current thread. */
988 if (!inst
->isFault() &&
989 thread
->status() == ThreadContext::Suspended
&&
990 branch
.isBubble() && /* It didn't branch too */
991 !isInterrupted(thread_id
)) /* Don't suspend if we have
994 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
996 assert(resume_pc
.microPC() == 0);
998 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
999 " inst: %s\n", thread_id
, *inst
);
1001 cpu
.stats
.numFetchSuspends
++;
1003 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
1008 return completed_inst
;
1012 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1015 Fault fault
= NoFault
;
1016 Cycles now
= cpu
.curCycle();
1017 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1020 * Try and execute as many instructions from the end of FU pipelines as
1021 * possible. This *doesn't* include actually advancing the pipelines.
1023 * We do this by looping on the front of the inFlightInsts queue for as
1024 * long as we can find the desired instruction at the end of the
1025 * functional unit it was issued to without seeing a branch or a fault.
1026 * In this function, these terms are used:
1027 * complete -- The instruction has finished its passage through
1028 * its functional unit and its fate has been decided
1029 * (committed, discarded, issued to the memory system)
1030 * commit -- The instruction is complete(d), not discarded and has
1031 * its effects applied to the CPU state
1032 * discard(ed) -- The instruction is complete but not committed
1033 * as its streamSeqNum disagrees with the current
1034 * Execute::streamSeqNum
1036 * Commits are also possible from two other places:
1038 * 1) Responses returning from the LSQ
1039 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1040 * than their position in the inFlightInsts queue, but after all
1041 * their dependencies are resolved.
1044 /* Has an instruction been completed? Once this becomes false, we stop
1045 * trying to complete instructions. */
1046 bool completed_inst
= true;
1048 /* Number of insts committed this cycle to check against commitLimit */
1049 unsigned int num_insts_committed
= 0;
1051 /* Number of memory access instructions committed to check against
1053 unsigned int num_mem_refs_committed
= 0;
1055 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1056 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1057 *(ex_info
.inFlightInsts
->front().inst
),
1058 ex_info
.lastCommitWasEndOfMacroop
);
1061 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1062 !branch
.isStreamChange() && /* No real branch */
1063 fault
== NoFault
&& /* No faults */
1064 completed_inst
&& /* Still finding instructions to execute */
1065 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1068 if (only_commit_microops
) {
1069 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1071 *(ex_info
.inFlightInsts
->front().inst
));
1074 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1076 InstSeqNum head_exec_seq_num
=
1077 head_inflight_inst
->inst
->id
.execSeqNum
;
1079 /* The instruction we actually process if completed_inst
1080 * remains true to the end of the loop body.
1081 * Start by considering the the head of the in flight insts queue */
1082 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1084 bool committed_inst
= false;
1085 bool discard_inst
= false;
1086 bool completed_mem_ref
= false;
1087 bool issued_mem_ref
= false;
1088 bool early_memory_issue
= false;
1090 /* Must set this again to go around the loop */
1091 completed_inst
= false;
1093 /* If we're just completing a macroop before an interrupt or drain,
1094 * can we stil commit another microop (rather than a memory response)
1095 * without crosing into the next full instruction? */
1096 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1097 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1099 /* Can we find a mem response for this inst */
1100 LSQ::LSQRequestPtr mem_response
=
1101 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1103 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1106 /* Test for PC events after every instruction */
1107 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1108 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1110 /* Branch as there was a change in PC */
1111 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1112 MinorDynInst::bubble(), thread
->pcState(), branch
);
1113 } else if (mem_response
&&
1114 num_mem_refs_committed
< memoryCommitLimit
)
1116 /* Try to commit from the memory responses next */
1117 discard_inst
= inst
->id
.streamSeqNum
!=
1118 ex_info
.streamSeqNum
|| discard
;
1120 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1123 /* Complete or discard the response */
1125 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1126 " stream state was unexpected, expected: %d\n",
1127 *inst
, ex_info
.streamSeqNum
);
1129 lsq
.popResponse(mem_response
);
1131 handleMemResponse(inst
, mem_response
, branch
, fault
);
1132 committed_inst
= true;
1135 completed_mem_ref
= true;
1136 completed_inst
= true;
1137 } else if (can_commit_insts
) {
1138 /* If true, this instruction will, subject to timing tweaks,
1139 * be considered for completion. try_to_commit flattens
1140 * the `if' tree a bit and allows other tests for inst
1141 * commit to be inserted here. */
1142 bool try_to_commit
= false;
1144 /* Try and issue memory ops early if they:
1145 * - Can push a request into the LSQ
1146 * - Have reached the end of their FUs
1147 * - Have had all their dependencies satisfied
1148 * - Are from the right stream
1150 * For any other case, leave it to the normal instruction
1151 * issue below to handle them.
1153 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1154 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1156 const MinorDynInstPtr head_mem_ref_inst
=
1157 ex_info
.inFUMemInsts
->front().inst
;
1158 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1159 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1161 /* Use this, possibly out of order, inst as the one
1162 * to 'commit'/send to the LSQ */
1163 if (!fu_inst
->isBubble() &&
1165 fu_inst
->canEarlyIssue
&&
1166 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1167 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1169 DPRINTF(MinorExecute
, "Issuing mem ref early"
1170 " inst: %s instToWaitFor: %d\n",
1171 *(fu_inst
), fu_inst
->instToWaitFor
);
1174 try_to_commit
= true;
1175 early_memory_issue
= true;
1176 completed_inst
= true;
1180 /* Try and commit FU-less insts */
1181 if (!completed_inst
&& inst
->isNoCostInst()) {
1182 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1184 try_to_commit
= true;
1185 completed_inst
= true;
1188 /* Try to issue from the ends of FUs and the inFlightInsts
1190 if (!completed_inst
&& !inst
->inLSQ
) {
1191 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1193 /* Try to commit from a functional unit */
1194 /* Is the head inst of the expected inst's FU actually the
1196 QueuedInst
&fu_inst
=
1197 funcUnits
[inst
->fuIndex
]->front();
1198 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1200 if (fu_inst
.inst
->isBubble()) {
1201 /* No instruction ready */
1202 completed_inst
= false;
1203 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1204 /* Past instruction: we must have already executed it
1205 * in the same cycle and so the head inst isn't
1206 * actually at the end of its pipeline
1207 * Future instruction: handled above and only for
1208 * mem refs on their way to the LSQ */
1209 } else if (fu_inst
.inst
->id
== inst
->id
) {
1210 /* All instructions can be committed if they have the
1211 * right execSeqNum and there are no in-flight
1212 * mem insts before us */
1213 try_to_commit
= true;
1214 completed_inst
= true;
1218 if (try_to_commit
) {
1219 discard_inst
= inst
->id
.streamSeqNum
!=
1220 ex_info
.streamSeqNum
|| discard
;
1222 /* Is this instruction discardable as its streamSeqNum
1224 if (!discard_inst
) {
1225 /* Try to commit or discard a non-memory instruction.
1226 * Memory ops are actually 'committed' from this FUs
1227 * and 'issued' into the memory system so we need to
1228 * account for them later (commit_was_mem_issue gets
1230 if (inst
->extraCommitDelayExpr
) {
1231 DPRINTF(MinorExecute
, "Evaluating expression for"
1232 " extra commit delay inst: %s\n", *inst
);
1234 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1236 TimingExprEvalContext
context(inst
->staticInst
,
1239 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1242 DPRINTF(MinorExecute
, "Extra commit delay expr"
1243 " result: %d\n", extra_delay
);
1245 if (extra_delay
< 128) {
1246 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1248 DPRINTF(MinorExecute
, "Extra commit delay was"
1249 " very long: %d\n", extra_delay
);
1251 inst
->extraCommitDelayExpr
= NULL
;
1254 /* Move the extraCommitDelay from the instruction
1255 * into the minimumCommitCycle */
1256 if (inst
->extraCommitDelay
!= Cycles(0)) {
1257 inst
->minimumCommitCycle
= cpu
.curCycle() +
1258 inst
->extraCommitDelay
;
1259 inst
->extraCommitDelay
= Cycles(0);
1262 /* @todo Think about making lastMemBarrier be
1263 * MAX_UINT_64 to avoid using 0 as a marker value */
1264 if (!inst
->isFault() && inst
->isMemRef() &&
1265 lsq
.getLastMemBarrier(thread_id
) <
1266 inst
->id
.execSeqNum
&&
1267 lsq
.getLastMemBarrier(thread_id
) != 0)
1269 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1270 " as there are incomplete barriers in flight\n",
1272 completed_inst
= false;
1273 } else if (inst
->minimumCommitCycle
> now
) {
1274 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1275 " as it wants to be stalled for %d more cycles\n",
1276 *inst
, inst
->minimumCommitCycle
- now
);
1277 completed_inst
= false;
1279 completed_inst
= commitInst(inst
,
1280 early_memory_issue
, branch
, fault
,
1281 committed_inst
, issued_mem_ref
);
1284 /* Discard instruction */
1285 completed_inst
= true;
1288 if (completed_inst
) {
1289 /* Allow the pipeline to advance. If the FU head
1290 * instruction wasn't the inFlightInsts head
1291 * but had already been committed, it would have
1292 * unstalled the pipeline before here */
1293 if (inst
->fuIndex
!= noCostFUIndex
) {
1294 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1295 funcUnits
[inst
->fuIndex
]->stalled
= false;
1300 DPRINTF(MinorExecute
, "No instructions to commit\n");
1301 completed_inst
= false;
1304 /* All discardable instructions must also be 'completed' by now */
1305 assert(!(discard_inst
&& !completed_inst
));
1307 /* Instruction committed but was discarded due to streamSeqNum
1310 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1311 " state was unexpected, expected: %d\n",
1312 *inst
, ex_info
.streamSeqNum
);
1314 if (fault
== NoFault
)
1315 cpu
.stats
.numDiscardedOps
++;
1318 /* Mark the mem inst as being in the LSQ */
1319 if (issued_mem_ref
) {
1324 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1325 * as they've *definitely* exited the FUs */
1326 if (completed_inst
&& inst
->isMemRef()) {
1327 /* The MemRef could have been discarded from the FU or the memory
1328 * queue, so just check an FU instruction */
1329 if (!ex_info
.inFUMemInsts
->empty() &&
1330 ex_info
.inFUMemInsts
->front().inst
== inst
)
1332 ex_info
.inFUMemInsts
->pop();
1336 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1337 /* Note that this includes discarded insts */
1338 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1340 /* Got to the end of a full instruction? */
1341 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1342 inst
->isLastOpInInst();
1344 /* lastPredictionSeqNum is kept as a convenience to prevent its
1345 * value from changing too much on the minorview display */
1346 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1348 /* Finished with the inst, remove it from the inst queue and
1349 * clear its dependencies */
1350 ex_info
.inFlightInsts
->pop();
1352 /* Complete barriers in the LSQ/move to store buffer */
1353 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1354 DPRINTF(MinorMem
, "Completing memory barrier"
1355 " inst: %s committed: %d\n", *inst
, committed_inst
);
1356 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1359 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1362 /* Handle per-cycle instruction counting */
1363 if (committed_inst
) {
1364 bool is_no_cost_inst
= inst
->isNoCostInst();
1366 /* Don't show no cost instructions as having taken a commit
1368 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1369 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1371 if (!is_no_cost_inst
)
1372 num_insts_committed
++;
1374 if (num_insts_committed
== commitLimit
)
1375 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1377 /* Re-set the time of the instruction if that's required for
1379 if (inst
->traceData
) {
1380 if (setTraceTimeOnCommit
)
1381 inst
->traceData
->setWhen(curTick());
1382 inst
->traceData
->dump();
1385 if (completed_mem_ref
)
1386 num_mem_refs_committed
++;
1388 if (num_mem_refs_committed
== memoryCommitLimit
)
1389 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1395 Execute::isInbetweenInsts(ThreadID thread_id
) const
1397 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1398 !lsq
.accessesInFlight();
1404 if (!inp
.outputWire
->isBubble())
1405 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1407 BranchData
&branch
= *out
.inputWire
;
1409 unsigned int num_issued
= 0;
1411 /* Do all the cycle-wise activities for dcachePort here to potentially
1412 * free up input spaces in the LSQ's requests queue */
1415 /* Check interrupts first. Will halt commit if interrupt found */
1416 bool interrupted
= false;
1417 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1419 if (interrupt_tid
!= InvalidThreadID
) {
1420 /* Signalling an interrupt this cycle, not issuing/committing from
1421 * any other threads */
1422 } else if (!branch
.isBubble()) {
1423 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1424 * without overwriting them */
1425 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1426 " branch to complete\n");
1428 ThreadID commit_tid
= getCommittingThread();
1430 if (commit_tid
!= InvalidThreadID
) {
1431 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1433 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1435 /* commit can set stalled flags observable to issue and so *must* be
1437 if (commit_info
.drainState
!= NotDraining
) {
1438 if (commit_info
.drainState
== DrainCurrentInst
) {
1439 /* Commit only micro-ops, don't kill anything else */
1440 commit(commit_tid
, true, false, branch
);
1442 if (isInbetweenInsts(commit_tid
))
1443 setDrainState(commit_tid
, DrainHaltFetch
);
1445 /* Discard any generated branch */
1446 branch
= BranchData::bubble();
1447 } else if (commit_info
.drainState
== DrainAllInsts
) {
1448 /* Kill all instructions */
1449 while (getInput(commit_tid
))
1450 popInput(commit_tid
);
1451 commit(commit_tid
, false, true, branch
);
1454 /* Commit micro-ops only if interrupted. Otherwise, commit
1455 * anything you like */
1456 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1458 bool only_commit_microops
= interrupted
&&
1459 hasInterrupt(commit_tid
);
1460 commit(commit_tid
, only_commit_microops
, false, branch
);
1463 /* Halt fetch, but don't do it until we have the current instruction in
1465 if (commit_info
.drainState
== DrainHaltFetch
) {
1466 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1467 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1469 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1470 setDrainState(commit_tid
, DrainAllInsts
);
1473 ThreadID issue_tid
= getIssuingThread();
1474 /* This will issue merrily even when interrupted in the sure and
1475 * certain knowledge that the interrupt with change the stream */
1476 if (issue_tid
!= InvalidThreadID
) {
1477 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1479 num_issued
= issue(issue_tid
);
1484 /* Run logic to step functional units + decide if we are active on the next
1486 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1487 bool can_issue_next
= false;
1489 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1490 /* Find the next issuable instruction for each thread and see if it can
1492 if (getInput(tid
)) {
1493 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1494 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1495 if (inst
->isFault()) {
1496 can_issue_next
= true;
1497 } else if (!inst
->isBubble()) {
1498 next_issuable_insts
.push_back(inst
);
1503 bool becoming_stalled
= true;
1505 /* Advance the pipelines and note whether they still need to be
1507 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1508 FUPipeline
*fu
= funcUnits
[i
];
1511 /* If we need to tick again, the pipeline will have been left or set
1512 * to be unstalled */
1513 if (fu
->occupancy
!=0 && !fu
->stalled
)
1514 becoming_stalled
= false;
1516 /* Could we possibly issue the next instruction from any thread?
1517 * This is quite an expensive test and is only used to determine
1518 * if the CPU should remain active, only run it if we aren't sure
1519 * we are active next cycle yet */
1520 for (auto inst
: next_issuable_insts
) {
1521 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1522 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1523 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1524 cpu
.getContext(inst
->id
.threadId
))) {
1525 can_issue_next
= true;
1531 bool head_inst_might_commit
= false;
1533 /* Could the head in flight insts be committed */
1534 for (auto const &info
: executeInfo
) {
1535 if (!info
.inFlightInsts
->empty()) {
1536 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1538 if (head_inst
.inst
->isNoCostInst()) {
1539 head_inst_might_commit
= true;
1541 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1543 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1544 lsq
.findResponse(head_inst
.inst
))
1546 head_inst_might_commit
= true;
1553 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1554 (num_issued
!= 0 ? " (issued some insts)" : ""),
1555 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1556 (can_issue_next
? " (can issued next inst)" : ""),
1557 (head_inst_might_commit
? "(head inst might commit)" : ""),
1558 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1559 (interrupted
? " (interrupted)" : ""));
1562 num_issued
!= 0 || /* Issued some insts this cycle */
1563 !becoming_stalled
|| /* Some FU pipelines can still move */
1564 can_issue_next
|| /* Can still issue a new inst */
1565 head_inst_might_commit
|| /* Could possible commit the next inst */
1566 lsq
.needsToTick() || /* Must step the dcache port */
1567 interrupted
; /* There are pending interrupts */
1569 if (!need_to_tick
) {
1570 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1571 " advanceable FUs\n");
1574 /* Wake up if we need to tick again */
1576 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1578 /* Note activity of following buffer */
1579 if (!branch
.isBubble())
1580 cpu
.activityRecorder
->activity();
1582 /* Make sure the input (if any left) is pushed */
1583 if (!inp
.outputWire
->isBubble())
1584 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1588 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1590 ThreadID tid
= interruptPriority
;
1591 /* Evaluate interrupts in round-robin based upon service */
1593 /* Has an interrupt been signalled? This may not be acted on
1594 * straighaway so this is different from took_interrupt */
1595 bool thread_interrupted
= false;
1597 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1598 /* This is here because it seems that after drainResume the
1599 * interrupt controller isn't always set */
1600 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1602 interrupted
= interrupted
|| thread_interrupted
;
1604 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1606 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1607 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1608 /* Act on interrupts */
1609 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1610 if (takeInterrupt(tid
, branch
)) {
1611 interruptPriority
= tid
;
1615 tid
= (tid
+ 1) % cpu
.numThreads
;
1617 } while (tid
!= interruptPriority
);
1619 return InvalidThreadID
;
1623 Execute::hasInterrupt(ThreadID thread_id
)
1625 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1626 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1627 isInterrupted(thread_id
);
1634 Execute::minorTrace() const
1636 std::ostringstream insts
;
1637 std::ostringstream stalled
;
1639 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1641 inputBuffer
[0].minorTrace();
1642 scoreboard
[0].minorTrace();
1644 /* Report functional unit stalling in one string */
1646 while (i
< numFuncUnits
)
1648 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1650 if (i
!= numFuncUnits
)
1654 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1655 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1656 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1657 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1659 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1660 std::mem_fun(&FUPipeline::minorTrace
));
1662 executeInfo
[0].inFlightInsts
->minorTrace();
1663 executeInfo
[0].inFUMemInsts
->minorTrace();
1667 Execute::getCommittingThread()
1669 std::vector
<ThreadID
> priority_list
;
1671 switch (cpu
.threadPolicy
) {
1672 case Enums::SingleThreaded
:
1674 case Enums::RoundRobin
:
1675 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1678 priority_list
= cpu
.randomPriority();
1681 panic("Invalid thread policy");
1684 for (auto tid
: priority_list
) {
1685 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1687 bool is_thread_active
=
1688 cpu
.getContext(tid
)->status() == ThreadContext::Active
;
1689 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1692 if (can_commit_insts
) {
1693 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1694 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1696 can_commit_insts
= can_commit_insts
&&
1697 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1700 bool can_transfer_mem_inst
= false;
1701 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1702 const MinorDynInstPtr head_mem_ref_inst
=
1703 ex_info
.inFUMemInsts
->front().inst
;
1704 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1705 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1706 can_transfer_mem_inst
=
1707 !fu_inst
->isBubble() &&
1708 fu_inst
->id
.threadId
== tid
&&
1710 fu_inst
->canEarlyIssue
&&
1711 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1714 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1715 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1716 inst
->fuIndex
!= noCostFUIndex
)
1718 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1719 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1720 fu_inst
.inst
->id
== inst
->id
;
1723 can_commit_insts
= can_commit_insts
&&
1724 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1729 if (can_commit_insts
) {
1730 commitPriority
= tid
;
1735 return InvalidThreadID
;
1739 Execute::getIssuingThread()
1741 std::vector
<ThreadID
> priority_list
;
1743 switch (cpu
.threadPolicy
) {
1744 case Enums::SingleThreaded
:
1746 case Enums::RoundRobin
:
1747 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1750 priority_list
= cpu
.randomPriority();
1753 panic("Invalid thread scheduling policy.");
1756 for (auto tid
: priority_list
) {
1757 if (cpu
.getContext(tid
)->status() == ThreadContext::Active
&&
1759 issuePriority
= tid
;
1764 return InvalidThreadID
;
1768 Execute::drainResume()
1770 DPRINTF(Drain
, "MinorExecute drainResume\n");
1772 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1773 setDrainState(tid
, NotDraining
);
1776 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1779 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1783 case Execute::NotDraining
:
1784 os
<< "NotDraining";
1786 case Execute::DrainCurrentInst
:
1787 os
<< "DrainCurrentInst";
1789 case Execute::DrainHaltFetch
:
1790 os
<< "DrainHaltFetch";
1792 case Execute::DrainAllInsts
:
1793 os
<< "DrainAllInsts";
1796 os
<< "Drain-" << static_cast<int>(state
);
1804 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1806 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1807 executeInfo
[thread_id
].drainState
= state
;
1813 DPRINTF(Drain
, "MinorExecute drain\n");
1815 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1816 if (executeInfo
[tid
].drainState
== NotDraining
) {
1817 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1819 /* Go to DrainCurrentInst if we're between microops
1820 * or waiting on an unbufferable memory operation.
1821 * Otherwise we can go straight to DrainHaltFetch
1823 if (isInbetweenInsts(tid
))
1824 setDrainState(tid
, DrainHaltFetch
);
1826 setDrainState(tid
, DrainCurrentInst
);
1829 return (isDrained() ? 0 : 1);
1833 Execute::isDrained()
1835 if (!lsq
.isDrained())
1838 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1839 if (!inputBuffer
[tid
].empty() ||
1840 !executeInfo
[tid
].inFlightInsts
->empty()) {
1851 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1852 delete funcUnits
[i
];
1854 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1855 delete executeInfo
[tid
].inFlightInsts
;
1859 Execute::instIsRightStream(MinorDynInstPtr inst
)
1861 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1865 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1869 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1870 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1875 MinorCPU::MinorCPUPort
&
1876 Execute::getDcachePort()
1878 return lsq
.getDcachePort();