2 * Copyright (c) 2013-2014,2018-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "cpu/minor/execute.hh"
40 #include "arch/locked_mem.hh"
41 #include "arch/registers.hh"
42 #include "arch/utility.hh"
43 #include "cpu/minor/cpu.hh"
44 #include "cpu/minor/exec_context.hh"
45 #include "cpu/minor/fetch1.hh"
46 #include "cpu/minor/lsq.hh"
47 #include "cpu/op_class.hh"
48 #include "debug/Activity.hh"
49 #include "debug/Branch.hh"
50 #include "debug/Drain.hh"
51 #include "debug/MinorExecute.hh"
52 #include "debug/MinorInterrupt.hh"
53 #include "debug/MinorMem.hh"
54 #include "debug/MinorTrace.hh"
55 #include "debug/PCEvent.hh"
60 Execute::Execute(const std::string
&name_
,
62 MinorCPUParams
¶ms
,
63 Latch
<ForwardInstData
>::Output inp_
,
64 Latch
<BranchData
>::Input out_
) :
69 issueLimit(params
.executeIssueLimit
),
70 memoryIssueLimit(params
.executeMemoryIssueLimit
),
71 commitLimit(params
.executeCommitLimit
),
72 memoryCommitLimit(params
.executeMemoryCommitLimit
),
73 processMoreThanOneInput(params
.executeCycleInput
),
74 fuDescriptions(*params
.executeFuncUnits
),
75 numFuncUnits(fuDescriptions
.funcUnits
.size()),
76 setTraceTimeOnCommit(params
.executeSetTraceTimeOnCommit
),
77 setTraceTimeOnIssue(params
.executeSetTraceTimeOnIssue
),
78 allowEarlyMemIssue(params
.executeAllowEarlyMemoryIssue
),
79 noCostFUIndex(fuDescriptions
.funcUnits
.size() + 1),
80 lsq(name_
+ ".lsq", name_
+ ".dcache_port",
82 params
.executeMaxAccessesInMemory
,
83 params
.executeMemoryWidth
,
84 params
.executeLSQRequestsQueueSize
,
85 params
.executeLSQTransfersQueueSize
,
86 params
.executeLSQStoreBufferSize
,
87 params
.executeLSQMaxStoreBufferStoresPerCycle
),
88 executeInfo(params
.numThreads
, ExecuteThreadInfo(params
.executeCommitLimit
)),
93 if (commitLimit
< 1) {
94 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
99 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_
,
103 if (memoryIssueLimit
< 1) {
104 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_
,
108 if (memoryCommitLimit
> commitLimit
) {
109 fatal("%s: executeMemoryCommitLimit (%d) must be <="
110 " executeCommitLimit (%d)\n",
111 name_
, memoryCommitLimit
, commitLimit
);
114 if (params
.executeInputBufferSize
< 1) {
115 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
116 params
.executeInputBufferSize
);
119 if (params
.executeInputBufferSize
< 1) {
120 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_
,
121 params
.executeInputBufferSize
);
124 /* This should be large enough to count all the in-FU instructions
125 * which need to be accounted for in the inFlightInsts
127 unsigned int total_slots
= 0;
129 /* Make FUPipelines for each MinorFU */
130 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
131 std::ostringstream fu_name
;
132 MinorFU
*fu_description
= fuDescriptions
.funcUnits
[i
];
134 /* Note the total number of instruction slots (for sizing
135 * the inFlightInst queue) and the maximum latency of any FU
136 * (for sizing the activity recorder) */
137 total_slots
+= fu_description
->opLat
;
139 fu_name
<< name_
<< ".fu." << i
;
141 FUPipeline
*fu
= new FUPipeline(fu_name
.str(), *fu_description
, cpu
);
143 funcUnits
.push_back(fu
);
146 /** Check that there is a functional unit for all operation classes */
147 for (int op_class
= No_OpClass
+ 1; op_class
< Num_OpClasses
; op_class
++) {
148 bool found_fu
= false;
149 unsigned int fu_index
= 0;
151 while (fu_index
< numFuncUnits
&& !found_fu
)
153 if (funcUnits
[fu_index
]->provides(
154 static_cast<OpClass
>(op_class
)))
162 warn("No functional unit for OpClass %s\n",
163 Enums::OpClassStrings
[op_class
]);
167 /* Per-thread structures */
168 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
169 std::string tid_str
= std::to_string(tid
);
172 inputBuffer
.push_back(
173 InputBuffer
<ForwardInstData
>(
174 name_
+ ".inputBuffer" + tid_str
, "insts",
175 params
.executeInputBufferSize
));
178 scoreboard
.push_back(Scoreboard(name_
+ ".scoreboard" + tid_str
));
180 /* In-flight instruction records */
181 executeInfo
[tid
].inFlightInsts
= new Queue
<QueuedInst
,
182 ReportTraitsAdaptor
<QueuedInst
> >(
183 name_
+ ".inFlightInsts" + tid_str
, "insts", total_slots
);
185 executeInfo
[tid
].inFUMemInsts
= new Queue
<QueuedInst
,
186 ReportTraitsAdaptor
<QueuedInst
> >(
187 name_
+ ".inFUMemInsts" + tid_str
, "insts", total_slots
);
191 const ForwardInstData
*
192 Execute::getInput(ThreadID tid
)
194 /* Get a line from the inputBuffer to work with */
195 if (!inputBuffer
[tid
].empty()) {
196 const ForwardInstData
&head
= inputBuffer
[tid
].front();
198 return (head
.isBubble() ? NULL
: &(inputBuffer
[tid
].front()));
205 Execute::popInput(ThreadID tid
)
207 if (!inputBuffer
[tid
].empty())
208 inputBuffer
[tid
].pop();
210 executeInfo
[tid
].inputIndex
= 0;
214 Execute::tryToBranch(MinorDynInstPtr inst
, Fault fault
, BranchData
&branch
)
216 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
217 const TheISA::PCState
&pc_before
= inst
->pc
;
218 TheISA::PCState target
= thread
->pcState();
220 /* Force a branch for SerializeAfter/SquashAfter instructions
221 * at the end of micro-op sequence when we're not suspended */
222 bool force_branch
= thread
->status() != ThreadContext::Suspended
&&
224 inst
->isLastOpInInst() &&
225 (inst
->staticInst
->isSerializeAfter() ||
226 inst
->staticInst
->isSquashAfter() ||
227 inst
->staticInst
->isIprAccess());
229 DPRINTF(Branch
, "tryToBranch before: %s after: %s%s\n",
230 pc_before
, target
, (force_branch
? " (forcing)" : ""));
232 /* Will we change the PC to something other than the next instruction? */
233 bool must_branch
= pc_before
!= target
||
237 /* The reason for the branch data we're about to generate, set below */
238 BranchData::Reason reason
= BranchData::NoBranch
;
240 if (fault
== NoFault
)
242 TheISA::advancePC(target
, inst
->staticInst
);
243 thread
->pcState(target
);
245 DPRINTF(Branch
, "Advancing current PC from: %s to: %s\n",
249 if (inst
->predictedTaken
&& !force_branch
) {
250 /* Predicted to branch */
252 /* No branch was taken, change stream to get us back to the
253 * intended PC value */
254 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x but"
255 " none happened inst: %s\n",
256 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
258 reason
= BranchData::BadlyPredictedBranch
;
259 } else if (inst
->predictedTarget
== target
) {
260 /* Branch prediction got the right target, kill the branch and
262 * Note that this information to the branch predictor might get
263 * overwritten by a "real" branch during this cycle */
264 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x correctly"
266 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(), *inst
);
268 reason
= BranchData::CorrectlyPredictedBranch
;
270 /* Branch prediction got the wrong target */
271 DPRINTF(Branch
, "Predicted a branch from 0x%x to 0x%x"
272 " but got the wrong target (actual: 0x%x) inst: %s\n",
273 inst
->pc
.instAddr(), inst
->predictedTarget
.instAddr(),
274 target
.instAddr(), *inst
);
276 reason
= BranchData::BadlyPredictedBranchTarget
;
278 } else if (must_branch
) {
279 /* Unpredicted branch */
280 DPRINTF(Branch
, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
281 inst
->pc
.instAddr(), target
.instAddr(), *inst
);
283 reason
= BranchData::UnpredictedBranch
;
285 /* No branch at all */
286 reason
= BranchData::NoBranch
;
289 updateBranchData(inst
->id
.threadId
, reason
, inst
, target
, branch
);
293 Execute::updateBranchData(
295 BranchData::Reason reason
,
296 MinorDynInstPtr inst
, const TheISA::PCState
&target
,
299 if (reason
!= BranchData::NoBranch
) {
300 /* Bump up the stream sequence number on a real branch*/
301 if (BranchData::isStreamChange(reason
))
302 executeInfo
[tid
].streamSeqNum
++;
304 /* Branches (even mis-predictions) don't change the predictionSeqNum,
305 * just the streamSeqNum */
306 branch
= BranchData(reason
, tid
,
307 executeInfo
[tid
].streamSeqNum
,
308 /* Maintaining predictionSeqNum if there's no inst is just a
309 * courtesy and looks better on minorview */
310 (inst
->isBubble() ? executeInfo
[tid
].lastPredictionSeqNum
311 : inst
->id
.predictionSeqNum
),
314 DPRINTF(Branch
, "Branch data signalled: %s\n", branch
);
319 Execute::handleMemResponse(MinorDynInstPtr inst
,
320 LSQ::LSQRequestPtr response
, BranchData
&branch
, Fault
&fault
)
322 ThreadID thread_id
= inst
->id
.threadId
;
323 ThreadContext
*thread
= cpu
.getContext(thread_id
);
325 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
327 PacketPtr packet
= response
->packet
;
329 bool is_load
= inst
->staticInst
->isLoad();
330 bool is_store
= inst
->staticInst
->isStore();
331 bool is_atomic
= inst
->staticInst
->isAtomic();
332 bool is_prefetch
= inst
->staticInst
->isDataPrefetch();
334 /* If true, the trace's predicate value will be taken from the exec
335 * context predicate, otherwise, it will be set to false */
336 bool use_context_predicate
= true;
338 if (inst
->translationFault
!= NoFault
) {
339 /* Invoke memory faults. */
340 DPRINTF(MinorMem
, "Completing fault from DTLB access: %s\n",
341 inst
->translationFault
->name());
343 if (inst
->staticInst
->isPrefetch()) {
344 DPRINTF(MinorMem
, "Not taking fault on prefetch: %s\n",
345 inst
->translationFault
->name());
347 /* Don't assign to fault */
349 /* Take the fault raised during the TLB/memory access */
350 fault
= inst
->translationFault
;
352 fault
->invoke(thread
, inst
->staticInst
);
354 } else if (!packet
) {
355 DPRINTF(MinorMem
, "Completing failed request inst: %s\n",
357 use_context_predicate
= false;
358 if (!context
.readMemAccPredicate())
359 inst
->staticInst
->completeAcc(nullptr, &context
, inst
->traceData
);
360 } else if (packet
->isError()) {
361 DPRINTF(MinorMem
, "Trying to commit error response: %s\n",
364 fatal("Received error response packet for inst: %s\n", *inst
);
365 } else if (is_store
|| is_load
|| is_prefetch
|| is_atomic
) {
368 DPRINTF(MinorMem
, "Memory response inst: %s addr: 0x%x size: %d\n",
369 *inst
, packet
->getAddr(), packet
->getSize());
371 if (is_load
&& packet
->getSize() > 0) {
372 DPRINTF(MinorMem
, "Memory data[0]: 0x%x\n",
373 static_cast<unsigned int>(packet
->getConstPtr
<uint8_t>()[0]));
376 /* Complete the memory access instruction */
377 fault
= inst
->staticInst
->completeAcc(packet
, &context
,
380 if (fault
!= NoFault
) {
381 /* Invoke fault created by instruction completion */
382 DPRINTF(MinorMem
, "Fault in memory completeAcc: %s\n",
384 fault
->invoke(thread
, inst
->staticInst
);
386 /* Stores need to be pushed into the store buffer to finish
388 if (response
->needsToBeSentToStoreBuffer())
389 lsq
.sendStoreToStoreBuffer(response
);
392 fatal("There should only ever be reads, "
393 "writes or faults at this point\n");
396 lsq
.popResponse(response
);
398 if (inst
->traceData
) {
399 inst
->traceData
->setPredicate((use_context_predicate
?
400 context
.readPredicate() : false));
403 doInstCommitAccounting(inst
);
405 /* Generate output to account for branches */
406 tryToBranch(inst
, fault
, branch
);
410 Execute::isInterrupted(ThreadID thread_id
) const
412 return cpu
.checkInterrupts(cpu
.getContext(thread_id
));
416 Execute::takeInterrupt(ThreadID thread_id
, BranchData
&branch
)
418 DPRINTF(MinorInterrupt
, "Considering interrupt status from PC: %s\n",
419 cpu
.getContext(thread_id
)->pcState());
421 Fault interrupt
= cpu
.getInterruptController(thread_id
)->getInterrupt
422 (cpu
.getContext(thread_id
));
424 if (interrupt
!= NoFault
) {
425 /* The interrupt *must* set pcState */
426 cpu
.getInterruptController(thread_id
)->updateIntrInfo
427 (cpu
.getContext(thread_id
));
428 interrupt
->invoke(cpu
.getContext(thread_id
));
430 assert(!lsq
.accessesInFlight());
432 DPRINTF(MinorInterrupt
, "Invoking interrupt: %s to PC: %s\n",
433 interrupt
->name(), cpu
.getContext(thread_id
)->pcState());
435 /* Assume that an interrupt *must* cause a branch. Assert this? */
437 updateBranchData(thread_id
, BranchData::Interrupt
,
438 MinorDynInst::bubble(), cpu
.getContext(thread_id
)->pcState(),
442 return interrupt
!= NoFault
;
446 Execute::executeMemRefInst(MinorDynInstPtr inst
, BranchData
&branch
,
447 bool &passed_predicate
, Fault
&fault
)
451 /* Set to true if the mem op. is issued and sent to the mem system */
452 passed_predicate
= false;
454 if (!lsq
.canRequest()) {
455 /* Not acting on instruction yet as the memory
459 ThreadContext
*thread
= cpu
.getContext(inst
->id
.threadId
);
460 TheISA::PCState old_pc
= thread
->pcState();
462 ExecContext
context(cpu
, *cpu
.threads
[inst
->id
.threadId
],
465 DPRINTF(MinorExecute
, "Initiating memRef inst: %s\n", *inst
);
467 Fault init_fault
= inst
->staticInst
->initiateAcc(&context
,
471 if (init_fault
!= NoFault
) {
472 assert(inst
->translationFault
!= NoFault
);
473 // Translation faults are dealt with in handleMemResponse()
474 init_fault
= NoFault
;
476 // If we have a translation fault then it got suppressed by
478 inst
->translationFault
= NoFault
;
482 if (init_fault
!= NoFault
) {
483 DPRINTF(MinorExecute
, "Fault on memory inst: %s"
484 " initiateAcc: %s\n", *inst
, init_fault
->name());
487 /* Only set this if the instruction passed its
489 if (!context
.readMemAccPredicate()) {
490 DPRINTF(MinorMem
, "No memory access for inst: %s\n", *inst
);
491 assert(context
.readPredicate());
493 passed_predicate
= context
.readPredicate();
495 /* Set predicate in tracing */
497 inst
->traceData
->setPredicate(passed_predicate
);
499 /* If the instruction didn't pass its predicate
500 * or it is a predicated vector instruction and the
501 * associated predicate register is all-false (and so will not
502 * progress from here) Try to branch to correct and branch
505 /* Leave it up to commit to handle the fault */
506 lsq
.pushFailedRequest(inst
);
511 /* Restore thread PC */
512 thread
->pcState(old_pc
);
519 /** Increment a cyclic buffer index for indices [0, cycle_size-1] */
521 cyclicIndexInc(unsigned int index
, unsigned int cycle_size
)
523 unsigned int ret
= index
+ 1;
525 if (ret
== cycle_size
)
531 /** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
533 cyclicIndexDec(unsigned int index
, unsigned int cycle_size
)
538 ret
= cycle_size
- 1;
544 Execute::issue(ThreadID thread_id
)
546 const ForwardInstData
*insts_in
= getInput(thread_id
);
547 ExecuteThreadInfo
&thread
= executeInfo
[thread_id
];
549 /* Early termination if we have no instructions */
553 /* Start from the first FU */
554 unsigned int fu_index
= 0;
556 /* Remains true while instructions are still being issued. If any
557 * instruction fails to issue, this is set to false and we exit issue.
558 * This strictly enforces in-order issue. For other issue behaviours,
559 * a more complicated test in the outer while loop below is needed. */
562 /* Number of insts issues this cycle to check for issueLimit */
563 unsigned num_insts_issued
= 0;
565 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
566 unsigned num_mem_insts_issued
= 0;
568 /* Number of instructions discarded this cycle in order to enforce a
569 * discardLimit. @todo, add that parameter? */
570 unsigned num_insts_discarded
= 0;
573 MinorDynInstPtr inst
= insts_in
->insts
[thread
.inputIndex
];
574 Fault fault
= inst
->fault
;
575 bool discarded
= false;
576 bool issued_mem_ref
= false;
578 if (inst
->isBubble()) {
581 } else if (cpu
.getContext(thread_id
)->status() ==
582 ThreadContext::Suspended
)
584 DPRINTF(MinorExecute
, "Discarding inst: %s from suspended"
589 } else if (inst
->id
.streamSeqNum
!= thread
.streamSeqNum
) {
590 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
591 " state was unexpected, expected: %d\n",
592 *inst
, thread
.streamSeqNum
);
596 /* Try and issue an instruction into an FU, assume we didn't and
597 * fix that in the loop */
600 /* Try FU from 0 each instruction */
603 /* Try and issue a single instruction stepping through the
606 FUPipeline
*fu
= funcUnits
[fu_index
];
608 DPRINTF(MinorExecute
, "Trying to issue inst: %s to FU: %d\n",
611 /* Does the examined fu have the OpClass-related capability
612 * needed to execute this instruction? Faults can always
613 * issue to any FU but probably should just 'live' in the
614 * inFlightInsts queue rather than having an FU. */
615 bool fu_is_capable
= (!inst
->isFault() ?
616 fu
->provides(inst
->staticInst
->opClass()) : true);
618 if (inst
->isNoCostInst()) {
619 /* Issue free insts. to a fake numbered FU */
620 fu_index
= noCostFUIndex
;
622 /* And start the countdown on activity to allow
623 * this instruction to get to the end of its FU */
624 cpu
.activityRecorder
->activity();
626 /* Mark the destinations for this instruction as
628 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
629 Cycles(0), cpu
.getContext(thread_id
), false);
631 DPRINTF(MinorExecute
, "Issuing %s to %d\n", inst
->id
, noCostFUIndex
);
632 inst
->fuIndex
= noCostFUIndex
;
633 inst
->extraCommitDelay
= Cycles(0);
634 inst
->extraCommitDelayExpr
= NULL
;
636 /* Push the instruction onto the inFlight queue so
637 * it can be committed in order */
638 QueuedInst
fu_inst(inst
);
639 thread
.inFlightInsts
->push(fu_inst
);
643 } else if (!fu_is_capable
|| fu
->alreadyPushed()) {
645 if (!fu_is_capable
) {
646 DPRINTF(MinorExecute
, "Can't issue as FU: %d isn't"
647 " capable\n", fu_index
);
649 DPRINTF(MinorExecute
, "Can't issue as FU: %d is"
650 " already busy\n", fu_index
);
652 } else if (fu
->stalled
) {
653 DPRINTF(MinorExecute
, "Can't issue inst: %s into FU: %d,"
656 } else if (!fu
->canInsert()) {
657 DPRINTF(MinorExecute
, "Can't issue inst: %s to busy FU"
658 " for another: %d cycles\n",
659 *inst
, fu
->cyclesBeforeInsert());
661 MinorFUTiming
*timing
= (!inst
->isFault() ?
662 fu
->findTiming(inst
->staticInst
) : NULL
);
664 const std::vector
<Cycles
> *src_latencies
=
665 (timing
? &(timing
->srcRegsRelativeLats
)
668 const std::vector
<bool> *cant_forward_from_fu_indices
=
669 &(fu
->cantForwardFromFUIndices
);
671 if (timing
&& timing
->suppress
) {
672 DPRINTF(MinorExecute
, "Can't issue inst: %s as extra"
673 " decoding is suppressing it\n",
675 } else if (!scoreboard
[thread_id
].canInstIssue(inst
,
676 src_latencies
, cant_forward_from_fu_indices
,
677 cpu
.curCycle(), cpu
.getContext(thread_id
)))
679 DPRINTF(MinorExecute
, "Can't issue inst: %s yet\n",
682 /* Can insert the instruction into this FU */
683 DPRINTF(MinorExecute
, "Issuing inst: %s"
684 " into FU %d\n", *inst
,
687 Cycles extra_dest_retire_lat
= Cycles(0);
688 TimingExpr
*extra_dest_retire_lat_expr
= NULL
;
689 Cycles extra_assumed_lat
= Cycles(0);
691 /* Add the extraCommitDelay and extraAssumeLat to
692 * the FU pipeline timings */
694 extra_dest_retire_lat
=
695 timing
->extraCommitLat
;
696 extra_dest_retire_lat_expr
=
697 timing
->extraCommitLatExpr
;
699 timing
->extraAssumedLat
;
702 issued_mem_ref
= inst
->isMemRef();
704 QueuedInst
fu_inst(inst
);
706 /* Decorate the inst with FU details */
707 inst
->fuIndex
= fu_index
;
708 inst
->extraCommitDelay
= extra_dest_retire_lat
;
709 inst
->extraCommitDelayExpr
=
710 extra_dest_retire_lat_expr
;
712 if (issued_mem_ref
) {
713 /* Remember which instruction this memory op
714 * depends on so that initiateAcc can be called
716 if (allowEarlyMemIssue
) {
717 inst
->instToWaitFor
=
718 scoreboard
[thread_id
].execSeqNumToWaitFor(inst
,
719 cpu
.getContext(thread_id
));
721 if (lsq
.getLastMemBarrier(thread_id
) >
724 DPRINTF(MinorExecute
, "A barrier will"
725 " cause a delay in mem ref issue of"
726 " inst: %s until after inst"
727 " %d(exec)\n", *inst
,
728 lsq
.getLastMemBarrier(thread_id
));
730 inst
->instToWaitFor
=
731 lsq
.getLastMemBarrier(thread_id
);
733 DPRINTF(MinorExecute
, "Memory ref inst:"
734 " %s must wait for inst %d(exec)"
736 *inst
, inst
->instToWaitFor
);
739 inst
->canEarlyIssue
= true;
741 /* Also queue this instruction in the memory ref
742 * queue to ensure in-order issue to the LSQ */
743 DPRINTF(MinorExecute
, "Pushing mem inst: %s\n",
745 thread
.inFUMemInsts
->push(fu_inst
);
750 /* And start the countdown on activity to allow
751 * this instruction to get to the end of its FU */
752 cpu
.activityRecorder
->activity();
754 /* Mark the destinations for this instruction as
756 scoreboard
[thread_id
].markupInstDests(inst
, cpu
.curCycle() +
757 fu
->description
.opLat
+
758 extra_dest_retire_lat
+
760 cpu
.getContext(thread_id
),
761 issued_mem_ref
&& extra_assumed_lat
== Cycles(0));
763 /* Push the instruction onto the inFlight queue so
764 * it can be committed in order */
765 thread
.inFlightInsts
->push(fu_inst
);
772 } while (fu_index
!= numFuncUnits
&& !issued
);
775 DPRINTF(MinorExecute
, "Didn't issue inst: %s\n", *inst
);
779 /* Generate MinorTrace's MinorInst lines. Do this at commit
780 * to allow better instruction annotation? */
781 if (DTRACE(MinorTrace
) && !inst
->isBubble())
782 inst
->minorTraceInst(*this);
784 /* Mark up barriers in the LSQ */
785 if (!discarded
&& inst
->isInst() &&
786 inst
->staticInst
->isMemBarrier())
788 DPRINTF(MinorMem
, "Issuing memory barrier inst: %s\n", *inst
);
789 lsq
.issuedMemBarrierInst(inst
);
792 if (inst
->traceData
&& setTraceTimeOnIssue
) {
793 inst
->traceData
->setWhen(curTick());
797 num_mem_insts_issued
++;
800 num_insts_discarded
++;
801 } else if (!inst
->isBubble()) {
804 if (num_insts_issued
== issueLimit
)
805 DPRINTF(MinorExecute
, "Reached inst issue limit\n");
809 DPRINTF(MinorExecute
, "Stepping to next inst inputIndex: %d\n",
813 /* Got to the end of a line */
814 if (thread
.inputIndex
== insts_in
->width()) {
816 /* Set insts_in to null to force us to leave the surrounding
820 if (processMoreThanOneInput
) {
821 DPRINTF(MinorExecute
, "Wrapping\n");
822 insts_in
= getInput(thread_id
);
825 } while (insts_in
&& thread
.inputIndex
< insts_in
->width() &&
826 /* We still have instructions */
827 fu_index
!= numFuncUnits
&& /* Not visited all FUs */
828 issued
&& /* We've not yet failed to issue an instruction */
829 num_insts_issued
!= issueLimit
&& /* Still allowed to issue */
830 num_mem_insts_issued
!= memoryIssueLimit
);
832 return num_insts_issued
;
836 Execute::tryPCEvents(ThreadID thread_id
)
838 ThreadContext
*thread
= cpu
.getContext(thread_id
);
839 unsigned int num_pc_event_checks
= 0;
841 /* Handle PC events on instructions */
844 oldPC
= thread
->instAddr();
845 cpu
.threads
[thread_id
]->pcEventQueue
.service(oldPC
, thread
);
846 num_pc_event_checks
++;
847 } while (oldPC
!= thread
->instAddr());
849 if (num_pc_event_checks
> 1) {
850 DPRINTF(PCEvent
, "Acting on PC Event to PC: %s\n",
854 return num_pc_event_checks
> 1;
858 Execute::doInstCommitAccounting(MinorDynInstPtr inst
)
860 assert(!inst
->isFault());
862 MinorThread
*thread
= cpu
.threads
[inst
->id
.threadId
];
864 /* Increment the many and various inst and op counts in the
865 * thread and system */
866 if (!inst
->staticInst
->isMicroop() || inst
->staticInst
->isLastMicroop())
870 cpu
.stats
.numInsts
++;
871 cpu
.system
->totalNumInsts
++;
873 /* Act on events related to instruction counts */
874 thread
->comInstEventQueue
.serviceEvents(thread
->numInst
);
879 cpu
.stats
.committedInstType
[inst
->id
.threadId
]
880 [inst
->staticInst
->opClass()]++;
882 /* Set the CP SeqNum to the numOps commit number */
884 inst
->traceData
->setCPSeq(thread
->numOp
);
886 cpu
.probeInstCommit(inst
->staticInst
, inst
->pc
.instAddr());
890 Execute::commitInst(MinorDynInstPtr inst
, bool early_memory_issue
,
891 BranchData
&branch
, Fault
&fault
, bool &committed
,
892 bool &completed_mem_issue
)
894 ThreadID thread_id
= inst
->id
.threadId
;
895 ThreadContext
*thread
= cpu
.getContext(thread_id
);
897 bool completed_inst
= true;
900 /* Is the thread for this instruction suspended? In that case, just
901 * stall as long as there are no pending interrupts */
902 if (thread
->status() == ThreadContext::Suspended
&&
903 !isInterrupted(thread_id
))
905 panic("We should never hit the case where we try to commit from a "
906 "suspended thread as the streamSeqNum should not match");
907 } else if (inst
->isFault()) {
908 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
910 DPRINTF(MinorExecute
, "Fault inst reached Execute: %s\n",
911 inst
->fault
->name());
914 inst
->fault
->invoke(thread
, NULL
);
916 tryToBranch(inst
, fault
, branch
);
917 } else if (inst
->staticInst
->isMemRef()) {
918 /* Memory accesses are executed in two parts:
919 * executeMemRefInst -- calculates the EA and issues the access
920 * to memory. This is done here.
921 * handleMemResponse -- handles the response packet, done by
924 * While the memory access is in its FU, the EA is being
925 * calculated. At the end of the FU, when it is ready to
926 * 'commit' (in this function), the access is presented to the
927 * memory queues. When a response comes back from memory,
928 * Execute::commit will commit it.
930 bool predicate_passed
= false;
931 bool completed_mem_inst
= executeMemRefInst(inst
, branch
,
932 predicate_passed
, fault
);
934 if (completed_mem_inst
&& fault
!= NoFault
) {
935 if (early_memory_issue
) {
936 DPRINTF(MinorExecute
, "Fault in early executing inst: %s\n",
938 /* Don't execute the fault, just stall the instruction
939 * until it gets to the head of inFlightInsts */
940 inst
->canEarlyIssue
= false;
941 /* Not completed as we'll come here again to pick up
942 * the fault when we get to the end of the FU */
943 completed_inst
= false;
945 DPRINTF(MinorExecute
, "Fault in execute: %s\n",
947 fault
->invoke(thread
, NULL
);
949 tryToBranch(inst
, fault
, branch
);
950 completed_inst
= true;
953 completed_inst
= completed_mem_inst
;
955 completed_mem_issue
= completed_inst
;
956 } else if (inst
->isInst() && inst
->staticInst
->isMemBarrier() &&
957 !lsq
.canPushIntoStoreBuffer())
959 DPRINTF(MinorExecute
, "Can't commit data barrier inst: %s yet as"
960 " there isn't space in the store buffer\n", *inst
);
962 completed_inst
= false;
963 } else if (inst
->isInst() && inst
->staticInst
->isQuiesce()
964 && !branch
.isBubble()){
965 /* This instruction can suspend, need to be able to communicate
966 * backwards, so no other branches may evaluate this cycle*/
967 completed_inst
= false;
969 ExecContext
context(cpu
, *cpu
.threads
[thread_id
], *this, inst
);
971 DPRINTF(MinorExecute
, "Committing inst: %s\n", *inst
);
973 fault
= inst
->staticInst
->execute(&context
,
976 /* Set the predicate for tracing and dump */
978 inst
->traceData
->setPredicate(context
.readPredicate());
982 if (fault
!= NoFault
) {
983 DPRINTF(MinorExecute
, "Fault in execute of inst: %s fault: %s\n",
984 *inst
, fault
->name());
985 fault
->invoke(thread
, inst
->staticInst
);
988 doInstCommitAccounting(inst
);
989 tryToBranch(inst
, fault
, branch
);
992 if (completed_inst
) {
993 /* Keep a copy of this instruction's predictionSeqNum just in case
994 * we need to issue a branch without an instruction (such as an
996 executeInfo
[thread_id
].lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
998 /* Check to see if this instruction suspended the current thread. */
999 if (!inst
->isFault() &&
1000 thread
->status() == ThreadContext::Suspended
&&
1001 branch
.isBubble() && /* It didn't branch too */
1002 !isInterrupted(thread_id
)) /* Don't suspend if we have
1005 TheISA::PCState resume_pc
= cpu
.getContext(thread_id
)->pcState();
1007 assert(resume_pc
.microPC() == 0);
1009 DPRINTF(MinorInterrupt
, "Suspending thread: %d from Execute"
1010 " inst: %s\n", thread_id
, *inst
);
1012 cpu
.stats
.numFetchSuspends
++;
1014 updateBranchData(thread_id
, BranchData::SuspendThread
, inst
,
1019 return completed_inst
;
1023 Execute::commit(ThreadID thread_id
, bool only_commit_microops
, bool discard
,
1026 Fault fault
= NoFault
;
1027 Cycles now
= cpu
.curCycle();
1028 ExecuteThreadInfo
&ex_info
= executeInfo
[thread_id
];
1031 * Try and execute as many instructions from the end of FU pipelines as
1032 * possible. This *doesn't* include actually advancing the pipelines.
1034 * We do this by looping on the front of the inFlightInsts queue for as
1035 * long as we can find the desired instruction at the end of the
1036 * functional unit it was issued to without seeing a branch or a fault.
1037 * In this function, these terms are used:
1038 * complete -- The instruction has finished its passage through
1039 * its functional unit and its fate has been decided
1040 * (committed, discarded, issued to the memory system)
1041 * commit -- The instruction is complete(d), not discarded and has
1042 * its effects applied to the CPU state
1043 * discard(ed) -- The instruction is complete but not committed
1044 * as its streamSeqNum disagrees with the current
1045 * Execute::streamSeqNum
1047 * Commits are also possible from two other places:
1049 * 1) Responses returning from the LSQ
1050 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1051 * than their position in the inFlightInsts queue, but after all
1052 * their dependencies are resolved.
1055 /* Has an instruction been completed? Once this becomes false, we stop
1056 * trying to complete instructions. */
1057 bool completed_inst
= true;
1059 /* Number of insts committed this cycle to check against commitLimit */
1060 unsigned int num_insts_committed
= 0;
1062 /* Number of memory access instructions committed to check against
1064 unsigned int num_mem_refs_committed
= 0;
1066 if (only_commit_microops
&& !ex_info
.inFlightInsts
->empty()) {
1067 DPRINTF(MinorInterrupt
, "Only commit microops %s %d\n",
1068 *(ex_info
.inFlightInsts
->front().inst
),
1069 ex_info
.lastCommitWasEndOfMacroop
);
1072 while (!ex_info
.inFlightInsts
->empty() && /* Some more instructions to process */
1073 !branch
.isStreamChange() && /* No real branch */
1074 fault
== NoFault
&& /* No faults */
1075 completed_inst
&& /* Still finding instructions to execute */
1076 num_insts_committed
!= commitLimit
/* Not reached commit limit */
1079 if (only_commit_microops
) {
1080 DPRINTF(MinorInterrupt
, "Committing tail of insts before"
1082 *(ex_info
.inFlightInsts
->front().inst
));
1085 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1087 InstSeqNum head_exec_seq_num
=
1088 head_inflight_inst
->inst
->id
.execSeqNum
;
1090 /* The instruction we actually process if completed_inst
1091 * remains true to the end of the loop body.
1092 * Start by considering the the head of the in flight insts queue */
1093 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1095 bool committed_inst
= false;
1096 bool discard_inst
= false;
1097 bool completed_mem_ref
= false;
1098 bool issued_mem_ref
= false;
1099 bool early_memory_issue
= false;
1101 /* Must set this again to go around the loop */
1102 completed_inst
= false;
1104 /* If we're just completing a macroop before an interrupt or drain,
1105 * can we stil commit another microop (rather than a memory response)
1106 * without crosing into the next full instruction? */
1107 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty() &&
1108 !(only_commit_microops
&& ex_info
.lastCommitWasEndOfMacroop
);
1110 /* Can we find a mem response for this inst */
1111 LSQ::LSQRequestPtr mem_response
=
1112 (inst
->inLSQ
? lsq
.findResponse(inst
) : NULL
);
1114 DPRINTF(MinorExecute
, "Trying to commit canCommitInsts: %d\n",
1117 /* Test for PC events after every instruction */
1118 if (isInbetweenInsts(thread_id
) && tryPCEvents(thread_id
)) {
1119 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1121 /* Branch as there was a change in PC */
1122 updateBranchData(thread_id
, BranchData::UnpredictedBranch
,
1123 MinorDynInst::bubble(), thread
->pcState(), branch
);
1124 } else if (mem_response
&&
1125 num_mem_refs_committed
< memoryCommitLimit
)
1127 /* Try to commit from the memory responses next */
1128 discard_inst
= inst
->id
.streamSeqNum
!=
1129 ex_info
.streamSeqNum
|| discard
;
1131 DPRINTF(MinorExecute
, "Trying to commit mem response: %s\n",
1134 /* Complete or discard the response */
1136 DPRINTF(MinorExecute
, "Discarding mem inst: %s as its"
1137 " stream state was unexpected, expected: %d\n",
1138 *inst
, ex_info
.streamSeqNum
);
1140 lsq
.popResponse(mem_response
);
1142 handleMemResponse(inst
, mem_response
, branch
, fault
);
1143 committed_inst
= true;
1146 completed_mem_ref
= true;
1147 completed_inst
= true;
1148 } else if (can_commit_insts
) {
1149 /* If true, this instruction will, subject to timing tweaks,
1150 * be considered for completion. try_to_commit flattens
1151 * the `if' tree a bit and allows other tests for inst
1152 * commit to be inserted here. */
1153 bool try_to_commit
= false;
1155 /* Try and issue memory ops early if they:
1156 * - Can push a request into the LSQ
1157 * - Have reached the end of their FUs
1158 * - Have had all their dependencies satisfied
1159 * - Are from the right stream
1161 * For any other case, leave it to the normal instruction
1162 * issue below to handle them.
1164 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1165 DPRINTF(MinorExecute
, "Trying to commit from mem FUs\n");
1167 const MinorDynInstPtr head_mem_ref_inst
=
1168 ex_info
.inFUMemInsts
->front().inst
;
1169 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1170 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1172 /* Use this, possibly out of order, inst as the one
1173 * to 'commit'/send to the LSQ */
1174 if (!fu_inst
->isBubble() &&
1176 fu_inst
->canEarlyIssue
&&
1177 ex_info
.streamSeqNum
== fu_inst
->id
.streamSeqNum
&&
1178 head_exec_seq_num
> fu_inst
->instToWaitFor
)
1180 DPRINTF(MinorExecute
, "Issuing mem ref early"
1181 " inst: %s instToWaitFor: %d\n",
1182 *(fu_inst
), fu_inst
->instToWaitFor
);
1185 try_to_commit
= true;
1186 early_memory_issue
= true;
1187 completed_inst
= true;
1191 /* Try and commit FU-less insts */
1192 if (!completed_inst
&& inst
->isNoCostInst()) {
1193 DPRINTF(MinorExecute
, "Committing no cost inst: %s", *inst
);
1195 try_to_commit
= true;
1196 completed_inst
= true;
1199 /* Try to issue from the ends of FUs and the inFlightInsts
1201 if (!completed_inst
&& !inst
->inLSQ
) {
1202 DPRINTF(MinorExecute
, "Trying to commit from FUs\n");
1204 /* Try to commit from a functional unit */
1205 /* Is the head inst of the expected inst's FU actually the
1207 QueuedInst
&fu_inst
=
1208 funcUnits
[inst
->fuIndex
]->front();
1209 InstSeqNum fu_inst_seq_num
= fu_inst
.inst
->id
.execSeqNum
;
1211 if (fu_inst
.inst
->isBubble()) {
1212 /* No instruction ready */
1213 completed_inst
= false;
1214 } else if (fu_inst_seq_num
!= head_exec_seq_num
) {
1215 /* Past instruction: we must have already executed it
1216 * in the same cycle and so the head inst isn't
1217 * actually at the end of its pipeline
1218 * Future instruction: handled above and only for
1219 * mem refs on their way to the LSQ */
1220 } else if (fu_inst
.inst
->id
== inst
->id
) {
1221 /* All instructions can be committed if they have the
1222 * right execSeqNum and there are no in-flight
1223 * mem insts before us */
1224 try_to_commit
= true;
1225 completed_inst
= true;
1229 if (try_to_commit
) {
1230 discard_inst
= inst
->id
.streamSeqNum
!=
1231 ex_info
.streamSeqNum
|| discard
;
1233 /* Is this instruction discardable as its streamSeqNum
1235 if (!discard_inst
) {
1236 /* Try to commit or discard a non-memory instruction.
1237 * Memory ops are actually 'committed' from this FUs
1238 * and 'issued' into the memory system so we need to
1239 * account for them later (commit_was_mem_issue gets
1241 if (inst
->extraCommitDelayExpr
) {
1242 DPRINTF(MinorExecute
, "Evaluating expression for"
1243 " extra commit delay inst: %s\n", *inst
);
1245 ThreadContext
*thread
= cpu
.getContext(thread_id
);
1247 TimingExprEvalContext
context(inst
->staticInst
,
1250 uint64_t extra_delay
= inst
->extraCommitDelayExpr
->
1253 DPRINTF(MinorExecute
, "Extra commit delay expr"
1254 " result: %d\n", extra_delay
);
1256 if (extra_delay
< 128) {
1257 inst
->extraCommitDelay
+= Cycles(extra_delay
);
1259 DPRINTF(MinorExecute
, "Extra commit delay was"
1260 " very long: %d\n", extra_delay
);
1262 inst
->extraCommitDelayExpr
= NULL
;
1265 /* Move the extraCommitDelay from the instruction
1266 * into the minimumCommitCycle */
1267 if (inst
->extraCommitDelay
!= Cycles(0)) {
1268 inst
->minimumCommitCycle
= cpu
.curCycle() +
1269 inst
->extraCommitDelay
;
1270 inst
->extraCommitDelay
= Cycles(0);
1273 /* @todo Think about making lastMemBarrier be
1274 * MAX_UINT_64 to avoid using 0 as a marker value */
1275 if (!inst
->isFault() && inst
->isMemRef() &&
1276 lsq
.getLastMemBarrier(thread_id
) <
1277 inst
->id
.execSeqNum
&&
1278 lsq
.getLastMemBarrier(thread_id
) != 0)
1280 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1281 " as there are incomplete barriers in flight\n",
1283 completed_inst
= false;
1284 } else if (inst
->minimumCommitCycle
> now
) {
1285 DPRINTF(MinorExecute
, "Not committing inst: %s yet"
1286 " as it wants to be stalled for %d more cycles\n",
1287 *inst
, inst
->minimumCommitCycle
- now
);
1288 completed_inst
= false;
1290 completed_inst
= commitInst(inst
,
1291 early_memory_issue
, branch
, fault
,
1292 committed_inst
, issued_mem_ref
);
1295 /* Discard instruction */
1296 completed_inst
= true;
1299 if (completed_inst
) {
1300 /* Allow the pipeline to advance. If the FU head
1301 * instruction wasn't the inFlightInsts head
1302 * but had already been committed, it would have
1303 * unstalled the pipeline before here */
1304 if (inst
->fuIndex
!= noCostFUIndex
) {
1305 DPRINTF(MinorExecute
, "Unstalling %d for inst %s\n", inst
->fuIndex
, inst
->id
);
1306 funcUnits
[inst
->fuIndex
]->stalled
= false;
1311 DPRINTF(MinorExecute
, "No instructions to commit\n");
1312 completed_inst
= false;
1315 /* All discardable instructions must also be 'completed' by now */
1316 assert(!(discard_inst
&& !completed_inst
));
1318 /* Instruction committed but was discarded due to streamSeqNum
1321 DPRINTF(MinorExecute
, "Discarding inst: %s as its stream"
1322 " state was unexpected, expected: %d\n",
1323 *inst
, ex_info
.streamSeqNum
);
1325 if (fault
== NoFault
)
1326 cpu
.stats
.numDiscardedOps
++;
1329 /* Mark the mem inst as being in the LSQ */
1330 if (issued_mem_ref
) {
1335 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1336 * as they've *definitely* exited the FUs */
1337 if (completed_inst
&& inst
->isMemRef()) {
1338 /* The MemRef could have been discarded from the FU or the memory
1339 * queue, so just check an FU instruction */
1340 if (!ex_info
.inFUMemInsts
->empty() &&
1341 ex_info
.inFUMemInsts
->front().inst
== inst
)
1343 ex_info
.inFUMemInsts
->pop();
1347 if (completed_inst
&& !(issued_mem_ref
&& fault
== NoFault
)) {
1348 /* Note that this includes discarded insts */
1349 DPRINTF(MinorExecute
, "Completed inst: %s\n", *inst
);
1351 /* Got to the end of a full instruction? */
1352 ex_info
.lastCommitWasEndOfMacroop
= inst
->isFault() ||
1353 inst
->isLastOpInInst();
1355 /* lastPredictionSeqNum is kept as a convenience to prevent its
1356 * value from changing too much on the minorview display */
1357 ex_info
.lastPredictionSeqNum
= inst
->id
.predictionSeqNum
;
1359 /* Finished with the inst, remove it from the inst queue and
1360 * clear its dependencies */
1361 ex_info
.inFlightInsts
->pop();
1363 /* Complete barriers in the LSQ/move to store buffer */
1364 if (inst
->isInst() && inst
->staticInst
->isMemBarrier()) {
1365 DPRINTF(MinorMem
, "Completing memory barrier"
1366 " inst: %s committed: %d\n", *inst
, committed_inst
);
1367 lsq
.completeMemBarrierInst(inst
, committed_inst
);
1370 scoreboard
[thread_id
].clearInstDests(inst
, inst
->isMemRef());
1373 /* Handle per-cycle instruction counting */
1374 if (committed_inst
) {
1375 bool is_no_cost_inst
= inst
->isNoCostInst();
1377 /* Don't show no cost instructions as having taken a commit
1379 if (DTRACE(MinorTrace
) && !is_no_cost_inst
)
1380 ex_info
.instsBeingCommitted
.insts
[num_insts_committed
] = inst
;
1382 if (!is_no_cost_inst
)
1383 num_insts_committed
++;
1385 if (num_insts_committed
== commitLimit
)
1386 DPRINTF(MinorExecute
, "Reached inst commit limit\n");
1388 /* Re-set the time of the instruction if that's required for
1390 if (inst
->traceData
) {
1391 if (setTraceTimeOnCommit
)
1392 inst
->traceData
->setWhen(curTick());
1393 inst
->traceData
->dump();
1396 if (completed_mem_ref
)
1397 num_mem_refs_committed
++;
1399 if (num_mem_refs_committed
== memoryCommitLimit
)
1400 DPRINTF(MinorExecute
, "Reached mem ref commit limit\n");
1406 Execute::isInbetweenInsts(ThreadID thread_id
) const
1408 return executeInfo
[thread_id
].lastCommitWasEndOfMacroop
&&
1409 !lsq
.accessesInFlight();
1415 if (!inp
.outputWire
->isBubble())
1416 inputBuffer
[inp
.outputWire
->threadId
].setTail(*inp
.outputWire
);
1418 BranchData
&branch
= *out
.inputWire
;
1420 unsigned int num_issued
= 0;
1422 /* Do all the cycle-wise activities for dcachePort here to potentially
1423 * free up input spaces in the LSQ's requests queue */
1426 /* Check interrupts first. Will halt commit if interrupt found */
1427 bool interrupted
= false;
1428 ThreadID interrupt_tid
= checkInterrupts(branch
, interrupted
);
1430 if (interrupt_tid
!= InvalidThreadID
) {
1431 /* Signalling an interrupt this cycle, not issuing/committing from
1432 * any other threads */
1433 } else if (!branch
.isBubble()) {
1434 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1435 * without overwriting them */
1436 DPRINTF(MinorInterrupt
, "Execute skipping a cycle to allow old"
1437 " branch to complete\n");
1439 ThreadID commit_tid
= getCommittingThread();
1441 if (commit_tid
!= InvalidThreadID
) {
1442 ExecuteThreadInfo
& commit_info
= executeInfo
[commit_tid
];
1444 DPRINTF(MinorExecute
, "Attempting to commit [tid:%d]\n",
1446 /* commit can set stalled flags observable to issue and so *must* be
1448 if (commit_info
.drainState
!= NotDraining
) {
1449 if (commit_info
.drainState
== DrainCurrentInst
) {
1450 /* Commit only micro-ops, don't kill anything else */
1451 commit(commit_tid
, true, false, branch
);
1453 if (isInbetweenInsts(commit_tid
))
1454 setDrainState(commit_tid
, DrainHaltFetch
);
1456 /* Discard any generated branch */
1457 branch
= BranchData::bubble();
1458 } else if (commit_info
.drainState
== DrainAllInsts
) {
1459 /* Kill all instructions */
1460 while (getInput(commit_tid
))
1461 popInput(commit_tid
);
1462 commit(commit_tid
, false, true, branch
);
1465 /* Commit micro-ops only if interrupted. Otherwise, commit
1466 * anything you like */
1467 DPRINTF(MinorExecute
, "Committing micro-ops for interrupt[tid:%d]\n",
1469 bool only_commit_microops
= interrupted
&&
1470 hasInterrupt(commit_tid
);
1471 commit(commit_tid
, only_commit_microops
, false, branch
);
1474 /* Halt fetch, but don't do it until we have the current instruction in
1476 if (commit_info
.drainState
== DrainHaltFetch
) {
1477 updateBranchData(commit_tid
, BranchData::HaltFetch
,
1478 MinorDynInst::bubble(), TheISA::PCState(0), branch
);
1480 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1481 setDrainState(commit_tid
, DrainAllInsts
);
1484 ThreadID issue_tid
= getIssuingThread();
1485 /* This will issue merrily even when interrupted in the sure and
1486 * certain knowledge that the interrupt with change the stream */
1487 if (issue_tid
!= InvalidThreadID
) {
1488 DPRINTF(MinorExecute
, "Attempting to issue [tid:%d]\n",
1490 num_issued
= issue(issue_tid
);
1495 /* Run logic to step functional units + decide if we are active on the next
1497 std::vector
<MinorDynInstPtr
> next_issuable_insts
;
1498 bool can_issue_next
= false;
1500 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1501 /* Find the next issuable instruction for each thread and see if it can
1503 if (getInput(tid
)) {
1504 unsigned int input_index
= executeInfo
[tid
].inputIndex
;
1505 MinorDynInstPtr inst
= getInput(tid
)->insts
[input_index
];
1506 if (inst
->isFault()) {
1507 can_issue_next
= true;
1508 } else if (!inst
->isBubble()) {
1509 next_issuable_insts
.push_back(inst
);
1514 bool becoming_stalled
= true;
1516 /* Advance the pipelines and note whether they still need to be
1518 for (unsigned int i
= 0; i
< numFuncUnits
; i
++) {
1519 FUPipeline
*fu
= funcUnits
[i
];
1522 /* If we need to tick again, the pipeline will have been left or set
1523 * to be unstalled */
1524 if (fu
->occupancy
!=0 && !fu
->stalled
)
1525 becoming_stalled
= false;
1527 /* Could we possibly issue the next instruction from any thread?
1528 * This is quite an expensive test and is only used to determine
1529 * if the CPU should remain active, only run it if we aren't sure
1530 * we are active next cycle yet */
1531 for (auto inst
: next_issuable_insts
) {
1532 if (!fu
->stalled
&& fu
->provides(inst
->staticInst
->opClass()) &&
1533 scoreboard
[inst
->id
.threadId
].canInstIssue(inst
,
1534 NULL
, NULL
, cpu
.curCycle() + Cycles(1),
1535 cpu
.getContext(inst
->id
.threadId
))) {
1536 can_issue_next
= true;
1542 bool head_inst_might_commit
= false;
1544 /* Could the head in flight insts be committed */
1545 for (auto const &info
: executeInfo
) {
1546 if (!info
.inFlightInsts
->empty()) {
1547 const QueuedInst
&head_inst
= info
.inFlightInsts
->front();
1549 if (head_inst
.inst
->isNoCostInst()) {
1550 head_inst_might_commit
= true;
1552 FUPipeline
*fu
= funcUnits
[head_inst
.inst
->fuIndex
];
1554 fu
->front().inst
->id
== head_inst
.inst
->id
) ||
1555 lsq
.findResponse(head_inst
.inst
))
1557 head_inst_might_commit
= true;
1564 DPRINTF(Activity
, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1565 (num_issued
!= 0 ? " (issued some insts)" : ""),
1566 (becoming_stalled
? "(becoming stalled)" : "(not becoming stalled)"),
1567 (can_issue_next
? " (can issued next inst)" : ""),
1568 (head_inst_might_commit
? "(head inst might commit)" : ""),
1569 (lsq
.needsToTick() ? " (LSQ needs to tick)" : ""),
1570 (interrupted
? " (interrupted)" : ""));
1573 num_issued
!= 0 || /* Issued some insts this cycle */
1574 !becoming_stalled
|| /* Some FU pipelines can still move */
1575 can_issue_next
|| /* Can still issue a new inst */
1576 head_inst_might_commit
|| /* Could possible commit the next inst */
1577 lsq
.needsToTick() || /* Must step the dcache port */
1578 interrupted
; /* There are pending interrupts */
1580 if (!need_to_tick
) {
1581 DPRINTF(Activity
, "The next cycle might be skippable as there are no"
1582 " advanceable FUs\n");
1585 /* Wake up if we need to tick again */
1587 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1589 /* Note activity of following buffer */
1590 if (!branch
.isBubble())
1591 cpu
.activityRecorder
->activity();
1593 /* Make sure the input (if any left) is pushed */
1594 if (!inp
.outputWire
->isBubble())
1595 inputBuffer
[inp
.outputWire
->threadId
].pushTail();
1599 Execute::checkInterrupts(BranchData
& branch
, bool& interrupted
)
1601 ThreadID tid
= interruptPriority
;
1602 /* Evaluate interrupts in round-robin based upon service */
1604 /* Has an interrupt been signalled? This may not be acted on
1605 * straighaway so this is different from took_interrupt */
1606 bool thread_interrupted
= false;
1608 if (FullSystem
&& cpu
.getInterruptController(tid
)) {
1609 /* This is here because it seems that after drainResume the
1610 * interrupt controller isn't always set */
1611 thread_interrupted
= executeInfo
[tid
].drainState
== NotDraining
&&
1613 interrupted
= interrupted
|| thread_interrupted
;
1615 DPRINTF(MinorInterrupt
, "No interrupt controller\n");
1617 DPRINTF(MinorInterrupt
, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1618 tid
, thread_interrupted
, isInbetweenInsts(tid
));
1619 /* Act on interrupts */
1620 if (thread_interrupted
&& isInbetweenInsts(tid
)) {
1621 if (takeInterrupt(tid
, branch
)) {
1622 interruptPriority
= tid
;
1626 tid
= (tid
+ 1) % cpu
.numThreads
;
1628 } while (tid
!= interruptPriority
);
1630 return InvalidThreadID
;
1634 Execute::hasInterrupt(ThreadID thread_id
)
1636 if (FullSystem
&& cpu
.getInterruptController(thread_id
)) {
1637 return executeInfo
[thread_id
].drainState
== NotDraining
&&
1638 isInterrupted(thread_id
);
1645 Execute::minorTrace() const
1647 std::ostringstream insts
;
1648 std::ostringstream stalled
;
1650 executeInfo
[0].instsBeingCommitted
.reportData(insts
);
1652 inputBuffer
[0].minorTrace();
1653 scoreboard
[0].minorTrace();
1655 /* Report functional unit stalling in one string */
1657 while (i
< numFuncUnits
)
1659 stalled
<< (funcUnits
[i
]->stalled
? '1' : 'E');
1661 if (i
!= numFuncUnits
)
1665 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1666 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1667 insts
.str(), executeInfo
[0].inputIndex
, executeInfo
[0].streamSeqNum
,
1668 stalled
.str(), executeInfo
[0].drainState
, isInbetweenInsts(0));
1670 std::for_each(funcUnits
.begin(), funcUnits
.end(),
1671 std::mem_fun(&FUPipeline::minorTrace
));
1673 executeInfo
[0].inFlightInsts
->minorTrace();
1674 executeInfo
[0].inFUMemInsts
->minorTrace();
1678 Execute::getCommittingThread()
1680 std::vector
<ThreadID
> priority_list
;
1682 switch (cpu
.threadPolicy
) {
1683 case Enums::SingleThreaded
:
1685 case Enums::RoundRobin
:
1686 priority_list
= cpu
.roundRobinPriority(commitPriority
);
1689 priority_list
= cpu
.randomPriority();
1692 panic("Invalid thread policy");
1695 for (auto tid
: priority_list
) {
1696 ExecuteThreadInfo
&ex_info
= executeInfo
[tid
];
1697 bool can_commit_insts
= !ex_info
.inFlightInsts
->empty();
1698 if (can_commit_insts
) {
1699 QueuedInst
*head_inflight_inst
= &(ex_info
.inFlightInsts
->front());
1700 MinorDynInstPtr inst
= head_inflight_inst
->inst
;
1702 can_commit_insts
= can_commit_insts
&&
1703 (!inst
->inLSQ
|| (lsq
.findResponse(inst
) != NULL
));
1706 bool can_transfer_mem_inst
= false;
1707 if (!ex_info
.inFUMemInsts
->empty() && lsq
.canRequest()) {
1708 const MinorDynInstPtr head_mem_ref_inst
=
1709 ex_info
.inFUMemInsts
->front().inst
;
1710 FUPipeline
*fu
= funcUnits
[head_mem_ref_inst
->fuIndex
];
1711 const MinorDynInstPtr
&fu_inst
= fu
->front().inst
;
1712 can_transfer_mem_inst
=
1713 !fu_inst
->isBubble() &&
1714 fu_inst
->id
.threadId
== tid
&&
1716 fu_inst
->canEarlyIssue
&&
1717 inst
->id
.execSeqNum
> fu_inst
->instToWaitFor
;
1720 bool can_execute_fu_inst
= inst
->fuIndex
== noCostFUIndex
;
1721 if (can_commit_insts
&& !can_transfer_mem_inst
&&
1722 inst
->fuIndex
!= noCostFUIndex
)
1724 QueuedInst
& fu_inst
= funcUnits
[inst
->fuIndex
]->front();
1725 can_execute_fu_inst
= !fu_inst
.inst
->isBubble() &&
1726 fu_inst
.inst
->id
== inst
->id
;
1729 can_commit_insts
= can_commit_insts
&&
1730 (can_transfer_mem_inst
|| can_execute_fu_inst
);
1735 if (can_commit_insts
) {
1736 commitPriority
= tid
;
1741 return InvalidThreadID
;
1745 Execute::getIssuingThread()
1747 std::vector
<ThreadID
> priority_list
;
1749 switch (cpu
.threadPolicy
) {
1750 case Enums::SingleThreaded
:
1752 case Enums::RoundRobin
:
1753 priority_list
= cpu
.roundRobinPriority(issuePriority
);
1756 priority_list
= cpu
.randomPriority();
1759 panic("Invalid thread scheduling policy.");
1762 for (auto tid
: priority_list
) {
1763 if (getInput(tid
)) {
1764 issuePriority
= tid
;
1769 return InvalidThreadID
;
1773 Execute::drainResume()
1775 DPRINTF(Drain
, "MinorExecute drainResume\n");
1777 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1778 setDrainState(tid
, NotDraining
);
1781 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1784 std::ostream
&operator <<(std::ostream
&os
, Execute::DrainState state
)
1788 case Execute::NotDraining
:
1789 os
<< "NotDraining";
1791 case Execute::DrainCurrentInst
:
1792 os
<< "DrainCurrentInst";
1794 case Execute::DrainHaltFetch
:
1795 os
<< "DrainHaltFetch";
1797 case Execute::DrainAllInsts
:
1798 os
<< "DrainAllInsts";
1801 os
<< "Drain-" << static_cast<int>(state
);
1809 Execute::setDrainState(ThreadID thread_id
, DrainState state
)
1811 DPRINTF(Drain
, "setDrainState[%d]: %s\n", thread_id
, state
);
1812 executeInfo
[thread_id
].drainState
= state
;
1818 DPRINTF(Drain
, "MinorExecute drain\n");
1820 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1821 if (executeInfo
[tid
].drainState
== NotDraining
) {
1822 cpu
.wakeupOnEvent(Pipeline::ExecuteStageId
);
1824 /* Go to DrainCurrentInst if we're between microops
1825 * or waiting on an unbufferable memory operation.
1826 * Otherwise we can go straight to DrainHaltFetch
1828 if (isInbetweenInsts(tid
))
1829 setDrainState(tid
, DrainHaltFetch
);
1831 setDrainState(tid
, DrainCurrentInst
);
1834 return (isDrained() ? 0 : 1);
1838 Execute::isDrained()
1840 if (!lsq
.isDrained())
1843 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
1844 if (!inputBuffer
[tid
].empty() ||
1845 !executeInfo
[tid
].inFlightInsts
->empty()) {
1856 for (unsigned int i
= 0; i
< numFuncUnits
; i
++)
1857 delete funcUnits
[i
];
1859 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++)
1860 delete executeInfo
[tid
].inFlightInsts
;
1864 Execute::instIsRightStream(MinorDynInstPtr inst
)
1866 return inst
->id
.streamSeqNum
== executeInfo
[inst
->id
.threadId
].streamSeqNum
;
1870 Execute::instIsHeadInst(MinorDynInstPtr inst
)
1874 if (!executeInfo
[inst
->id
.threadId
].inFlightInsts
->empty())
1875 ret
= executeInfo
[inst
->id
.threadId
].inFlightInsts
->front().inst
->id
== inst
->id
;
1880 MinorCPU::MinorCPUPort
&
1881 Execute::getDcachePort()
1883 return lsq
.getDcachePort();