2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
42 #include "arch/decoder.hh"
43 #include "arch/utility.hh"
44 #include "cpu/minor/fetch2.hh"
45 #include "cpu/minor/pipeline.hh"
46 #include "cpu/pred/bpred_unit.hh"
47 #include "debug/Branch.hh"
48 #include "debug/Fetch.hh"
49 #include "debug/MinorTrace.hh"
54 Fetch2::Fetch2(const std::string
&name
,
56 MinorCPUParams
¶ms
,
57 Latch
<ForwardLineData
>::Output inp_
,
58 Latch
<BranchData
>::Output branchInp_
,
59 Latch
<BranchData
>::Input predictionOut_
,
60 Latch
<ForwardInstData
>::Input out_
,
61 Reservable
&next_stage_input_buffer
) :
65 branchInp(branchInp_
),
66 predictionOut(predictionOut_
),
68 nextStageReserve(next_stage_input_buffer
),
69 outputWidth(params
.decodeInputWidth
),
70 processMoreThanOneInput(params
.fetch2CycleInput
),
71 branchPredictor(*params
.branchPred
),
72 inputBuffer(name
+ ".inputBuffer", "lines", params
.fetch2InputBufferSize
),
74 pc(TheISA::PCState(0)),
76 lastStreamSeqNum(InstId::firstStreamSeqNum
),
77 fetchSeqNum(InstId::firstFetchSeqNum
),
78 expectedStreamSeqNum(InstId::firstStreamSeqNum
),
79 predictionSeqNum(InstId::firstPredictionSeqNum
),
83 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name
, outputWidth
);
85 if (params
.fetch2InputBufferSize
< 1) {
86 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name
,
87 params
.fetch2InputBufferSize
);
91 const ForwardLineData
*
94 /* Get a line from the inputBuffer to work with */
95 if (!inputBuffer
.empty()) {
96 return &(inputBuffer
.front());
105 if (!inputBuffer
.empty()) {
106 inputBuffer
.front().freeLine();
114 Fetch2::dumpAllInput()
116 DPRINTF(Fetch
, "Dumping whole input buffer\n");
117 while (!inputBuffer
.empty())
124 Fetch2::updateBranchPrediction(const BranchData
&branch
)
126 MinorDynInstPtr inst
= branch
.inst
;
128 /* Don't even consider instructions we didn't try to predict or faults */
129 if (inst
->isFault() || !inst
->triedToPredict
)
132 switch (branch
.reason
) {
133 case BranchData::NoBranch
:
134 /* No data to update */
136 case BranchData::Interrupt
:
137 /* Never try to predict interrupts */
139 case BranchData::SuspendThread
:
140 /* Don't need to act on suspends */
142 case BranchData::WakeupFetch
:
143 /* Don't need to act on wakeups, no instruction tied to action. */
145 case BranchData::HaltFetch
:
146 /* Don't need to act on fetch wakeup */
148 case BranchData::BranchPrediction
:
149 /* Shouldn't happen. Fetch2 is the only source of
150 * BranchPredictions */
152 case BranchData::UnpredictedBranch
:
153 /* Unpredicted branch or barrier */
154 DPRINTF(Branch
, "Unpredicted branch seen inst: %s\n", *inst
);
155 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
156 branch
.target
, true, inst
->id
.threadId
);
158 case BranchData::CorrectlyPredictedBranch
:
159 /* Predicted taken, was taken */
160 DPRINTF(Branch
, "Branch predicted correctly inst: %s\n", *inst
);
161 branchPredictor
.update(inst
->id
.fetchSeqNum
,
164 case BranchData::BadlyPredictedBranch
:
165 /* Predicted taken, not taken */
166 DPRINTF(Branch
, "Branch mis-predicted inst: %s\n", *inst
);
167 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
168 branch
.target
/* Not used */, false, inst
->id
.threadId
);
170 case BranchData::BadlyPredictedBranchTarget
:
171 /* Predicted taken, was taken but to a different target */
172 DPRINTF(Branch
, "Branch mis-predicted target inst: %s target: %s\n",
173 *inst
, branch
.target
);
174 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
175 branch
.target
, true, inst
->id
.threadId
);
181 Fetch2::predictBranch(MinorDynInstPtr inst
, BranchData
&branch
)
183 TheISA::PCState inst_pc
= inst
->pc
;
185 assert(!inst
->predictedTaken
);
187 /* Skip non-control/sys call instructions */
188 if (inst
->staticInst
->isControl() ||
189 inst
->staticInst
->isSyscall())
191 /* Tried to predict */
192 inst
->triedToPredict
= true;
194 DPRINTF(Branch
, "Trying to predict for inst: %s\n", *inst
);
196 if (branchPredictor
.predict(inst
->staticInst
,
197 inst
->id
.fetchSeqNum
, inst_pc
,
200 inst
->predictedTaken
= true;
201 inst
->predictedTarget
= inst_pc
;
202 branch
.target
= inst_pc
;
205 DPRINTF(Branch
, "Not attempting prediction for inst: %s\n", *inst
);
208 /* If we predict taken, set branch and update sequence numbers */
209 if (inst
->predictedTaken
) {
210 /* Update the predictionSeqNum and remember the streamSeqNum that it
211 * was associated with */
212 expectedStreamSeqNum
= inst
->id
.streamSeqNum
;
214 BranchData new_branch
= BranchData(BranchData::BranchPrediction
,
215 inst
->id
.streamSeqNum
, predictionSeqNum
+ 1,
216 inst
->predictedTarget
, inst
);
218 /* Mark with a new prediction number by the stream number of the
219 * instruction causing the prediction */
223 DPRINTF(Branch
, "Branch predicted taken inst: %s target: %s"
224 " new predictionSeqNum: %d\n",
225 *inst
, inst
->predictedTarget
, predictionSeqNum
);
232 inputBuffer
.setTail(*inp
.outputWire
);
233 ForwardInstData
&insts_out
= *out
.inputWire
;
234 BranchData prediction
;
235 BranchData
&branch_inp
= *branchInp
.outputWire
;
237 assert(insts_out
.isBubble());
241 /* React to branches from Execute to update local branch prediction
243 updateBranchPrediction(branch_inp
);
245 /* If a branch arrives, don't try and do anything about it. Only
246 * react to your own predictions */
247 if (branch_inp
.isStreamChange()) {
248 DPRINTF(Fetch
, "Dumping all input as a stream changing branch"
254 /* Even when blocked, clear out input lines with the wrong
255 * prediction sequence number */
257 const ForwardLineData
*line_in
= getInput();
260 expectedStreamSeqNum
== line_in
->id
.streamSeqNum
&&
261 predictionSeqNum
!= line_in
->id
.predictionSeqNum
)
263 DPRINTF(Fetch
, "Discarding line %s"
264 " due to predictionSeqNum mismatch (expected: %d)\n",
265 line_in
->id
, predictionSeqNum
);
270 if (processMoreThanOneInput
) {
271 DPRINTF(Fetch
, "Wrapping\n");
272 line_in
= getInput();
279 if (!nextStageReserve
.canReserve()) {
282 const ForwardLineData
*line_in
= getInput();
284 unsigned int output_index
= 0;
286 /* Pack instructions into the output while we can. This may involve
287 * using more than one input line. Note that lineWidth will be 0
288 * for faulting lines */
290 (line_in
->isFault() ||
291 inputIndex
< line_in
->lineWidth
) && /* More input */
292 output_index
< outputWidth
&& /* More output to fill */
293 prediction
.isBubble() /* No predicted branch */)
295 ThreadContext
*thread
= cpu
.getContext(line_in
->id
.threadId
);
296 TheISA::Decoder
*decoder
= thread
->getDecoderPtr();
298 /* Discard line due to prediction sequence number being wrong but
299 * without the streamSeqNum number having changed */
301 expectedStreamSeqNum
== line_in
->id
.streamSeqNum
&&
302 predictionSeqNum
!= line_in
->id
.predictionSeqNum
;
304 /* Set the PC if the stream changes. Setting havePC to false in
305 * a previous cycle handles all other change of flow of control
307 bool set_pc
= lastStreamSeqNum
!= line_in
->id
.streamSeqNum
;
309 if (!discard_line
&& (!havePC
|| set_pc
)) {
310 /* Set the inputIndex to be the MachInst-aligned offset
311 * from lineBaseAddr of the new PC value */
313 (line_in
->pc
.instAddr() & BaseCPU::PCMask
) -
314 line_in
->lineBaseAddr
;
315 DPRINTF(Fetch
, "Setting new PC value: %s inputIndex: 0x%x"
316 " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
317 line_in
->pc
, inputIndex
, line_in
->lineBaseAddr
,
324 /* The generated instruction. Leave as NULL if no instruction
325 * is to be packed into the output */
326 MinorDynInstPtr dyn_inst
= NULL
;
329 /* Rest of line was from an older prediction in the same
331 DPRINTF(Fetch
, "Discarding line %s (from inputIndex: %d)"
332 " due to predictionSeqNum mismatch (expected: %d)\n",
333 line_in
->id
, inputIndex
, predictionSeqNum
);
334 } else if (line_in
->isFault()) {
335 /* Pack a fault as a MinorDynInst with ->fault set */
337 /* Make a new instruction and pick up the line, stream,
338 * prediction, thread ids from the incoming line */
339 dyn_inst
= new MinorDynInst(line_in
->id
);
341 /* Fetch and prediction sequence numbers originate here */
342 dyn_inst
->id
.fetchSeqNum
= fetchSeqNum
;
343 dyn_inst
->id
.predictionSeqNum
= predictionSeqNum
;
344 /* To complete the set, test that exec sequence number has
346 assert(dyn_inst
->id
.execSeqNum
== 0);
350 /* Pack a faulting instruction but allow other
351 * instructions to be generated. (Fetch2 makes no
352 * immediate judgement about streamSeqNum) */
353 dyn_inst
->fault
= line_in
->fault
;
354 DPRINTF(Fetch
, "Fault being passed output_index: "
355 "%d: %s\n", output_index
, dyn_inst
->fault
->name());
357 uint8_t *line
= line_in
->line
;
359 TheISA::MachInst inst_word
;
360 /* The instruction is wholly in the line, can just
362 inst_word
= TheISA::gtoh(
363 *(reinterpret_cast<TheISA::MachInst
*>
364 (line
+ inputIndex
)));
366 if (!decoder
->instReady()) {
367 decoder
->moreBytes(pc
,
368 line_in
->lineBaseAddr
+ inputIndex
, inst_word
);
369 DPRINTF(Fetch
, "Offering MachInst to decoder"
370 " addr: 0x%x\n", line_in
->lineBaseAddr
+ inputIndex
);
373 /* Maybe make the above a loop to accomodate ISAs with
374 * instructions longer than sizeof(MachInst) */
376 if (decoder
->instReady()) {
377 /* Make a new instruction and pick up the line, stream,
378 * prediction, thread ids from the incoming line */
379 dyn_inst
= new MinorDynInst(line_in
->id
);
381 /* Fetch and prediction sequence numbers originate here */
382 dyn_inst
->id
.fetchSeqNum
= fetchSeqNum
;
383 dyn_inst
->id
.predictionSeqNum
= predictionSeqNum
;
384 /* To complete the set, test that exec sequence number
385 * has not been set */
386 assert(dyn_inst
->id
.execSeqNum
== 0);
388 /* Note that the decoder can update the given PC.
389 * Remember not to assign it until *after* calling
391 StaticInstPtr decoded_inst
= decoder
->decode(pc
);
392 dyn_inst
->staticInst
= decoded_inst
;
396 DPRINTF(Fetch
, "Instruction extracted from line %s"
397 " lineWidth: %d output_index: %d inputIndex: %d"
398 " pc: %s inst: %s\n",
400 line_in
->lineWidth
, output_index
, inputIndex
,
403 #if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
404 /* In SE mode, it's possible to branch to a microop when
405 * replaying faults such as page faults (or simply
406 * intra-microcode branches in X86). Unfortunately,
407 * as Minor has micro-op decomposition in a separate
408 * pipeline stage from instruction decomposition, the
409 * following advancePC (which may follow a branch with
410 * microPC() != 0) *must* see a fresh macroop. This
411 * kludge should be improved with an addition to PCState
412 * but I offer it in this form for the moment
414 * X86 can branch within microops so we need to deal with
415 * the case that, after a branch, the first un-advanced PC
416 * may be pointing to a microop other than 0. Once
417 * advanced, however, the microop number *must* be 0 */
422 /* Advance PC for the next instruction */
423 TheISA::advancePC(pc
, decoded_inst
);
425 /* Predict any branches and issue a branch if
427 predictBranch(dyn_inst
, prediction
);
429 DPRINTF(Fetch
, "Inst not ready yet\n");
432 /* Step on the pointer into the line if there's no
433 * complete instruction waiting */
434 if (decoder
->needMoreBytes()) {
435 inputIndex
+= sizeof(TheISA::MachInst
);
437 DPRINTF(Fetch
, "Updated inputIndex value PC: %s"
438 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
439 line_in
->pc
, inputIndex
, line_in
->lineBaseAddr
,
445 /* Step to next sequence number */
448 /* Correctly size the output before writing */
449 if (output_index
== 0)
450 insts_out
.resize(outputWidth
);
451 /* Pack the generated dynamic instruction into the output */
452 insts_out
.insts
[output_index
] = dyn_inst
;
455 /* Output MinorTrace instruction info for
456 * pre-microop decomposition macroops */
457 if (DTRACE(MinorTrace
) && !dyn_inst
->isFault() &&
458 dyn_inst
->staticInst
->isMacroop())
460 dyn_inst
->minorTraceInst(*this);
464 /* Remember the streamSeqNum of this line so we can tell when
465 * we change stream */
466 lastStreamSeqNum
= line_in
->id
.streamSeqNum
;
468 /* Asked to discard line or there was a branch or fault */
469 if (!prediction
.isBubble() || /* The remains of a
470 line with a prediction in it */
471 line_in
->isFault() /* A line which is just a fault */)
473 DPRINTF(Fetch
, "Discarding all input on branch/fault\n");
477 } else if (discard_line
) {
478 /* Just discard one line, one's behind it may have new
479 * stream sequence numbers. There's a DPRINTF above
484 } else if (inputIndex
== line_in
->lineWidth
) {
485 /* Got to end of a line, pop the line but keep PC
486 * in case this is a line-wrapping inst. */
491 if (!line_in
&& processMoreThanOneInput
) {
492 DPRINTF(Fetch
, "Wrapping\n");
493 line_in
= getInput();
497 /* The rest of the output (if any) should already have been packed
498 * with bubble instructions by insts_out's initialisation */
501 /** Reserve a slot in the next stage and output data */
502 *predictionOut
.inputWire
= prediction
;
504 /* If we generated output, reserve space for the result in the next stage
505 * and mark the stage as being active this cycle */
506 if (!insts_out
.isBubble()) {
507 /* Note activity of following buffer */
508 cpu
.activityRecorder
->activity();
509 nextStageReserve
.reserve();
512 /* If we still have input to process and somewhere to put it,
513 * mark stage as active */
514 if (getInput() && nextStageReserve
.canReserve())
515 cpu
.activityRecorder
->activateStage(Pipeline::Fetch2StageId
);
517 /* Make sure the input (if any left) is pushed */
518 inputBuffer
.pushTail();
524 return inputBuffer
.empty() &&
525 (*inp
.outputWire
).isBubble() &&
526 (*predictionOut
.inputWire
).isBubble();
530 Fetch2::minorTrace() const
532 std::ostringstream data
;
537 (*out
.inputWire
).reportData(data
);
539 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
540 inputIndex
, havePC
, predictionSeqNum
, data
.str());
541 inputBuffer
.minorTrace();