2 * Copyright (c) 2013-2014,2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andrew Bardsley
40 #include "cpu/minor/fetch2.hh"
44 #include "arch/decoder.hh"
45 #include "arch/utility.hh"
46 #include "cpu/minor/pipeline.hh"
47 #include "cpu/pred/bpred_unit.hh"
48 #include "debug/Branch.hh"
49 #include "debug/Fetch.hh"
50 #include "debug/MinorTrace.hh"
55 Fetch2::Fetch2(const std::string
&name
,
57 MinorCPUParams
¶ms
,
58 Latch
<ForwardLineData
>::Output inp_
,
59 Latch
<BranchData
>::Output branchInp_
,
60 Latch
<BranchData
>::Input predictionOut_
,
61 Latch
<ForwardInstData
>::Input out_
,
62 std::vector
<InputBuffer
<ForwardInstData
>> &next_stage_input_buffer
) :
66 branchInp(branchInp_
),
67 predictionOut(predictionOut_
),
69 nextStageReserve(next_stage_input_buffer
),
70 outputWidth(params
.decodeInputWidth
),
71 processMoreThanOneInput(params
.fetch2CycleInput
),
72 branchPredictor(*params
.branchPred
),
73 fetchInfo(params
.numThreads
),
77 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name
, outputWidth
);
79 if (params
.fetch2InputBufferSize
< 1) {
80 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name
,
81 params
.fetch2InputBufferSize
);
84 /* Per-thread input buffers */
85 for (ThreadID tid
= 0; tid
< params
.numThreads
; tid
++) {
86 inputBuffer
.push_back(
87 InputBuffer
<ForwardLineData
>(
88 name
+ ".inputBuffer" + std::to_string(tid
), "lines",
89 params
.fetch2InputBufferSize
));
93 const ForwardLineData
*
94 Fetch2::getInput(ThreadID tid
)
96 /* Get a line from the inputBuffer to work with */
97 if (!inputBuffer
[tid
].empty()) {
98 return &(inputBuffer
[tid
].front());
105 Fetch2::popInput(ThreadID tid
)
107 if (!inputBuffer
[tid
].empty()) {
108 inputBuffer
[tid
].front().freeLine();
109 inputBuffer
[tid
].pop();
112 fetchInfo
[tid
].inputIndex
= 0;
116 Fetch2::dumpAllInput(ThreadID tid
)
118 DPRINTF(Fetch
, "Dumping whole input buffer\n");
119 while (!inputBuffer
[tid
].empty())
122 fetchInfo
[tid
].inputIndex
= 0;
126 Fetch2::updateBranchPrediction(const BranchData
&branch
)
128 MinorDynInstPtr inst
= branch
.inst
;
130 /* Don't even consider instructions we didn't try to predict or faults */
131 if (inst
->isFault() || !inst
->triedToPredict
)
134 switch (branch
.reason
) {
135 case BranchData::NoBranch
:
136 /* No data to update */
138 case BranchData::Interrupt
:
139 /* Never try to predict interrupts */
141 case BranchData::SuspendThread
:
142 /* Don't need to act on suspends */
144 case BranchData::HaltFetch
:
145 /* Don't need to act on fetch wakeup */
147 case BranchData::BranchPrediction
:
148 /* Shouldn't happen. Fetch2 is the only source of
149 * BranchPredictions */
151 case BranchData::UnpredictedBranch
:
152 /* Unpredicted branch or barrier */
153 DPRINTF(Branch
, "Unpredicted branch seen inst: %s\n", *inst
);
154 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
155 branch
.target
, true, inst
->id
.threadId
);
156 // Update after squashing to accomodate O3CPU
157 // using the branch prediction code.
158 branchPredictor
.update(inst
->id
.fetchSeqNum
,
161 case BranchData::CorrectlyPredictedBranch
:
162 /* Predicted taken, was taken */
163 DPRINTF(Branch
, "Branch predicted correctly inst: %s\n", *inst
);
164 branchPredictor
.update(inst
->id
.fetchSeqNum
,
167 case BranchData::BadlyPredictedBranch
:
168 /* Predicted taken, not taken */
169 DPRINTF(Branch
, "Branch mis-predicted inst: %s\n", *inst
);
170 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
171 branch
.target
/* Not used */, false, inst
->id
.threadId
);
172 // Update after squashing to accomodate O3CPU
173 // using the branch prediction code.
174 branchPredictor
.update(inst
->id
.fetchSeqNum
,
177 case BranchData::BadlyPredictedBranchTarget
:
178 /* Predicted taken, was taken but to a different target */
179 DPRINTF(Branch
, "Branch mis-predicted target inst: %s target: %s\n",
180 *inst
, branch
.target
);
181 branchPredictor
.squash(inst
->id
.fetchSeqNum
,
182 branch
.target
, true, inst
->id
.threadId
);
188 Fetch2::predictBranch(MinorDynInstPtr inst
, BranchData
&branch
)
190 Fetch2ThreadInfo
&thread
= fetchInfo
[inst
->id
.threadId
];
191 TheISA::PCState inst_pc
= inst
->pc
;
193 assert(!inst
->predictedTaken
);
195 /* Skip non-control/sys call instructions */
196 if (inst
->staticInst
->isControl() ||
197 inst
->staticInst
->isSyscall())
199 /* Tried to predict */
200 inst
->triedToPredict
= true;
202 DPRINTF(Branch
, "Trying to predict for inst: %s\n", *inst
);
204 if (branchPredictor
.predict(inst
->staticInst
,
205 inst
->id
.fetchSeqNum
, inst_pc
,
208 inst
->predictedTaken
= true;
209 inst
->predictedTarget
= inst_pc
;
210 branch
.target
= inst_pc
;
213 DPRINTF(Branch
, "Not attempting prediction for inst: %s\n", *inst
);
216 /* If we predict taken, set branch and update sequence numbers */
217 if (inst
->predictedTaken
) {
218 /* Update the predictionSeqNum and remember the streamSeqNum that it
219 * was associated with */
220 thread
.expectedStreamSeqNum
= inst
->id
.streamSeqNum
;
222 BranchData new_branch
= BranchData(BranchData::BranchPrediction
,
224 inst
->id
.streamSeqNum
, thread
.predictionSeqNum
+ 1,
225 inst
->predictedTarget
, inst
);
227 /* Mark with a new prediction number by the stream number of the
228 * instruction causing the prediction */
229 thread
.predictionSeqNum
++;
232 DPRINTF(Branch
, "Branch predicted taken inst: %s target: %s"
233 " new predictionSeqNum: %d\n",
234 *inst
, inst
->predictedTarget
, thread
.predictionSeqNum
);
241 /* Push input onto appropriate input buffer */
242 if (!inp
.outputWire
->isBubble())
243 inputBuffer
[inp
.outputWire
->id
.threadId
].setTail(*inp
.outputWire
);
245 ForwardInstData
&insts_out
= *out
.inputWire
;
246 BranchData prediction
;
247 BranchData
&branch_inp
= *branchInp
.outputWire
;
249 assert(insts_out
.isBubble());
251 /* React to branches from Execute to update local branch prediction
253 updateBranchPrediction(branch_inp
);
255 /* If a branch arrives, don't try and do anything about it. Only
256 * react to your own predictions */
257 if (branch_inp
.isStreamChange()) {
258 DPRINTF(Fetch
, "Dumping all input as a stream changing branch"
260 dumpAllInput(branch_inp
.threadId
);
261 fetchInfo
[branch_inp
.threadId
].havePC
= false;
264 assert(insts_out
.isBubble());
265 /* Even when blocked, clear out input lines with the wrong
266 * prediction sequence number */
267 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
268 Fetch2ThreadInfo
&thread
= fetchInfo
[tid
];
270 thread
.blocked
= !nextStageReserve
[tid
].canReserve();
272 const ForwardLineData
*line_in
= getInput(tid
);
275 thread
.expectedStreamSeqNum
== line_in
->id
.streamSeqNum
&&
276 thread
.predictionSeqNum
!= line_in
->id
.predictionSeqNum
)
278 DPRINTF(Fetch
, "Discarding line %s"
279 " due to predictionSeqNum mismatch (expected: %d)\n",
280 line_in
->id
, thread
.predictionSeqNum
);
283 fetchInfo
[tid
].havePC
= false;
285 if (processMoreThanOneInput
) {
286 DPRINTF(Fetch
, "Wrapping\n");
287 line_in
= getInput(tid
);
294 ThreadID tid
= getScheduledThread();
295 DPRINTF(Fetch
, "Scheduled Thread: %d\n", tid
);
297 assert(insts_out
.isBubble());
298 if (tid
!= InvalidThreadID
) {
299 Fetch2ThreadInfo
&fetch_info
= fetchInfo
[tid
];
301 const ForwardLineData
*line_in
= getInput(tid
);
303 unsigned int output_index
= 0;
305 /* Pack instructions into the output while we can. This may involve
306 * using more than one input line. Note that lineWidth will be 0
307 * for faulting lines */
309 (line_in
->isFault() ||
310 fetch_info
.inputIndex
< line_in
->lineWidth
) && /* More input */
311 output_index
< outputWidth
&& /* More output to fill */
312 prediction
.isBubble() /* No predicted branch */)
314 ThreadContext
*thread
= cpu
.getContext(line_in
->id
.threadId
);
315 TheISA::Decoder
*decoder
= thread
->getDecoderPtr();
317 /* Discard line due to prediction sequence number being wrong but
318 * without the streamSeqNum number having changed */
320 fetch_info
.expectedStreamSeqNum
== line_in
->id
.streamSeqNum
&&
321 fetch_info
.predictionSeqNum
!= line_in
->id
.predictionSeqNum
;
323 /* Set the PC if the stream changes. Setting havePC to false in
324 * a previous cycle handles all other change of flow of control
326 bool set_pc
= fetch_info
.lastStreamSeqNum
!= line_in
->id
.streamSeqNum
;
328 if (!discard_line
&& (!fetch_info
.havePC
|| set_pc
)) {
329 /* Set the inputIndex to be the MachInst-aligned offset
330 * from lineBaseAddr of the new PC value */
331 fetch_info
.inputIndex
=
332 (line_in
->pc
.instAddr() & BaseCPU::PCMask
) -
333 line_in
->lineBaseAddr
;
334 DPRINTF(Fetch
, "Setting new PC value: %s inputIndex: 0x%x"
335 " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
336 line_in
->pc
, fetch_info
.inputIndex
, line_in
->lineBaseAddr
,
338 fetch_info
.pc
= line_in
->pc
;
339 fetch_info
.havePC
= true;
343 /* The generated instruction. Leave as NULL if no instruction
344 * is to be packed into the output */
345 MinorDynInstPtr dyn_inst
= NULL
;
348 /* Rest of line was from an older prediction in the same
350 DPRINTF(Fetch
, "Discarding line %s (from inputIndex: %d)"
351 " due to predictionSeqNum mismatch (expected: %d)\n",
352 line_in
->id
, fetch_info
.inputIndex
,
353 fetch_info
.predictionSeqNum
);
354 } else if (line_in
->isFault()) {
355 /* Pack a fault as a MinorDynInst with ->fault set */
357 /* Make a new instruction and pick up the line, stream,
358 * prediction, thread ids from the incoming line */
359 dyn_inst
= new MinorDynInst(line_in
->id
);
361 /* Fetch and prediction sequence numbers originate here */
362 dyn_inst
->id
.fetchSeqNum
= fetch_info
.fetchSeqNum
;
363 dyn_inst
->id
.predictionSeqNum
= fetch_info
.predictionSeqNum
;
364 /* To complete the set, test that exec sequence number has
366 assert(dyn_inst
->id
.execSeqNum
== 0);
368 dyn_inst
->pc
= fetch_info
.pc
;
370 /* Pack a faulting instruction but allow other
371 * instructions to be generated. (Fetch2 makes no
372 * immediate judgement about streamSeqNum) */
373 dyn_inst
->fault
= line_in
->fault
;
374 DPRINTF(Fetch
, "Fault being passed output_index: "
375 "%d: %s\n", output_index
, dyn_inst
->fault
->name());
377 uint8_t *line
= line_in
->line
;
379 /* The instruction is wholly in the line, can just
381 auto inst_word
= *reinterpret_cast<TheISA::MachInst
*>
382 (line
+ fetch_info
.inputIndex
);
384 if (!decoder
->instReady()) {
385 decoder
->moreBytes(fetch_info
.pc
,
386 line_in
->lineBaseAddr
+ fetch_info
.inputIndex
,
388 DPRINTF(Fetch
, "Offering MachInst to decoder addr: 0x%x\n",
389 line_in
->lineBaseAddr
+ fetch_info
.inputIndex
);
392 /* Maybe make the above a loop to accomodate ISAs with
393 * instructions longer than sizeof(MachInst) */
395 if (decoder
->instReady()) {
396 /* Make a new instruction and pick up the line, stream,
397 * prediction, thread ids from the incoming line */
398 dyn_inst
= new MinorDynInst(line_in
->id
);
400 /* Fetch and prediction sequence numbers originate here */
401 dyn_inst
->id
.fetchSeqNum
= fetch_info
.fetchSeqNum
;
402 dyn_inst
->id
.predictionSeqNum
= fetch_info
.predictionSeqNum
;
403 /* To complete the set, test that exec sequence number
404 * has not been set */
405 assert(dyn_inst
->id
.execSeqNum
== 0);
407 /* Note that the decoder can update the given PC.
408 * Remember not to assign it until *after* calling
410 StaticInstPtr decoded_inst
= decoder
->decode(fetch_info
.pc
);
411 dyn_inst
->staticInst
= decoded_inst
;
413 dyn_inst
->pc
= fetch_info
.pc
;
414 DPRINTF(Fetch
, "decoder inst %s\n", *dyn_inst
);
416 // Collect some basic inst class stats
417 if (decoded_inst
->isLoad())
419 else if (decoded_inst
->isStore())
421 else if (decoded_inst
->isAtomic())
423 else if (decoded_inst
->isVector())
425 else if (decoded_inst
->isFloating())
427 else if (decoded_inst
->isInteger())
430 DPRINTF(Fetch
, "Instruction extracted from line %s"
431 " lineWidth: %d output_index: %d inputIndex: %d"
432 " pc: %s inst: %s\n",
434 line_in
->lineWidth
, output_index
, fetch_info
.inputIndex
,
435 fetch_info
.pc
, *dyn_inst
);
437 #if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
438 /* In SE mode, it's possible to branch to a microop when
439 * replaying faults such as page faults (or simply
440 * intra-microcode branches in X86). Unfortunately,
441 * as Minor has micro-op decomposition in a separate
442 * pipeline stage from instruction decomposition, the
443 * following advancePC (which may follow a branch with
444 * microPC() != 0) *must* see a fresh macroop. This
445 * kludge should be improved with an addition to PCState
446 * but I offer it in this form for the moment
448 * X86 can branch within microops so we need to deal with
449 * the case that, after a branch, the first un-advanced PC
450 * may be pointing to a microop other than 0. Once
451 * advanced, however, the microop number *must* be 0 */
452 fetch_info
.pc
.upc(0);
453 fetch_info
.pc
.nupc(1);
456 /* Advance PC for the next instruction */
457 TheISA::advancePC(fetch_info
.pc
, decoded_inst
);
459 /* Predict any branches and issue a branch if
461 predictBranch(dyn_inst
, prediction
);
463 DPRINTF(Fetch
, "Inst not ready yet\n");
466 /* Step on the pointer into the line if there's no
467 * complete instruction waiting */
468 if (decoder
->needMoreBytes()) {
469 fetch_info
.inputIndex
+= sizeof(TheISA::MachInst
);
471 DPRINTF(Fetch
, "Updated inputIndex value PC: %s"
472 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
473 line_in
->pc
, fetch_info
.inputIndex
, line_in
->lineBaseAddr
,
479 /* Step to next sequence number */
480 fetch_info
.fetchSeqNum
++;
482 /* Correctly size the output before writing */
483 if (output_index
== 0) {
484 insts_out
.resize(outputWidth
);
486 /* Pack the generated dynamic instruction into the output */
487 insts_out
.insts
[output_index
] = dyn_inst
;
490 /* Output MinorTrace instruction info for
491 * pre-microop decomposition macroops */
492 if (DTRACE(MinorTrace
) && !dyn_inst
->isFault() &&
493 dyn_inst
->staticInst
->isMacroop())
495 dyn_inst
->minorTraceInst(*this);
499 /* Remember the streamSeqNum of this line so we can tell when
500 * we change stream */
501 fetch_info
.lastStreamSeqNum
= line_in
->id
.streamSeqNum
;
503 /* Asked to discard line or there was a branch or fault */
504 if (!prediction
.isBubble() || /* The remains of a
505 line with a prediction in it */
506 line_in
->isFault() /* A line which is just a fault */)
508 DPRINTF(Fetch
, "Discarding all input on branch/fault\n");
510 fetch_info
.havePC
= false;
512 } else if (discard_line
) {
513 /* Just discard one line, one's behind it may have new
514 * stream sequence numbers. There's a DPRINTF above
517 fetch_info
.havePC
= false;
519 } else if (fetch_info
.inputIndex
== line_in
->lineWidth
) {
520 /* Got to end of a line, pop the line but keep PC
521 * in case this is a line-wrapping inst. */
526 if (!line_in
&& processMoreThanOneInput
) {
527 DPRINTF(Fetch
, "Wrapping\n");
528 line_in
= getInput(tid
);
532 /* The rest of the output (if any) should already have been packed
533 * with bubble instructions by insts_out's initialisation */
535 if (tid
== InvalidThreadID
) {
536 assert(insts_out
.isBubble());
538 /** Reserve a slot in the next stage and output data */
539 *predictionOut
.inputWire
= prediction
;
541 /* If we generated output, reserve space for the result in the next stage
542 * and mark the stage as being active this cycle */
543 if (!insts_out
.isBubble()) {
544 /* Note activity of following buffer */
545 cpu
.activityRecorder
->activity();
546 insts_out
.threadId
= tid
;
547 nextStageReserve
[tid
].reserve();
550 /* If we still have input to process and somewhere to put it,
551 * mark stage as active */
552 for (ThreadID i
= 0; i
< cpu
.numThreads
; i
++)
554 if (getInput(i
) && nextStageReserve
[i
].canReserve()) {
555 cpu
.activityRecorder
->activateStage(Pipeline::Fetch2StageId
);
560 /* Make sure the input (if any left) is pushed */
561 if (!inp
.outputWire
->isBubble())
562 inputBuffer
[inp
.outputWire
->id
.threadId
].pushTail();
566 Fetch2::getScheduledThread()
568 /* Select thread via policy. */
569 std::vector
<ThreadID
> priority_list
;
571 switch (cpu
.threadPolicy
) {
572 case Enums::SingleThreaded
:
573 priority_list
.push_back(0);
575 case Enums::RoundRobin
:
576 priority_list
= cpu
.roundRobinPriority(threadPriority
);
579 priority_list
= cpu
.randomPriority();
582 panic("Unknown fetch policy");
585 for (auto tid
: priority_list
) {
586 if (getInput(tid
) && !fetchInfo
[tid
].blocked
) {
587 threadPriority
= tid
;
592 return InvalidThreadID
;
598 for (const auto &buffer
: inputBuffer
) {
603 return (*inp
.outputWire
).isBubble() &&
604 (*predictionOut
.inputWire
).isBubble();
610 using namespace Stats
;
613 .name(name() + ".int_instructions")
614 .desc("Number of integer instructions successfully decoded")
618 .name(name() + ".fp_instructions")
619 .desc("Number of floating point instructions successfully decoded")
623 .name(name() + ".vec_instructions")
624 .desc("Number of SIMD instructions successfully decoded")
628 .name(name() + ".load_instructions")
629 .desc("Number of memory load instructions successfully decoded")
633 .name(name() + ".store_instructions")
634 .desc("Number of memory store instructions successfully decoded")
638 .name(name() + ".amo_instructions")
639 .desc("Number of memory atomic instructions successfully decoded")
644 Fetch2::minorTrace() const
646 std::ostringstream data
;
648 if (fetchInfo
[0].blocked
)
651 (*out
.inputWire
).reportData(data
);
653 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
654 fetchInfo
[0].inputIndex
, fetchInfo
[0].havePC
, fetchInfo
[0].predictionSeqNum
, data
.str());
655 inputBuffer
[0].minorTrace();