src/cpu/minor/fetch2.hh

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /**
  39  * @file
  40  *
  41  *  Fetch2 receives lines of data from Fetch1, separates them into
  42  *  instructions and passes them to Decode
  43  */
  44
  45 #ifndef __CPU_MINOR_FETCH2_HH__
  46 #define __CPU_MINOR_FETCH2_HH__
  47
  48 #include "cpu/minor/buffers.hh"
  49 #include "cpu/minor/cpu.hh"
  50 #include "cpu/minor/pipe_data.hh"
  51 #include "cpu/pred/bpred_unit.hh"
  52 #include "params/MinorCPU.hh"
  53
  54 namespace Minor
  55 {
  56
  57 /** This stage receives lines of data from Fetch1, separates them into
  58  *  instructions and passes them to Decode */
  59 class Fetch2 : public Named
  60 {
  61   protected:
  62     /** Pointer back to the containing CPU */
  63     MinorCPU &cpu;
  64
  65     /** Input port carrying lines from Fetch1 */
  66     Latch<ForwardLineData>::Output inp;
  67
  68     /** Input port carrying branches from Execute.  This is a snoop of the
  69      *  data provided to F1. */
  70     Latch<BranchData>::Output branchInp;
  71
  72     /** Output port carrying predictions back to Fetch1 */
  73     Latch<BranchData>::Input predictionOut;
  74
  75     /** Output port carrying instructions into Decode */
  76     Latch<ForwardInstData>::Input out;
  77
  78     /** Interface to reserve space in the next stage */
  79     std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;
  80
  81     /** Width of output of this stage/input of next in instructions */
  82     unsigned int outputWidth;
  83
  84     /** If true, more than one input word can be processed each cycle if
  85      *  there is room in the output to contain its processed data */
  86     bool processMoreThanOneInput;
  87
  88     /** Branch predictor passed from Python configuration */
  89     BPredUnit &branchPredictor;
  90
  91   public:
  92     /* Public so that Pipeline can pass it to Fetch1 */
  93     std::vector<InputBuffer<ForwardLineData>> inputBuffer;
  94
  95   protected:
  96     /** Data members after this line are cycle-to-cycle state */
  97
  98     struct Fetch2ThreadInfo {
  99
 100         /** Default constructor */
 101         Fetch2ThreadInfo() :
 102             inputIndex(0),
 103             pc(TheISA::PCState(0)),
 104             havePC(false),
 105             lastStreamSeqNum(InstId::firstStreamSeqNum),
 106             fetchSeqNum(InstId::firstFetchSeqNum),
 107             expectedStreamSeqNum(InstId::firstStreamSeqNum),
 108             predictionSeqNum(InstId::firstPredictionSeqNum),
 109             blocked(false)
 110         { }
 111
 112         Fetch2ThreadInfo(const Fetch2ThreadInfo& other) :
 113             inputIndex(other.inputIndex),
 114             pc(other.pc),
 115             havePC(other.havePC),
 116             lastStreamSeqNum(other.lastStreamSeqNum),
 117             expectedStreamSeqNum(other.expectedStreamSeqNum),
 118             predictionSeqNum(other.predictionSeqNum),
 119             blocked(other.blocked)
 120         { }
 121
 122         /** Index into an incompletely processed input line that instructions
 123          *  are to be extracted from */
 124         unsigned int inputIndex;
 125
 126
 127         /** Remembered program counter value.  Between contiguous lines, this
 128          *  is just updated with advancePC.  For lines following changes of
 129          *  stream, a new PC must be loaded and havePC be set.
 130          *  havePC is needed to accomodate instructions which span across
 131          *  lines meaning that Fetch2 and the decoder need to remember a PC
 132          *  value and a partially-offered instruction from the previous line */
 133         TheISA::PCState pc;
 134
 135         /** PC is currently valid.  Initially false, gets set to true when a
 136          *  change-of-stream line is received and false again when lines are
 137          *  discarded for any reason */
 138         bool havePC;
 139
 140         /** Stream sequence number of the last seen line used to identify
 141          *  changes of instruction stream */
 142         InstSeqNum lastStreamSeqNum;
 143
 144         /** Fetch2 is the source of fetch sequence numbers.  These represent the
 145          *  sequence that instructions were extracted from fetched lines. */
 146         InstSeqNum fetchSeqNum;
 147
 148         /** Stream sequence number remembered from last time the
 149          *  predictionSeqNum changed.  Lines should only be discarded when their
 150          *  predictionSeqNums disagree with Fetch2::predictionSeqNum *and* they
 151          *  are from the same stream that bore that prediction number */
 152         InstSeqNum expectedStreamSeqNum;
 153
 154         /** Fetch2 is the source of prediction sequence numbers.  These
 155          *  represent predicted changes of control flow sources from branch
 156          *  prediction in Fetch2. */
 157         InstSeqNum predictionSeqNum;
 158
 159         /** Blocked indication for report */
 160         bool blocked;
 161     };
 162
 163     std::vector<Fetch2ThreadInfo> fetchInfo;
 164     ThreadID threadPriority;
 165
 166     /** Stats */
 167     Stats::Scalar intInstructions;
 168     Stats::Scalar fpInstructions;
 169     Stats::Scalar vecInstructions;
 170     Stats::Scalar loadInstructions;
 171     Stats::Scalar storeInstructions;
 172     Stats::Scalar amoInstructions;
 173
 174   protected:
 175     /** Get a piece of data to work on from the inputBuffer, or 0 if there
 176      *  is no data. */
 177     const ForwardLineData *getInput(ThreadID tid);
 178
 179     /** Pop an element off the input buffer, if there are any */
 180     void popInput(ThreadID tid);
 181
 182     /** Dump the whole contents of the input buffer.  Useful after a
 183      *  prediction changes control flow */
 184     void dumpAllInput(ThreadID tid);
 185
 186     /** Update local branch prediction structures from feedback from
 187      *  Execute. */
 188     void updateBranchPrediction(const BranchData &branch);
 189
 190     /** Predicts branches for the given instruction.  Updates the
 191      *  instruction's predicted... fields and also the branch which
 192      *  carries the prediction to Fetch1 */
 193     void predictBranch(MinorDynInstPtr inst, BranchData &branch);
 194
 195     /** Use the current threading policy to determine the next thread to
 196      *  fetch from. */
 197     ThreadID getScheduledThread();
 198
 199   public:
 200     Fetch2(const std::string &name,
 201         MinorCPU &cpu_,
 202         MinorCPUParams &params,
 203         Latch<ForwardLineData>::Output inp_,
 204         Latch<BranchData>::Output branchInp_,
 205         Latch<BranchData>::Input predictionOut_,
 206         Latch<ForwardInstData>::Input out_,
 207         std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
 208
 209   public:
 210     /** Pass on input/buffer data to the output if you can */
 211     void evaluate();
 212
 213     void minorTrace() const;
 214
 215     void regStats();
 216
 217     /** Is this stage drained?  For Fetch2, draining is initiated by
 218      *  Execute halting Fetch1 causing Fetch2 to naturally drain.
 219      *  Branch predictions are ignored by Fetch1 during halt */
 220     bool isDrained();
 221 };
 222
 223 }
 224
 225 #endif /* __CPU_MINOR_FETCH2_HH__ */