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41 * Fetch2 receives lines of data from Fetch1, separates them into
42 * instructions and passes them to Decode
45 #ifndef __CPU_MINOR_FETCH2_HH__
46 #define __CPU_MINOR_FETCH2_HH__
48 #include "cpu/minor/buffers.hh"
49 #include "cpu/minor/cpu.hh"
50 #include "cpu/minor/pipe_data.hh"
51 #include "cpu/pred/bpred_unit.hh"
52 #include "params/MinorCPU.hh"
57 /** This stage receives lines of data from Fetch1, separates them into
58 * instructions and passes them to Decode */
59 class Fetch2 : public Named
62 /** Pointer back to the containing CPU */
65 /** Input port carrying lines from Fetch1 */
66 Latch<ForwardLineData>::Output inp;
68 /** Input port carrying branches from Execute. This is a snoop of the
69 * data provided to F1. */
70 Latch<BranchData>::Output branchInp;
72 /** Output port carrying predictions back to Fetch1 */
73 Latch<BranchData>::Input predictionOut;
75 /** Output port carrying instructions into Decode */
76 Latch<ForwardInstData>::Input out;
78 /** Interface to reserve space in the next stage */
79 std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;
81 /** Width of output of this stage/input of next in instructions */
82 unsigned int outputWidth;
84 /** If true, more than one input word can be processed each cycle if
85 * there is room in the output to contain its processed data */
86 bool processMoreThanOneInput;
88 /** Branch predictor passed from Python configuration */
89 BPredUnit &branchPredictor;
92 /* Public so that Pipeline can pass it to Fetch1 */
93 std::vector<InputBuffer<ForwardLineData>> inputBuffer;
96 /** Data members after this line are cycle-to-cycle state */
98 struct Fetch2ThreadInfo {
100 /** Default constructor */
103 pc(TheISA::PCState(0)),
105 lastStreamSeqNum(InstId::firstStreamSeqNum),
106 fetchSeqNum(InstId::firstFetchSeqNum),
107 expectedStreamSeqNum(InstId::firstStreamSeqNum),
108 predictionSeqNum(InstId::firstPredictionSeqNum),
112 Fetch2ThreadInfo(const Fetch2ThreadInfo& other) :
113 inputIndex(other.inputIndex),
115 havePC(other.havePC),
116 lastStreamSeqNum(other.lastStreamSeqNum),
117 expectedStreamSeqNum(other.expectedStreamSeqNum),
118 predictionSeqNum(other.predictionSeqNum),
119 blocked(other.blocked)
122 /** Index into an incompletely processed input line that instructions
123 * are to be extracted from */
124 unsigned int inputIndex;
127 /** Remembered program counter value. Between contiguous lines, this
128 * is just updated with advancePC. For lines following changes of
129 * stream, a new PC must be loaded and havePC be set.
130 * havePC is needed to accomodate instructions which span across
131 * lines meaning that Fetch2 and the decoder need to remember a PC
132 * value and a partially-offered instruction from the previous line */
135 /** PC is currently valid. Initially false, gets set to true when a
136 * change-of-stream line is received and false again when lines are
137 * discarded for any reason */
140 /** Stream sequence number of the last seen line used to identify
141 * changes of instruction stream */
142 InstSeqNum lastStreamSeqNum;
144 /** Fetch2 is the source of fetch sequence numbers. These represent the
145 * sequence that instructions were extracted from fetched lines. */
146 InstSeqNum fetchSeqNum;
148 /** Stream sequence number remembered from last time the
149 * predictionSeqNum changed. Lines should only be discarded when their
150 * predictionSeqNums disagree with Fetch2::predictionSeqNum *and* they
151 * are from the same stream that bore that prediction number */
152 InstSeqNum expectedStreamSeqNum;
154 /** Fetch2 is the source of prediction sequence numbers. These
155 * represent predicted changes of control flow sources from branch
156 * prediction in Fetch2. */
157 InstSeqNum predictionSeqNum;
159 /** Blocked indication for report */
163 std::vector<Fetch2ThreadInfo> fetchInfo;
164 ThreadID threadPriority;
167 Stats::Scalar intInstructions;
168 Stats::Scalar fpInstructions;
169 Stats::Scalar vecInstructions;
170 Stats::Scalar loadInstructions;
171 Stats::Scalar storeInstructions;
172 Stats::Scalar amoInstructions;
175 /** Get a piece of data to work on from the inputBuffer, or 0 if there
177 const ForwardLineData *getInput(ThreadID tid);
179 /** Pop an element off the input buffer, if there are any */
180 void popInput(ThreadID tid);
182 /** Dump the whole contents of the input buffer. Useful after a
183 * prediction changes control flow */
184 void dumpAllInput(ThreadID tid);
186 /** Update local branch prediction structures from feedback from
188 void updateBranchPrediction(const BranchData &branch);
190 /** Predicts branches for the given instruction. Updates the
191 * instruction's predicted... fields and also the branch which
192 * carries the prediction to Fetch1 */
193 void predictBranch(MinorDynInstPtr inst, BranchData &branch);
195 /** Use the current threading policy to determine the next thread to
197 ThreadID getScheduledThread();
200 Fetch2(const std::string &name,
202 MinorCPUParams ¶ms,
203 Latch<ForwardLineData>::Output inp_,
204 Latch<BranchData>::Output branchInp_,
205 Latch<BranchData>::Input predictionOut_,
206 Latch<ForwardInstData>::Input out_,
207 std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
210 /** Pass on input/buffer data to the output if you can */
213 void minorTrace() const;
217 /** Is this stage drained? For Fetch2, draining is initiated by
218 * Execute halting Fetch1 causing Fetch2 to naturally drain.
219 * Branch predictions are ignored by Fetch1 during halt */
225 #endif /* __CPU_MINOR_FETCH2_HH__ */