2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
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23 * this software without specific prior written permission.
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38 #include "cpu/minor/pipeline.hh"
42 #include "cpu/minor/decode.hh"
43 #include "cpu/minor/execute.hh"
44 #include "cpu/minor/fetch1.hh"
45 #include "cpu/minor/fetch2.hh"
46 #include "debug/Drain.hh"
47 #include "debug/MinorCPU.hh"
48 #include "debug/MinorTrace.hh"
49 #include "debug/Quiesce.hh"
54 Pipeline::Pipeline(MinorCPU
&cpu_
, MinorCPUParams
¶ms
) :
55 Ticked(cpu_
, &(cpu_
.BaseCPU::numCycles
)),
57 allow_idling(params
.enableIdling
),
58 f1ToF2(cpu
.name() + ".f1ToF2", "lines",
59 params
.fetch1ToFetch2ForwardDelay
),
60 f2ToF1(cpu
.name() + ".f2ToF1", "prediction",
61 params
.fetch1ToFetch2BackwardDelay
, true),
62 f2ToD(cpu
.name() + ".f2ToD", "insts",
63 params
.fetch2ToDecodeForwardDelay
),
64 dToE(cpu
.name() + ".dToE", "insts",
65 params
.decodeToExecuteForwardDelay
),
66 eToF1(cpu
.name() + ".eToF1", "branch",
67 params
.executeBranchDelay
),
68 execute(cpu
.name() + ".execute", cpu
, params
,
69 dToE
.output(), eToF1
.input()),
70 decode(cpu
.name() + ".decode", cpu
, params
,
71 f2ToD
.output(), dToE
.input(), execute
.inputBuffer
),
72 fetch2(cpu
.name() + ".fetch2", cpu
, params
,
73 f1ToF2
.output(), eToF1
.output(), f2ToF1
.input(), f2ToD
.input(),
75 fetch1(cpu
.name() + ".fetch1", cpu
, params
,
76 eToF1
.output(), f1ToF2
.input(), f2ToF1
.output(), fetch2
.inputBuffer
),
77 activityRecorder(cpu
.name() + ".activity", Num_StageId
,
78 /* The max depth of inter-stage FIFOs */
79 std::max(params
.fetch1ToFetch2ForwardDelay
,
80 std::max(params
.fetch2ToDecodeForwardDelay
,
81 std::max(params
.decodeToExecuteForwardDelay
,
82 params
.executeBranchDelay
)))),
83 needToSignalDrained(false)
85 if (params
.fetch1ToFetch2ForwardDelay
< 1) {
86 fatal("%s: fetch1ToFetch2ForwardDelay must be >= 1 (%d)\n",
87 cpu
.name(), params
.fetch1ToFetch2ForwardDelay
);
90 if (params
.fetch2ToDecodeForwardDelay
< 1) {
91 fatal("%s: fetch2ToDecodeForwardDelay must be >= 1 (%d)\n",
92 cpu
.name(), params
.fetch2ToDecodeForwardDelay
);
95 if (params
.decodeToExecuteForwardDelay
< 1) {
96 fatal("%s: decodeToExecuteForwardDelay must be >= 1 (%d)\n",
97 cpu
.name(), params
.decodeToExecuteForwardDelay
);
100 if (params
.executeBranchDelay
< 1) {
101 fatal("%s: executeBranchDelay must be >= 1\n",
102 cpu
.name(), params
.executeBranchDelay
);
115 Pipeline::minorTrace() const
124 execute
.minorTrace();
126 activityRecorder
.minorTrace();
132 /* Note that it's important to evaluate the stages in order to allow
133 * 'immediate', 0-time-offset TimeBuffer activity to be visible from
134 * later stages to earlier ones in the same cycle */
140 if (DTRACE(MinorTrace
))
143 /* Update the time buffers after the stages */
150 /* The activity recorder must be be called after all the stages and
151 * before the idler (which acts on the advice of the activity recorder */
152 activityRecorder
.evaluate();
155 /* Become idle if we can but are not draining */
156 if (!activityRecorder
.active() && !needToSignalDrained
) {
157 DPRINTF(Quiesce
, "Suspending as the processor is idle\n");
161 /* Deactivate all stages. Note that the stages *could*
162 * activate and deactivate themselves but that's fraught
163 * with additional difficulty.
164 * As organised herre */
165 activityRecorder
.deactivateStage(Pipeline::CPUStageId
);
166 activityRecorder
.deactivateStage(Pipeline::Fetch1StageId
);
167 activityRecorder
.deactivateStage(Pipeline::Fetch2StageId
);
168 activityRecorder
.deactivateStage(Pipeline::DecodeStageId
);
169 activityRecorder
.deactivateStage(Pipeline::ExecuteStageId
);
172 if (needToSignalDrained
) /* Must be draining */
174 DPRINTF(Drain
, "Still draining\n");
176 DPRINTF(Drain
, "Signalling end of draining\n");
177 cpu
.signalDrainDone();
178 needToSignalDrained
= false;
184 MinorCPU::MinorCPUPort
&
185 Pipeline::getInstPort()
187 return fetch1
.getIcachePort();
190 MinorCPU::MinorCPUPort
&
191 Pipeline::getDataPort()
193 return execute
.getDcachePort();
197 Pipeline::wakeupFetch(ThreadID tid
)
199 fetch1
.wakeupFetch(tid
);
205 DPRINTF(MinorCPU
, "Draining pipeline by halting inst fetches. "
206 " Execution should drain naturally\n");
210 /* Make sure that needToSignalDrained isn't accidentally set if we
211 * are 'pre-drained' */
212 bool drained
= isDrained();
213 needToSignalDrained
= !drained
;
219 Pipeline::drainResume()
221 DPRINTF(Drain
, "Drain resume\n");
223 for (ThreadID tid
= 0; tid
< cpu
.numThreads
; tid
++) {
224 fetch1
.wakeupFetch(tid
);
227 execute
.drainResume();
231 Pipeline::isDrained()
233 bool fetch1_drained
= fetch1
.isDrained();
234 bool fetch2_drained
= fetch2
.isDrained();
235 bool decode_drained
= decode
.isDrained();
236 bool execute_drained
= execute
.isDrained();
238 bool f1_to_f2_drained
= f1ToF2
.empty();
239 bool f2_to_f1_drained
= f2ToF1
.empty();
240 bool f2_to_d_drained
= f2ToD
.empty();
241 bool d_to_e_drained
= dToE
.empty();
243 bool ret
= fetch1_drained
&& fetch2_drained
&&
244 decode_drained
&& execute_drained
&&
245 f1_to_f2_drained
&& f2_to_f1_drained
&&
246 f2_to_d_drained
&& d_to_e_drained
;
248 DPRINTF(MinorCPU
, "Pipeline undrained stages state:%s%s%s%s%s%s%s%s\n",
249 (fetch1_drained
? "" : " Fetch1"),
250 (fetch2_drained
? "" : " Fetch2"),
251 (decode_drained
? "" : " Decode"),
252 (execute_drained
? "" : " Execute"),
253 (f1_to_f2_drained
? "" : " F1->F2"),
254 (f2_to_f1_drained
? "" : " F2->F1"),
255 (f2_to_d_drained
? "" : " F2->D"),
256 (d_to_e_drained
? "" : " D->E")