src/cpu/minor/pipeline.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "cpu/minor/pipeline.hh"
  39
  40 #include <algorithm>
  41
  42 #include "cpu/minor/decode.hh"
  43 #include "cpu/minor/execute.hh"
  44 #include "cpu/minor/fetch1.hh"
  45 #include "cpu/minor/fetch2.hh"
  46 #include "debug/Drain.hh"
  47 #include "debug/MinorCPU.hh"
  48 #include "debug/MinorTrace.hh"
  49 #include "debug/Quiesce.hh"
  50
  51 namespace Minor
  52 {
  53
  54 Pipeline::Pipeline(MinorCPU &cpu_, MinorCPUParams &params) :
  55     Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
  56     cpu(cpu_),
  57     allow_idling(params.enableIdling),
  58     f1ToF2(cpu.name() + ".f1ToF2", "lines",
  59         params.fetch1ToFetch2ForwardDelay),
  60     f2ToF1(cpu.name() + ".f2ToF1", "prediction",
  61         params.fetch1ToFetch2BackwardDelay, true),
  62     f2ToD(cpu.name() + ".f2ToD", "insts",
  63         params.fetch2ToDecodeForwardDelay),
  64     dToE(cpu.name() + ".dToE", "insts",
  65         params.decodeToExecuteForwardDelay),
  66     eToF1(cpu.name() + ".eToF1", "branch",
  67         params.executeBranchDelay),
  68     execute(cpu.name() + ".execute", cpu, params,
  69         dToE.output(), eToF1.input()),
  70     decode(cpu.name() + ".decode", cpu, params,
  71         f2ToD.output(), dToE.input(), execute.inputBuffer),
  72     fetch2(cpu.name() + ".fetch2", cpu, params,
  73         f1ToF2.output(), eToF1.output(), f2ToF1.input(), f2ToD.input(),
  74         decode.inputBuffer),
  75     fetch1(cpu.name() + ".fetch1", cpu, params,
  76         eToF1.output(), f1ToF2.input(), f2ToF1.output(), fetch2.inputBuffer),
  77     activityRecorder(cpu.name() + ".activity", Num_StageId,
  78         /* The max depth of inter-stage FIFOs */
  79         std::max(params.fetch1ToFetch2ForwardDelay,
  80         std::max(params.fetch2ToDecodeForwardDelay,
  81         std::max(params.decodeToExecuteForwardDelay,
  82         params.executeBranchDelay)))),
  83     needToSignalDrained(false)
  84 {
  85     if (params.fetch1ToFetch2ForwardDelay < 1) {
  86         fatal("%s: fetch1ToFetch2ForwardDelay must be >= 1 (%d)\n",
  87             cpu.name(), params.fetch1ToFetch2ForwardDelay);
  88     }
  89
  90     if (params.fetch2ToDecodeForwardDelay < 1) {
  91         fatal("%s: fetch2ToDecodeForwardDelay must be >= 1 (%d)\n",
  92             cpu.name(), params.fetch2ToDecodeForwardDelay);
  93     }
  94
  95     if (params.decodeToExecuteForwardDelay < 1) {
  96         fatal("%s: decodeToExecuteForwardDelay must be >= 1 (%d)\n",
  97             cpu.name(), params.decodeToExecuteForwardDelay);
  98     }
  99
 100     if (params.executeBranchDelay < 1) {
 101         fatal("%s: executeBranchDelay must be >= 1\n",
 102             cpu.name(), params.executeBranchDelay);
 103     }
 104 }
 105
 106 void
 107 Pipeline::regStats()
 108 {
 109     Ticked::regStats();
 110
 111     fetch2.regStats();
 112 }
 113
 114 void
 115 Pipeline::minorTrace() const
 116 {
 117     fetch1.minorTrace();
 118     f1ToF2.minorTrace();
 119     f2ToF1.minorTrace();
 120     fetch2.minorTrace();
 121     f2ToD.minorTrace();
 122     decode.minorTrace();
 123     dToE.minorTrace();
 124     execute.minorTrace();
 125     eToF1.minorTrace();
 126     activityRecorder.minorTrace();
 127 }
 128
 129 void
 130 Pipeline::evaluate()
 131 {
 132     /* Note that it's important to evaluate the stages in order to allow
 133      *  'immediate', 0-time-offset TimeBuffer activity to be visible from
 134      *  later stages to earlier ones in the same cycle */
 135     execute.evaluate();
 136     decode.evaluate();
 137     fetch2.evaluate();
 138     fetch1.evaluate();
 139
 140     if (DTRACE(MinorTrace))
 141         minorTrace();
 142
 143     /* Update the time buffers after the stages */
 144     f1ToF2.evaluate();
 145     f2ToF1.evaluate();
 146     f2ToD.evaluate();
 147     dToE.evaluate();
 148     eToF1.evaluate();
 149
 150     /* The activity recorder must be be called after all the stages and
 151      *  before the idler (which acts on the advice of the activity recorder */
 152     activityRecorder.evaluate();
 153
 154     if (allow_idling) {
 155         /* Become idle if we can but are not draining */
 156         if (!activityRecorder.active() && !needToSignalDrained) {
 157             DPRINTF(Quiesce, "Suspending as the processor is idle\n");
 158             stop();
 159         }
 160
 161         /* Deactivate all stages.  Note that the stages *could*
 162          *  activate and deactivate themselves but that's fraught
 163          *  with additional difficulty.
 164          *  As organised herre */
 165         activityRecorder.deactivateStage(Pipeline::CPUStageId);
 166         activityRecorder.deactivateStage(Pipeline::Fetch1StageId);
 167         activityRecorder.deactivateStage(Pipeline::Fetch2StageId);
 168         activityRecorder.deactivateStage(Pipeline::DecodeStageId);
 169         activityRecorder.deactivateStage(Pipeline::ExecuteStageId);
 170     }
 171
 172     if (needToSignalDrained) /* Must be draining */
 173     {
 174         DPRINTF(Drain, "Still draining\n");
 175         if (isDrained()) {
 176             DPRINTF(Drain, "Signalling end of draining\n");
 177             cpu.signalDrainDone();
 178             needToSignalDrained = false;
 179             stop();
 180         }
 181     }
 182 }
 183
 184 MinorCPU::MinorCPUPort &
 185 Pipeline::getInstPort()
 186 {
 187     return fetch1.getIcachePort();
 188 }
 189
 190 MinorCPU::MinorCPUPort &
 191 Pipeline::getDataPort()
 192 {
 193     return execute.getDcachePort();
 194 }
 195
 196 void
 197 Pipeline::wakeupFetch(ThreadID tid)
 198 {
 199     fetch1.wakeupFetch(tid);
 200 }
 201
 202 bool
 203 Pipeline::drain()
 204 {
 205     DPRINTF(MinorCPU, "Draining pipeline by halting inst fetches. "
 206         " Execution should drain naturally\n");
 207
 208     execute.drain();
 209
 210     /* Make sure that needToSignalDrained isn't accidentally set if we
 211      *  are 'pre-drained' */
 212     bool drained = isDrained();
 213     needToSignalDrained = !drained;
 214
 215     return drained;
 216 }
 217
 218 void
 219 Pipeline::drainResume()
 220 {
 221     DPRINTF(Drain, "Drain resume\n");
 222
 223     for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
 224         fetch1.wakeupFetch(tid);
 225     }
 226
 227     execute.drainResume();
 228 }
 229
 230 bool
 231 Pipeline::isDrained()
 232 {
 233     bool fetch1_drained = fetch1.isDrained();
 234     bool fetch2_drained = fetch2.isDrained();
 235     bool decode_drained = decode.isDrained();
 236     bool execute_drained = execute.isDrained();
 237
 238     bool f1_to_f2_drained = f1ToF2.empty();
 239     bool f2_to_f1_drained = f2ToF1.empty();
 240     bool f2_to_d_drained = f2ToD.empty();
 241     bool d_to_e_drained = dToE.empty();
 242
 243     bool ret = fetch1_drained && fetch2_drained &&
 244         decode_drained && execute_drained &&
 245         f1_to_f2_drained && f2_to_f1_drained &&
 246         f2_to_d_drained && d_to_e_drained;
 247
 248     DPRINTF(MinorCPU, "Pipeline undrained stages state:%s%s%s%s%s%s%s%s\n",
 249         (fetch1_drained ? "" : " Fetch1"),
 250         (fetch2_drained ? "" : " Fetch2"),
 251         (decode_drained ? "" : " Decode"),
 252         (execute_drained ? "" : " Execute"),
 253         (f1_to_f2_drained ? "" : " F1->F2"),
 254         (f2_to_f1_drained ? "" : " F2->F1"),
 255         (f2_to_d_drained ? "" : " F2->D"),
 256         (d_to_e_drained ? "" : " D->E")
 257         );
 258
 259     return ret;
 260 }
 261
 262 }