src/cpu/minor/pipeline.hh

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andrew Bardsley
  38  */
  39
  40 /**
  41  * @file
  42  *
  43  *  The constructed pipeline.  Kept out of MinorCPU to keep the interface
  44  *  between the CPU and its grubby implementation details clean.
  45  */
  46
  47 #ifndef __CPU_MINOR_PIPELINE_HH__
  48 #define __CPU_MINOR_PIPELINE_HH__
  49
  50 #include "cpu/minor/activity.hh"
  51 #include "cpu/minor/cpu.hh"
  52 #include "cpu/minor/decode.hh"
  53 #include "cpu/minor/execute.hh"
  54 #include "cpu/minor/fetch1.hh"
  55 #include "cpu/minor/fetch2.hh"
  56 #include "params/MinorCPU.hh"
  57 #include "sim/ticked_object.hh"
  58
  59 namespace Minor
  60 {
  61
  62 /**
  63  * @namespace Minor
  64  *
  65  * Minor contains all the definitions within the MinorCPU apart from the CPU
  66  * class itself
  67  */
  68
  69 /** The constructed pipeline.  Kept out of MinorCPU to keep the interface
  70  *  between the CPU and its grubby implementation details clean. */
  71 class Pipeline : public Ticked
  72 {
  73   protected:
  74     MinorCPU &cpu;
  75
  76     /** Allow cycles to be skipped when the pipeline is idle */
  77     bool allow_idling;
  78
  79     Latch<ForwardLineData> f1ToF2;
  80     Latch<BranchData> f2ToF1;
  81     Latch<ForwardInstData> f2ToD;
  82     Latch<ForwardInstData> dToE;
  83     Latch<BranchData> eToF1;
  84
  85     Execute execute;
  86     Decode decode;
  87     Fetch2 fetch2;
  88     Fetch1 fetch1;
  89
  90     /** Activity recording for the pipeline.  This is access through the CPU
  91      *  by the pipeline stages but belongs to the Pipeline as it is the
  92      *  cleanest place to initialise it */
  93     MinorActivityRecorder activityRecorder;
  94
  95   public:
  96     /** Enumerated ids of the 'stages' for the activity recorder */
  97     enum StageId
  98     {
  99         /* A stage representing wakeup of the whole processor */
 100         CPUStageId = 0,
 101         /* Real pipeline stages */
 102         Fetch1StageId, Fetch2StageId, DecodeStageId, ExecuteStageId,
 103         Num_StageId /* Stage count */
 104     };
 105
 106     /** True after drain is called but draining isn't complete */
 107     bool needToSignalDrained;
 108
 109   public:
 110     Pipeline(MinorCPU &cpu_, MinorCPUParams &params);
 111
 112   public:
 113     /** Wake up the Fetch unit.  This is needed on thread activation esp.
 114      *  after quiesce wakeup */
 115     void wakeupFetch();
 116
 117     /** Try to drain the CPU */
 118     unsigned int drain(DrainManager *manager);
 119
 120     void drainResume();
 121
 122     /** Test to see if the CPU is drained */
 123     bool isDrained();
 124
 125     /** A custom evaluate allows report in the right place (between
 126      *  stages and pipeline advance) */
 127     void evaluate();
 128
 129     void countCycles(Cycles delta) M5_ATTR_OVERRIDE
 130     {
 131         cpu.ppCycles->notify(delta);
 132     }
 133
 134     void minorTrace() const;
 135
 136     /** Functions below here are BaseCPU operations passed on to pipeline
 137      *  stages */
 138
 139     /** Return the IcachePort belonging to Fetch1 for the CPU */
 140     MinorCPU::MinorCPUPort &getInstPort();
 141     /** Return the DcachePort belonging to Execute for the CPU */
 142     MinorCPU::MinorCPUPort &getDataPort();
 143
 144     /** To give the activity recorder to the CPU */
 145     MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; }
 146 };
 147
 148 }
 149
 150 #endif /* __CPU_MINOR_PIPELINE_HH__ */