src/cpu/minor/pipeline.hh

   1 /*
   2  * Copyright (c) 2013-2014, 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /**
  39  * @file
  40  *
  41  *  The constructed pipeline.  Kept out of MinorCPU to keep the interface
  42  *  between the CPU and its grubby implementation details clean.
  43  */
  44
  45 #ifndef __CPU_MINOR_PIPELINE_HH__
  46 #define __CPU_MINOR_PIPELINE_HH__
  47
  48 #include "cpu/minor/activity.hh"
  49 #include "cpu/minor/cpu.hh"
  50 #include "cpu/minor/decode.hh"
  51 #include "cpu/minor/execute.hh"
  52 #include "cpu/minor/fetch1.hh"
  53 #include "cpu/minor/fetch2.hh"
  54 #include "params/MinorCPU.hh"
  55 #include "sim/ticked_object.hh"
  56
  57 namespace Minor
  58 {
  59
  60 /**
  61  * @namespace Minor
  62  *
  63  * Minor contains all the definitions within the MinorCPU apart from the CPU
  64  * class itself
  65  */
  66
  67 /** The constructed pipeline.  Kept out of MinorCPU to keep the interface
  68  *  between the CPU and its grubby implementation details clean. */
  69 class Pipeline : public Ticked
  70 {
  71   protected:
  72     MinorCPU &cpu;
  73
  74     /** Allow cycles to be skipped when the pipeline is idle */
  75     bool allow_idling;
  76
  77     Latch<ForwardLineData> f1ToF2;
  78     Latch<BranchData> f2ToF1;
  79     Latch<ForwardInstData> f2ToD;
  80     Latch<ForwardInstData> dToE;
  81     Latch<BranchData> eToF1;
  82
  83     Execute execute;
  84     Decode decode;
  85     Fetch2 fetch2;
  86     Fetch1 fetch1;
  87
  88     /** Activity recording for the pipeline.  This is access through the CPU
  89      *  by the pipeline stages but belongs to the Pipeline as it is the
  90      *  cleanest place to initialise it */
  91     MinorActivityRecorder activityRecorder;
  92
  93   public:
  94     /** Enumerated ids of the 'stages' for the activity recorder */
  95     enum StageId
  96     {
  97         /* A stage representing wakeup of the whole processor */
  98         CPUStageId = 0,
  99         /* Real pipeline stages */
 100         Fetch1StageId, Fetch2StageId, DecodeStageId, ExecuteStageId,
 101         Num_StageId /* Stage count */
 102     };
 103
 104     /** True after drain is called but draining isn't complete */
 105     bool needToSignalDrained;
 106
 107   public:
 108     Pipeline(MinorCPU &cpu_, MinorCPUParams &params);
 109
 110   public:
 111     /** Wake up the Fetch unit.  This is needed on thread activation esp.
 112      *  after quiesce wakeup */
 113     void wakeupFetch(ThreadID tid);
 114
 115     /** Try to drain the CPU */
 116     bool drain();
 117
 118     void drainResume();
 119
 120     /** Test to see if the CPU is drained */
 121     bool isDrained();
 122
 123     /** A custom evaluate allows report in the right place (between
 124      *  stages and pipeline advance) */
 125     void evaluate() override;
 126
 127     void minorTrace() const;
 128
 129     /** Stats registering */
 130     void regStats();
 131
 132     /** Functions below here are BaseCPU operations passed on to pipeline
 133      *  stages */
 134
 135     /** Return the IcachePort belonging to Fetch1 for the CPU */
 136     MinorCPU::MinorCPUPort &getInstPort();
 137     /** Return the DcachePort belonging to Execute for the CPU */
 138     MinorCPU::MinorCPUPort &getDataPort();
 139
 140     /** To give the activity recorder to the CPU */
 141     MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; }
 142 };
 143
 144 }
 145
 146 #endif /* __CPU_MINOR_PIPELINE_HH__ */