arch,cpu: Change setCPU to setThreadContext in Interrupts.
[gem5.git] / src / cpu / minor / stats.hh
1 /*
2 * Copyright (c) 2011-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /**
39 * @file
40 *
41 * The stats for MinorCPU separated from the CPU definition.
42 */
43
44 #ifndef __CPU_MINOR_STATS_HH__
45 #define __CPU_MINOR_STATS_HH__
46
47 #include "base/statistics.hh"
48 #include "cpu/base.hh"
49 #include "sim/ticked_object.hh"
50
51 namespace Minor
52 {
53
54 /** Currently unused stats class. */
55 class MinorStats
56 {
57 public:
58 /** Number of simulated instructions */
59 Stats::Scalar numInsts;
60
61 /** Number of simulated insts and microops */
62 Stats::Scalar numOps;
63
64 /** Number of ops discarded before committing */
65 Stats::Scalar numDiscardedOps;
66
67 /** Number of times fetch was asked to suspend by Execute */
68 Stats::Scalar numFetchSuspends;
69
70 /** Number of cycles in quiescent state */
71 Stats::Scalar quiesceCycles;
72
73 /** CPI/IPC for total cycle counts and macro insts */
74 Stats::Formula cpi;
75 Stats::Formula ipc;
76
77 /** Number of instructions by type (OpClass) */
78 Stats::Vector2d committedInstType;
79
80 public:
81 MinorStats();
82
83 public:
84 void regStats(const std::string &name, BaseCPU &baseCpu);
85 };
86
87 }
88
89 #endif /* __CPU_MINOR_STATS_HH__ */